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b42dfed8 FF |
1 | /* |
2 | * Broadcom BCM63xx SPI controller support | |
3 | * | |
cde4384e | 4 | * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> |
b42dfed8 FF |
5 | * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
b42dfed8 FF |
16 | */ |
17 | ||
18 | #include <linux/kernel.h> | |
b42dfed8 FF |
19 | #include <linux/clk.h> |
20 | #include <linux/io.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/completion.h> | |
27 | #include <linux/err.h> | |
cde4384e | 28 | #include <linux/pm_runtime.h> |
b42dfed8 FF |
29 | |
30 | #include <bcm63xx_dev_spi.h> | |
31 | ||
b17de076 JG |
32 | #define BCM63XX_SPI_MAX_PREPEND 15 |
33 | ||
b42dfed8 | 34 | struct bcm63xx_spi { |
b42dfed8 FF |
35 | struct completion done; |
36 | ||
37 | void __iomem *regs; | |
38 | int irq; | |
39 | ||
40 | /* Platform data */ | |
b42dfed8 | 41 | unsigned fifo_size; |
5a670445 FF |
42 | unsigned int msg_type_shift; |
43 | unsigned int msg_ctl_width; | |
b42dfed8 | 44 | |
b42dfed8 FF |
45 | /* data iomem */ |
46 | u8 __iomem *tx_io; | |
47 | const u8 __iomem *rx_io; | |
48 | ||
b42dfed8 FF |
49 | struct clk *clk; |
50 | struct platform_device *pdev; | |
51 | }; | |
52 | ||
53 | static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, | |
54 | unsigned int offset) | |
55 | { | |
56 | return bcm_readb(bs->regs + bcm63xx_spireg(offset)); | |
57 | } | |
58 | ||
59 | static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, | |
60 | unsigned int offset) | |
61 | { | |
62 | return bcm_readw(bs->regs + bcm63xx_spireg(offset)); | |
63 | } | |
64 | ||
65 | static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, | |
66 | u8 value, unsigned int offset) | |
67 | { | |
68 | bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); | |
69 | } | |
70 | ||
71 | static inline void bcm_spi_writew(struct bcm63xx_spi *bs, | |
72 | u16 value, unsigned int offset) | |
73 | { | |
74 | bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); | |
75 | } | |
76 | ||
77 | static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { | |
78 | { 20000000, SPI_CLK_20MHZ }, | |
79 | { 12500000, SPI_CLK_12_50MHZ }, | |
80 | { 6250000, SPI_CLK_6_250MHZ }, | |
81 | { 3125000, SPI_CLK_3_125MHZ }, | |
82 | { 1563000, SPI_CLK_1_563MHZ }, | |
83 | { 781000, SPI_CLK_0_781MHZ }, | |
84 | { 391000, SPI_CLK_0_391MHZ } | |
85 | }; | |
86 | ||
cde4384e FF |
87 | static void bcm63xx_spi_setup_transfer(struct spi_device *spi, |
88 | struct spi_transfer *t) | |
89 | { | |
90 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | |
cde4384e FF |
91 | u8 clk_cfg, reg; |
92 | int i; | |
93 | ||
b42dfed8 FF |
94 | /* Find the closest clock configuration */ |
95 | for (i = 0; i < SPI_CLK_MASK; i++) { | |
68792e2a | 96 | if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { |
b42dfed8 FF |
97 | clk_cfg = bcm63xx_spi_freq_table[i][1]; |
98 | break; | |
99 | } | |
100 | } | |
101 | ||
102 | /* No matching configuration found, default to lowest */ | |
103 | if (i == SPI_CLK_MASK) | |
104 | clk_cfg = SPI_CLK_0_391MHZ; | |
105 | ||
106 | /* clear existing clock configuration bits of the register */ | |
107 | reg = bcm_spi_readb(bs, SPI_CLK_CFG); | |
108 | reg &= ~SPI_CLK_MASK; | |
109 | reg |= clk_cfg; | |
110 | ||
111 | bcm_spi_writeb(bs, reg, SPI_CLK_CFG); | |
112 | dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", | |
68792e2a | 113 | clk_cfg, t->speed_hz); |
b42dfed8 FF |
114 | } |
115 | ||
116 | /* the spi->mode bits understood by this driver: */ | |
117 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
118 | ||
b17de076 JG |
119 | static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
120 | unsigned int num_transfers) | |
b42dfed8 FF |
121 | { |
122 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); | |
123 | u16 msg_ctl; | |
124 | u16 cmd; | |
c0fde3ba | 125 | u8 rx_tail; |
b17de076 JG |
126 | unsigned int i, timeout = 0, prepend_len = 0, len = 0; |
127 | struct spi_transfer *t = first; | |
128 | bool do_rx = false; | |
129 | bool do_tx = false; | |
b42dfed8 | 130 | |
cde4384e FF |
131 | /* Disable the CMD_DONE interrupt */ |
132 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
133 | ||
b42dfed8 FF |
134 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
135 | t->tx_buf, t->rx_buf, t->len); | |
136 | ||
b17de076 JG |
137 | if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
138 | prepend_len = t->len; | |
139 | ||
140 | /* prepare the buffer */ | |
141 | for (i = 0; i < num_transfers; i++) { | |
142 | if (t->tx_buf) { | |
143 | do_tx = true; | |
144 | memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); | |
145 | ||
146 | /* don't prepend more than one tx */ | |
147 | if (t != first) | |
148 | prepend_len = 0; | |
149 | } | |
150 | ||
151 | if (t->rx_buf) { | |
152 | do_rx = true; | |
153 | /* prepend is half-duplex write only */ | |
154 | if (t == first) | |
155 | prepend_len = 0; | |
156 | } | |
157 | ||
158 | len += t->len; | |
159 | ||
160 | t = list_entry(t->transfer_list.next, struct spi_transfer, | |
161 | transfer_list); | |
162 | } | |
163 | ||
aa0fe826 | 164 | reinit_completion(&bs->done); |
b42dfed8 FF |
165 | |
166 | /* Fill in the Message control register */ | |
b17de076 | 167 | msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
b42dfed8 | 168 | |
b17de076 | 169 | if (do_rx && do_tx && prepend_len == 0) |
5a670445 | 170 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
b17de076 | 171 | else if (do_rx) |
5a670445 | 172 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
b17de076 | 173 | else if (do_tx) |
5a670445 FF |
174 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
175 | ||
176 | switch (bs->msg_ctl_width) { | |
177 | case 8: | |
178 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); | |
179 | break; | |
180 | case 16: | |
181 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); | |
182 | break; | |
183 | } | |
b42dfed8 FF |
184 | |
185 | /* Issue the transfer */ | |
186 | cmd = SPI_CMD_START_IMMEDIATE; | |
b17de076 | 187 | cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
b42dfed8 FF |
188 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
189 | bcm_spi_writew(bs, cmd, SPI_CMD); | |
b42dfed8 | 190 | |
cde4384e FF |
191 | /* Enable the CMD_DONE interrupt */ |
192 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); | |
b42dfed8 | 193 | |
c0fde3ba JG |
194 | timeout = wait_for_completion_timeout(&bs->done, HZ); |
195 | if (!timeout) | |
196 | return -ETIMEDOUT; | |
197 | ||
20e9e78f | 198 | if (!do_rx) |
b17de076 JG |
199 | return 0; |
200 | ||
201 | len = 0; | |
202 | t = first; | |
c0fde3ba | 203 | /* Read out all the data */ |
b17de076 JG |
204 | for (i = 0; i < num_transfers; i++) { |
205 | if (t->rx_buf) | |
206 | memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); | |
207 | ||
208 | if (t != first || prepend_len == 0) | |
209 | len += t->len; | |
210 | ||
211 | t = list_entry(t->transfer_list.next, struct spi_transfer, | |
212 | transfer_list); | |
213 | } | |
c0fde3ba JG |
214 | |
215 | return 0; | |
b42dfed8 FF |
216 | } |
217 | ||
cde4384e FF |
218 | static int bcm63xx_spi_transfer_one(struct spi_master *master, |
219 | struct spi_message *m) | |
220 | { | |
221 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
b17de076 | 222 | struct spi_transfer *t, *first = NULL; |
cde4384e FF |
223 | struct spi_device *spi = m->spi; |
224 | int status = 0; | |
b17de076 JG |
225 | unsigned int n_transfers = 0, total_len = 0; |
226 | bool can_use_prepend = false; | |
227 | ||
228 | /* | |
229 | * This SPI controller does not support keeping CS active after a | |
230 | * transfer. | |
231 | * Work around this by merging as many transfers we can into one big | |
232 | * full-duplex transfers. | |
233 | */ | |
b42dfed8 | 234 | list_for_each_entry(t, &m->transfers, transfer_list) { |
b17de076 JG |
235 | if (!first) |
236 | first = t; | |
237 | ||
238 | n_transfers++; | |
239 | total_len += t->len; | |
240 | ||
241 | if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && | |
242 | first->len <= BCM63XX_SPI_MAX_PREPEND) | |
243 | can_use_prepend = true; | |
244 | else if (can_use_prepend && t->tx_buf) | |
245 | can_use_prepend = false; | |
246 | ||
c0fde3ba | 247 | /* we can only transfer one fifo worth of data */ |
b17de076 JG |
248 | if ((can_use_prepend && |
249 | total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || | |
250 | (!can_use_prepend && total_len > bs->fifo_size)) { | |
c0fde3ba | 251 | dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", |
b17de076 | 252 | total_len, bs->fifo_size); |
c0fde3ba JG |
253 | status = -EINVAL; |
254 | goto exit; | |
255 | } | |
cde4384e | 256 | |
b17de076 JG |
257 | /* all combined transfers have to have the same speed */ |
258 | if (t->speed_hz != first->speed_hz) { | |
259 | dev_err(&spi->dev, "unable to change speed between transfers\n"); | |
c0fde3ba JG |
260 | status = -EINVAL; |
261 | goto exit; | |
262 | } | |
cde4384e | 263 | |
b17de076 JG |
264 | /* CS will be deasserted directly after transfer */ |
265 | if (t->delay_usecs) { | |
266 | dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); | |
c0fde3ba JG |
267 | status = -EINVAL; |
268 | goto exit; | |
269 | } | |
cde4384e | 270 | |
b17de076 JG |
271 | if (t->cs_change || |
272 | list_is_last(&t->transfer_list, &m->transfers)) { | |
273 | /* configure adapter for a new transfer */ | |
274 | bcm63xx_spi_setup_transfer(spi, first); | |
cde4384e | 275 | |
b17de076 JG |
276 | /* send the data */ |
277 | status = bcm63xx_txrx_bufs(spi, first, n_transfers); | |
278 | if (status) | |
279 | goto exit; | |
280 | ||
281 | m->actual_length += total_len; | |
b42dfed8 | 282 | |
b17de076 JG |
283 | first = NULL; |
284 | n_transfers = 0; | |
285 | total_len = 0; | |
286 | can_use_prepend = false; | |
287 | } | |
cde4384e FF |
288 | } |
289 | exit: | |
290 | m->status = status; | |
291 | spi_finalize_current_message(master); | |
b42dfed8 | 292 | |
cde4384e | 293 | return 0; |
b42dfed8 FF |
294 | } |
295 | ||
296 | /* This driver supports single master mode only. Hence | |
297 | * CMD_DONE is the only interrupt we care about | |
298 | */ | |
299 | static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) | |
300 | { | |
301 | struct spi_master *master = (struct spi_master *)dev_id; | |
302 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); | |
303 | u8 intr; | |
b42dfed8 FF |
304 | |
305 | /* Read interupts and clear them immediately */ | |
306 | intr = bcm_spi_readb(bs, SPI_INT_STATUS); | |
307 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); | |
308 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
309 | ||
cde4384e FF |
310 | /* A transfer completed */ |
311 | if (intr & SPI_INTR_CMD_DONE) | |
312 | complete(&bs->done); | |
b42dfed8 FF |
313 | |
314 | return IRQ_HANDLED; | |
315 | } | |
316 | ||
317 | ||
fd4a319b | 318 | static int bcm63xx_spi_probe(struct platform_device *pdev) |
b42dfed8 FF |
319 | { |
320 | struct resource *r; | |
321 | struct device *dev = &pdev->dev; | |
8074cf06 | 322 | struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); |
b42dfed8 FF |
323 | int irq; |
324 | struct spi_master *master; | |
325 | struct clk *clk; | |
326 | struct bcm63xx_spi *bs; | |
327 | int ret; | |
328 | ||
b42dfed8 FF |
329 | irq = platform_get_irq(pdev, 0); |
330 | if (irq < 0) { | |
331 | dev_err(dev, "no irq\n"); | |
acf4fc6f | 332 | return -ENXIO; |
b42dfed8 FF |
333 | } |
334 | ||
acf4fc6f | 335 | clk = devm_clk_get(dev, "spi"); |
b42dfed8 FF |
336 | if (IS_ERR(clk)) { |
337 | dev_err(dev, "no clock for device\n"); | |
acf4fc6f | 338 | return PTR_ERR(clk); |
b42dfed8 FF |
339 | } |
340 | ||
341 | master = spi_alloc_master(dev, sizeof(*bs)); | |
342 | if (!master) { | |
343 | dev_err(dev, "out of memory\n"); | |
acf4fc6f | 344 | return -ENOMEM; |
b42dfed8 FF |
345 | } |
346 | ||
347 | bs = spi_master_get_devdata(master); | |
aa0fe826 | 348 | init_completion(&bs->done); |
b42dfed8 FF |
349 | |
350 | platform_set_drvdata(pdev, master); | |
351 | bs->pdev = pdev; | |
352 | ||
de0fa83c | 353 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b66c7730 JG |
354 | bs->regs = devm_ioremap_resource(&pdev->dev, r); |
355 | if (IS_ERR(bs->regs)) { | |
356 | ret = PTR_ERR(bs->regs); | |
b42dfed8 FF |
357 | goto out_err; |
358 | } | |
359 | ||
360 | bs->irq = irq; | |
361 | bs->clk = clk; | |
362 | bs->fifo_size = pdata->fifo_size; | |
363 | ||
364 | ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, | |
365 | pdev->name, master); | |
366 | if (ret) { | |
367 | dev_err(dev, "unable to request irq\n"); | |
368 | goto out_err; | |
369 | } | |
370 | ||
371 | master->bus_num = pdata->bus_num; | |
372 | master->num_chipselect = pdata->num_chipselect; | |
cde4384e | 373 | master->transfer_one_message = bcm63xx_spi_transfer_one; |
88a3a255 | 374 | master->mode_bits = MODEBITS; |
24778be2 | 375 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
5355d96d | 376 | master->auto_runtime_pm = true; |
5a670445 FF |
377 | bs->msg_type_shift = pdata->msg_type_shift; |
378 | bs->msg_ctl_width = pdata->msg_ctl_width; | |
b42dfed8 FF |
379 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); |
380 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); | |
b42dfed8 | 381 | |
5a670445 FF |
382 | switch (bs->msg_ctl_width) { |
383 | case 8: | |
384 | case 16: | |
385 | break; | |
386 | default: | |
387 | dev_err(dev, "unsupported MSG_CTL width: %d\n", | |
388 | bs->msg_ctl_width); | |
b435ff21 | 389 | goto out_err; |
5a670445 FF |
390 | } |
391 | ||
b42dfed8 | 392 | /* Initialize hardware */ |
ea01e8a4 JG |
393 | ret = clk_prepare_enable(bs->clk); |
394 | if (ret) | |
395 | goto out_err; | |
396 | ||
b42dfed8 FF |
397 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
398 | ||
399 | /* register and we are done */ | |
bca76931 | 400 | ret = devm_spi_register_master(dev, master); |
b42dfed8 FF |
401 | if (ret) { |
402 | dev_err(dev, "spi register failed\n"); | |
403 | goto out_clk_disable; | |
404 | } | |
405 | ||
61d15963 FF |
406 | dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", |
407 | r->start, irq, bs->fifo_size); | |
b42dfed8 FF |
408 | |
409 | return 0; | |
410 | ||
411 | out_clk_disable: | |
4fbb82a7 | 412 | clk_disable_unprepare(clk); |
b42dfed8 | 413 | out_err: |
b42dfed8 | 414 | spi_master_put(master); |
b42dfed8 FF |
415 | return ret; |
416 | } | |
417 | ||
fd4a319b | 418 | static int bcm63xx_spi_remove(struct platform_device *pdev) |
b42dfed8 | 419 | { |
9637b86f | 420 | struct spi_master *master = platform_get_drvdata(pdev); |
b42dfed8 FF |
421 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
422 | ||
423 | /* reset spi block */ | |
424 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); | |
b42dfed8 FF |
425 | |
426 | /* HW shutdown */ | |
4fbb82a7 | 427 | clk_disable_unprepare(bs->clk); |
b42dfed8 | 428 | |
b42dfed8 FF |
429 | return 0; |
430 | } | |
431 | ||
1bae2028 | 432 | #ifdef CONFIG_PM_SLEEP |
b42dfed8 FF |
433 | static int bcm63xx_spi_suspend(struct device *dev) |
434 | { | |
a1216394 | 435 | struct spi_master *master = dev_get_drvdata(dev); |
b42dfed8 FF |
436 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
437 | ||
96519957 FF |
438 | spi_master_suspend(master); |
439 | ||
4fbb82a7 | 440 | clk_disable_unprepare(bs->clk); |
b42dfed8 FF |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static int bcm63xx_spi_resume(struct device *dev) | |
446 | { | |
a1216394 | 447 | struct spi_master *master = dev_get_drvdata(dev); |
b42dfed8 | 448 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
ea01e8a4 | 449 | int ret; |
b42dfed8 | 450 | |
ea01e8a4 JG |
451 | ret = clk_prepare_enable(bs->clk); |
452 | if (ret) | |
453 | return ret; | |
b42dfed8 | 454 | |
96519957 FF |
455 | spi_master_resume(master); |
456 | ||
b42dfed8 FF |
457 | return 0; |
458 | } | |
1bae2028 | 459 | #endif |
b42dfed8 FF |
460 | |
461 | static const struct dev_pm_ops bcm63xx_spi_pm_ops = { | |
1bae2028 | 462 | SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) |
b42dfed8 FF |
463 | }; |
464 | ||
b42dfed8 FF |
465 | static struct platform_driver bcm63xx_spi_driver = { |
466 | .driver = { | |
467 | .name = "bcm63xx-spi", | |
1bae2028 | 468 | .pm = &bcm63xx_spi_pm_ops, |
b42dfed8 FF |
469 | }, |
470 | .probe = bcm63xx_spi_probe, | |
fd4a319b | 471 | .remove = bcm63xx_spi_remove, |
b42dfed8 FF |
472 | }; |
473 | ||
474 | module_platform_driver(bcm63xx_spi_driver); | |
475 | ||
476 | MODULE_ALIAS("platform:bcm63xx_spi"); | |
477 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
478 | MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); | |
479 | MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); | |
480 | MODULE_LICENSE("GPL"); |