[deliverable/linux.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>

#include <bcm63xx_dev_spi.h>

#define PFX		KBUILD_MODNAME

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	u32			speed_hz;
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static int bcm63xx_spi_check_transfer(struct spi_device *spi,
					struct spi_transfer *t)
{
	u8 bits_per_word;

	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
	if (bits_per_word != 8) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	if (spi->chip_select > spi->master->num_chipselect) {
		dev_err(&spi->dev, "%s, unsupported slave %d\n",
			__func__, spi->chip_select);
		return -EINVAL;
	}

	return 0;
}

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u32 hz;
	u8 clk_cfg, reg;
	int i;

	hz = (t) ? t->speed_hz : spi->max_speed_hz;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* No matching configuration found, default to lowest */
	if (i == SPI_CLK_MASK)
		clk_cfg = SPI_CLK_0_391MHZ;

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_spi_setup(struct spi_device *spi)
{
	struct bcm63xx_spi *bs;
	int ret;

	bs = spi_master_get_devdata(spi->master);

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	if (spi->mode & ~MODEBITS) {
		dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
			__func__, spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
		__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);

	return 0;
}

static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;
	u8 rx_tail;
	unsigned int timeout = 0;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	if (t->tx_buf)
		memcpy_toio(bs->tx_io, t->tx_buf, t->len);

	init_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);

	if (t->rx_buf && t->tx_buf)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (t->rx_buf)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (t->tx_buf)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	timeout = wait_for_completion_timeout(&bs->done, HZ);
	if (!timeout)
		return -ETIMEDOUT;

	/* read out all data */
	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);

	/* Read out all the data */
	if (rx_tail)
		memcpy_fromio(t->rx_ptr, bs->rx_io, rx_tail);

	return 0;
}

static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_get_sync(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_put(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t;
	struct spi_device *spi = m->spi;
	int status = 0;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		status = bcm63xx_spi_check_transfer(spi, t);
		if (status < 0)
			goto exit;

		/* we can only transfer one fifo worth of data */
		if (t->len > bs->fifo_size) {
			dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
				t->len, bs->fifo_size);
			status = -EINVAL;
			goto exit;
		}

		/* CS will be deasserted directly after transfer */
		if (t->delay_usecs) {
			dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
			status = -EINVAL;
			goto exit;
		}

		if (!t->cs_change &&
		    !list_is_last(&t->transfer_list, &m->transfers)) {
			dev_err(&spi->dev, "unable to keep CS asserted between transfers\n");
			status = -EINVAL;
			goto exit;
		}

		/* configure adapter for a new transfer */
		bcm63xx_spi_setup_transfer(spi, t);

		/* send the data */
		status = bcm63xx_txrx_bufs(spi, t);
		if (status)
			goto exit;

		m->actual_length += t->len;
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}


static int bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	struct device *dev = &pdev->dev;
	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(dev, "no iomem\n");
		ret = -ENXIO;
		goto out;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		ret = -ENXIO;
		goto out;
	}

	clk = clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		ret = PTR_ERR(clk);
		goto out;
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		ret = -ENOMEM;
		goto out_clk;
	}

	bs = spi_master_get_devdata(master);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	if (!devm_request_mem_region(&pdev->dev, r->start,
					resource_size(r), PFX)) {
		dev_err(dev, "iomem request failed\n");
		ret = -ENXIO;
		goto out_err;
	}

	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
							resource_size(r));
	if (!bs->regs) {
		dev_err(dev, "unable to ioremap regs\n");
		ret = -ENOMEM;
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->fifo_size = pdata->fifo_size;

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	master->setup = bcm63xx_spi_setup;
	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	bs->speed_hz = pdata->speed_hz;
	bs->msg_type_shift = pdata->msg_type_shift;
	bs->msg_ctl_width = pdata->msg_ctl_width;
	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));

	switch (bs->msg_ctl_width) {
	case 8:
	case 16:
		break;
	default:
		dev_err(dev, "unsupported MSG_CTL width: %d\n",
			 bs->msg_ctl_width);
		goto out_clk_disable;
	}

	/* Initialize hardware */
	clk_enable(bs->clk);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = spi_register_master(master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
		 r->start, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable(clk);
out_err:
	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
out_clk:
	clk_put(clk);
out:
	return ret;
}

static int bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_unregister_master(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable(bs->clk);
	clk_put(bs->clk);

	platform_set_drvdata(pdev, 0);

	spi_master_put(master);

	return 0;
}

#ifdef CONFIG_PM
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	clk_enable(bs->clk);

	spi_master_resume(master);

	return 0;
}

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	.suspend	= bcm63xx_spi_suspend,
	.resume		= bcm63xx_spi_resume,
};

#define BCM63XX_SPI_PM_OPS	(&bcm63xx_spi_pm_ops)
#else
#define BCM63XX_SPI_PM_OPS	NULL
#endif

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.owner	= THIS_MODULE,
		.pm	= BCM63XX_SPI_PM_OPS,
	},
	.probe		= bcm63xx_spi_probe,
	.remove		= bcm63xx_spi_remove,
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the
	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/clk.h>
	25	#include <linux/io.h>
	26	#include <linux/module.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/delay.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/spi/spi.h>
	31	#include <linux/completion.h>
	32	#include <linux/err.h>
cde4384e FF	33	#include <linux/workqueue.h>
cde4384e FF	34	#include <linux/pm_runtime.h>
b42dfed8 FF	35
	36	#include <bcm63xx_dev_spi.h>
	37
	38	#define PFX KBUILD_MODNAME
b42dfed8 FF	39
b42dfed8 FF	40	struct bcm63xx_spi {
b42dfed8 FF	41	struct completion done;
	42
	43	void __iomem *regs;
	44	int irq;
	45
	46	/* Platform data */
	47	u32 speed_hz;
	48	unsigned fifo_size;
5a670445 FF	49	unsigned int msg_type_shift;
5a670445 FF	50	unsigned int msg_ctl_width;
b42dfed8	51
b42dfed8 FF	52	/* data iomem */
	53	u8 __iomem *tx_io;
	54	const u8 __iomem *rx_io;
	55
b42dfed8 FF	56	struct clk *clk;
	57	struct platform_device *pdev;
	58	};
	59
	60	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
	61	unsigned int offset)
	62	{
	63	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
	64	}
	65
	66	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	67	unsigned int offset)
	68	{
	69	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
	70	}
	71
	72	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	73	u8 value, unsigned int offset)
	74	{
	75	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
	76	}
	77
	78	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	79	u16 value, unsigned int offset)
	80	{
	81	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
	82	}
	83
	84	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	85	{ 20000000, SPI_CLK_20MHZ },
	86	{ 12500000, SPI_CLK_12_50MHZ },
	87	{ 6250000, SPI_CLK_6_250MHZ },
	88	{ 3125000, SPI_CLK_3_125MHZ },
	89	{ 1563000, SPI_CLK_1_563MHZ },
	90	{ 781000, SPI_CLK_0_781MHZ },
	91	{ 391000, SPI_CLK_0_391MHZ }
	92	};
	93
cde4384e FF	94	static int bcm63xx_spi_check_transfer(struct spi_device *spi,
cde4384e FF	95	struct spi_transfer *t)
b42dfed8	96	{
b42dfed8	97	u8 bits_per_word;
b42dfed8 FF	98
b42dfed8 FF	99	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
b42dfed8 FF	100	if (bits_per_word != 8) {
	101	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
	102	__func__, bits_per_word);
	103	return -EINVAL;
	104	}
	105
	106	if (spi->chip_select > spi->master->num_chipselect) {
	107	dev_err(&spi->dev, "%s, unsupported slave %d\n",
	108	__func__, spi->chip_select);
	109	return -EINVAL;
	110	}
	111
cde4384e FF	112	return 0;
	113	}
	114
	115	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	116	struct spi_transfer *t)
	117	{
	118	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	119	u32 hz;
	120	u8 clk_cfg, reg;
	121	int i;
	122
	123	hz = (t) ? t->speed_hz : spi->max_speed_hz;
	124
b42dfed8 FF	125	/* Find the closest clock configuration */
b42dfed8 FF	126	for (i = 0; i < SPI_CLK_MASK; i++) {
d76ea24a	127	if (hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	128	clk_cfg = bcm63xx_spi_freq_table[i][1];
	129	break;
	130	}
	131	}
	132
	133	/* No matching configuration found, default to lowest */
	134	if (i == SPI_CLK_MASK)
	135	clk_cfg = SPI_CLK_0_391MHZ;
	136
	137	/* clear existing clock configuration bits of the register */
	138	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	139	reg &= ~SPI_CLK_MASK;
	140	reg \|= clk_cfg;
	141
	142	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	143	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
	144	clk_cfg, hz);
b42dfed8 FF	145	}
	146
	147	/* the spi->mode bits understood by this driver: */
	148	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	149
	150	static int bcm63xx_spi_setup(struct spi_device *spi)
	151	{
	152	struct bcm63xx_spi *bs;
	153	int ret;
	154
	155	bs = spi_master_get_devdata(spi->master);
	156
b42dfed8 FF	157	if (!spi->bits_per_word)
	158	spi->bits_per_word = 8;
	159
	160	if (spi->mode & ~MODEBITS) {
	161	dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
	162	__func__, spi->mode & ~MODEBITS);
	163	return -EINVAL;
	164	}
	165
b42dfed8 FF	166	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
	167	__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
	168
	169	return 0;
	170	}
	171
c0fde3ba	172	static int bcm63xx_txrx_bufs(struct spi_device spi, struct spi_transfer t)
b42dfed8 FF	173	{
	174	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	175	u16 msg_ctl;
	176	u16 cmd;
c0fde3ba JG	177	u8 rx_tail;
c0fde3ba JG	178	unsigned int timeout = 0;
b42dfed8	179
cde4384e FF	180	/* Disable the CMD_DONE interrupt */
	181	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	182
b42dfed8 FF	183	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	184	t->tx_buf, t->rx_buf, t->len);
	185
c0fde3ba JG	186	if (t->tx_buf)
c0fde3ba JG	187	memcpy_toio(bs->tx_io, t->tx_buf, t->len);
b42dfed8	188
cde4384e	189	init_completion(&bs->done);
b42dfed8 FF	190
	191	/* Fill in the Message control register */
	192	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
	193
	194	if (t->rx_buf && t->tx_buf)
5a670445	195	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b42dfed8	196	else if (t->rx_buf)
5a670445	197	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b42dfed8	198	else if (t->tx_buf)
5a670445 FF	199	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	200
	201	switch (bs->msg_ctl_width) {
	202	case 8:
	203	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	204	break;
	205	case 16:
	206	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	207	break;
	208	}
b42dfed8 FF	209
	210	/* Issue the transfer */
	211	cmd = SPI_CMD_START_IMMEDIATE;
	212	cmd \|= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	213	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	214	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	215
cde4384e FF	216	/* Enable the CMD_DONE interrupt */
cde4384e FF	217	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8	218
c0fde3ba JG	219	timeout = wait_for_completion_timeout(&bs->done, HZ);
	220	if (!timeout)
	221	return -ETIMEDOUT;
	222
	223	/* read out all data */
	224	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
	225
	226	/* Read out all the data */
	227	if (rx_tail)
	228	memcpy_fromio(t->rx_ptr, bs->rx_io, rx_tail);
	229
	230	return 0;
b42dfed8 FF	231	}
b42dfed8 FF	232
cde4384e	233	static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
b42dfed8	234	{
cde4384e	235	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8	236
cde4384e	237	pm_runtime_get_sync(&bs->pdev->dev);
b42dfed8	238
cde4384e FF	239	return 0;
	240	}
	241
	242	static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
	243	{
	244	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	245
	246	pm_runtime_put(&bs->pdev->dev);
	247
	248	return 0;
	249	}
	250
	251	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	252	struct spi_message *m)
	253	{
	254	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	255	struct spi_transfer *t;
	256	struct spi_device *spi = m->spi;
	257	int status = 0;
b42dfed8 FF	258
b42dfed8 FF	259	list_for_each_entry(t, &m->transfers, transfer_list) {
cde4384e FF	260	status = bcm63xx_spi_check_transfer(spi, t);
	261	if (status < 0)
	262	goto exit;
	263
c0fde3ba JG	264	/* we can only transfer one fifo worth of data */
	265	if (t->len > bs->fifo_size) {
	266	dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
	267	t->len, bs->fifo_size);
	268	status = -EINVAL;
	269	goto exit;
	270	}
cde4384e	271
c0fde3ba JG	272	/* CS will be deasserted directly after transfer */
	273	if (t->delay_usecs) {
	274	dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
	275	status = -EINVAL;
	276	goto exit;
	277	}
cde4384e	278
c0fde3ba JG	279	if (!t->cs_change &&
	280	!list_is_last(&t->transfer_list, &m->transfers)) {
	281	dev_err(&spi->dev, "unable to keep CS asserted between transfers\n");
	282	status = -EINVAL;
	283	goto exit;
	284	}
cde4384e	285
c0fde3ba JG	286	/* configure adapter for a new transfer */
c0fde3ba JG	287	bcm63xx_spi_setup_transfer(spi, t);
cde4384e	288
c0fde3ba JG	289	/* send the data */
	290	status = bcm63xx_txrx_bufs(spi, t);
	291	if (status)
	292	goto exit;
b42dfed8	293
cde4384e FF	294	m->actual_length += t->len;
	295	}
	296	exit:
	297	m->status = status;
	298	spi_finalize_current_message(master);
b42dfed8	299
cde4384e	300	return 0;
b42dfed8 FF	301	}
	302
	303	/* This driver supports single master mode only. Hence
	304	* CMD_DONE is the only interrupt we care about
	305	*/
	306	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	307	{
	308	struct spi_master master = (struct spi_master )dev_id;
	309	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	310	u8 intr;
b42dfed8 FF	311
	312	/* Read interupts and clear them immediately */
	313	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	314	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	315	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	316
cde4384e FF	317	/* A transfer completed */
	318	if (intr & SPI_INTR_CMD_DONE)
	319	complete(&bs->done);
b42dfed8 FF	320
	321	return IRQ_HANDLED;
	322	}
	323
	324
fd4a319b	325	static int bcm63xx_spi_probe(struct platform_device *pdev)
b42dfed8 FF	326	{
	327	struct resource *r;
	328	struct device *dev = &pdev->dev;
	329	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	330	int irq;
	331	struct spi_master *master;
	332	struct clk *clk;
	333	struct bcm63xx_spi *bs;
	334	int ret;
	335
	336	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	337	if (!r) {
	338	dev_err(dev, "no iomem\n");
	339	ret = -ENXIO;
	340	goto out;
	341	}
	342
	343	irq = platform_get_irq(pdev, 0);
	344	if (irq < 0) {
	345	dev_err(dev, "no irq\n");
	346	ret = -ENXIO;
	347	goto out;
	348	}
	349
	350	clk = clk_get(dev, "spi");
	351	if (IS_ERR(clk)) {
	352	dev_err(dev, "no clock for device\n");
	353	ret = PTR_ERR(clk);
	354	goto out;
	355	}
	356
	357	master = spi_alloc_master(dev, sizeof(*bs));
	358	if (!master) {
	359	dev_err(dev, "out of memory\n");
	360	ret = -ENOMEM;
	361	goto out_clk;
	362	}
	363
	364	bs = spi_master_get_devdata(master);
b42dfed8 FF	365
	366	platform_set_drvdata(pdev, master);
	367	bs->pdev = pdev;
	368
	369	if (!devm_request_mem_region(&pdev->dev, r->start,
	370	resource_size(r), PFX)) {
	371	dev_err(dev, "iomem request failed\n");
	372	ret = -ENXIO;
	373	goto out_err;
	374	}
	375
	376	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
	377	resource_size(r));
	378	if (!bs->regs) {
	379	dev_err(dev, "unable to ioremap regs\n");
	380	ret = -ENOMEM;
	381	goto out_err;
	382	}
	383
	384	bs->irq = irq;
	385	bs->clk = clk;
	386	bs->fifo_size = pdata->fifo_size;
	387
	388	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	389	pdev->name, master);
	390	if (ret) {
	391	dev_err(dev, "unable to request irq\n");
	392	goto out_err;
	393	}
	394
	395	master->bus_num = pdata->bus_num;
	396	master->num_chipselect = pdata->num_chipselect;
	397	master->setup = bcm63xx_spi_setup;
cde4384e FF	398	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	399	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	400	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	401	master->mode_bits = MODEBITS;
b42dfed8	402	bs->speed_hz = pdata->speed_hz;
5a670445 FF	403	bs->msg_type_shift = pdata->msg_type_shift;
5a670445 FF	404	bs->msg_ctl_width = pdata->msg_ctl_width;
b42dfed8 FF	405	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
b42dfed8 FF	406	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
b42dfed8	407
5a670445 FF	408	switch (bs->msg_ctl_width) {
	409	case 8:
	410	case 16:
	411	break;
	412	default:
	413	dev_err(dev, "unsupported MSG_CTL width: %d\n",
	414	bs->msg_ctl_width);
	415	goto out_clk_disable;
	416	}
	417
b42dfed8 FF	418	/* Initialize hardware */
	419	clk_enable(bs->clk);
	420	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	421
	422	/* register and we are done */
	423	ret = spi_register_master(master);
	424	if (ret) {
	425	dev_err(dev, "spi register failed\n");
	426	goto out_clk_disable;
	427	}
	428
61d15963 FF	429	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
61d15963 FF	430	r->start, irq, bs->fifo_size);
b42dfed8 FF	431
	432	return 0;
	433
	434	out_clk_disable:
	435	clk_disable(clk);
	436	out_err:
	437	platform_set_drvdata(pdev, NULL);
	438	spi_master_put(master);
	439	out_clk:
	440	clk_put(clk);
	441	out:
	442	return ret;
	443	}
	444
fd4a319b	445	static int bcm63xx_spi_remove(struct platform_device *pdev)
b42dfed8	446	{
1f682378	447	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
b42dfed8 FF	448	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	449
1e41dc0e FF	450	spi_unregister_master(master);
1e41dc0e FF	451
b42dfed8 FF	452	/* reset spi block */
b42dfed8 FF	453	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	454
	455	/* HW shutdown */
	456	clk_disable(bs->clk);
	457	clk_put(bs->clk);
	458
b42dfed8	459	platform_set_drvdata(pdev, 0);
b42dfed8	460
1f682378 GR	461	spi_master_put(master);
1f682378 GR	462
b42dfed8 FF	463	return 0;
	464	}
	465
	466	#ifdef CONFIG_PM
	467	static int bcm63xx_spi_suspend(struct device *dev)
	468	{
	469	struct spi_master *master =
	470	platform_get_drvdata(to_platform_device(dev));
	471	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	472
96519957 FF	473	spi_master_suspend(master);
96519957 FF	474
b42dfed8 FF	475	clk_disable(bs->clk);
	476
	477	return 0;
	478	}
	479
	480	static int bcm63xx_spi_resume(struct device *dev)
	481	{
	482	struct spi_master *master =
	483	platform_get_drvdata(to_platform_device(dev));
	484	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	485
	486	clk_enable(bs->clk);
	487
96519957 FF	488	spi_master_resume(master);
96519957 FF	489
b42dfed8 FF	490	return 0;
	491	}
	492
	493	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	494	.suspend = bcm63xx_spi_suspend,
	495	.resume = bcm63xx_spi_resume,
	496	};
	497
	498	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
	499	#else
	500	#define BCM63XX_SPI_PM_OPS NULL
	501	#endif
	502
	503	static struct platform_driver bcm63xx_spi_driver = {
	504	.driver = {
	505	.name = "bcm63xx-spi",
	506	.owner = THIS_MODULE,
	507	.pm = BCM63XX_SPI_PM_OPS,
	508	},
	509	.probe = bcm63xx_spi_probe,
fd4a319b	510	.remove = bcm63xx_spi_remove,
b42dfed8 FF	511	};
	512
	513	module_platform_driver(bcm63xx_spi_driver);
	514
	515	MODULE_ALIAS("platform:bcm63xx_spi");
	516	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	517	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	518	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	519	MODULE_LICENSE("GPL");