[deliverable/linux.git] / drivers / spi / spi-bcm63xx.c

/*
 * Broadcom BCM63xx SPI controller support
 *
 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the
 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/workqueue.h>
#include <linux/pm_runtime.h>

#include <bcm63xx_dev_spi.h>

#define PFX		KBUILD_MODNAME

struct bcm63xx_spi {
	struct completion	done;

	void __iomem		*regs;
	int			irq;

	/* Platform data */
	u32			speed_hz;
	unsigned		fifo_size;
	unsigned int		msg_type_shift;
	unsigned int		msg_ctl_width;

	/* Data buffers */
	const unsigned char	*tx_ptr;
	unsigned char		*rx_ptr;

	/* data iomem */
	u8 __iomem		*tx_io;
	const u8 __iomem	*rx_io;

	int			remaining_bytes;

	struct clk		*clk;
	struct platform_device	*pdev;
};

static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
}

static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
				unsigned int offset)
{
	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
				  u8 value, unsigned int offset)
{
	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
}

static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
				  u16 value, unsigned int offset)
{
	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
}

static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	{ 20000000, SPI_CLK_20MHZ },
	{ 12500000, SPI_CLK_12_50MHZ },
	{  6250000, SPI_CLK_6_250MHZ },
	{  3125000, SPI_CLK_3_125MHZ },
	{  1563000, SPI_CLK_1_563MHZ },
	{   781000, SPI_CLK_0_781MHZ },
	{   391000, SPI_CLK_0_391MHZ }
};

static int bcm63xx_spi_check_transfer(struct spi_device *spi,
					struct spi_transfer *t)
{
	u8 bits_per_word;

	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
	if (bits_per_word != 8) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	if (spi->chip_select > spi->master->num_chipselect) {
		dev_err(&spi->dev, "%s, unsupported slave %d\n",
			__func__, spi->chip_select);
		return -EINVAL;
	}

	return 0;
}

static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
				      struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u32 hz;
	u8 clk_cfg, reg;
	int i;

	hz = (t) ? t->speed_hz : spi->max_speed_hz;

	/* Find the closest clock configuration */
	for (i = 0; i < SPI_CLK_MASK; i++) {
		if (hz >= bcm63xx_spi_freq_table[i][0]) {
			clk_cfg = bcm63xx_spi_freq_table[i][1];
			break;
		}
	}

	/* No matching configuration found, default to lowest */
	if (i == SPI_CLK_MASK)
		clk_cfg = SPI_CLK_0_391MHZ;

	/* clear existing clock configuration bits of the register */
	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	reg &= ~SPI_CLK_MASK;
	reg |= clk_cfg;

	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
		clk_cfg, hz);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS (SPI_CPOL | SPI_CPHA)

static int bcm63xx_spi_setup(struct spi_device *spi)
{
	struct bcm63xx_spi *bs;
	int ret;

	bs = spi_master_get_devdata(spi->master);

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	if (spi->mode & ~MODEBITS) {
		dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
			__func__, spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	ret = bcm63xx_spi_check_transfer(spi, NULL);
	if (ret < 0) {
		dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode & ~MODEBITS);
		return ret;
	}

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
		__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);

	return 0;
}

/* Fill the TX FIFO with as many bytes as possible */
static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
{
	u8 size;

	/* Fill the Tx FIFO with as many bytes as possible */
	size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
		bs->fifo_size;
	memcpy_toio(bs->tx_io, bs->tx_ptr, size);
	bs->remaining_bytes -= size;
}

static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
					struct spi_transfer *t)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	u16 msg_ctl;
	u16 cmd;

	/* Disable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	/* Transmitter is inhibited */
	bs->tx_ptr = t->tx_buf;
	bs->rx_ptr = t->rx_buf;

	if (t->tx_buf) {
		bs->remaining_bytes = t->len;
		bcm63xx_spi_fill_tx_fifo(bs);
	}

	init_completion(&bs->done);

	/* Fill in the Message control register */
	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);

	if (t->rx_buf && t->tx_buf)
		msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
	else if (t->rx_buf)
		msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
	else if (t->tx_buf)
		msg_ctl |= (SPI_HD_W << bs->msg_type_shift);

	switch (bs->msg_ctl_width) {
	case 8:
		bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
		break;
	case 16:
		bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
		break;
	}

	/* Issue the transfer */
	cmd = SPI_CMD_START_IMMEDIATE;
	cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	bcm_spi_writew(bs, cmd, SPI_CMD);

	/* Enable the CMD_DONE interrupt */
	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);

	return t->len - bs->remaining_bytes;
}

static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_get_sync(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	pm_runtime_put(&bs->pdev->dev);

	return 0;
}

static int bcm63xx_spi_transfer_one(struct spi_master *master,
					struct spi_message *m)
{
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *t;
	struct spi_device *spi = m->spi;
	int status = 0;
	unsigned int timeout = 0;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		unsigned int len = t->len;
		u8 rx_tail;

		status = bcm63xx_spi_check_transfer(spi, t);
		if (status < 0)
			goto exit;

		/* configure adapter for a new transfer */
		bcm63xx_spi_setup_transfer(spi, t);

		while (len) {
			/* send the data */
			len -= bcm63xx_txrx_bufs(spi, t);

			timeout = wait_for_completion_timeout(&bs->done, HZ);
			if (!timeout) {
				status = -ETIMEDOUT;
				goto exit;
			}

			/* read out all data */
			rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);

			/* Read out all the data */
			if (rx_tail)
				memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
		}

		m->actual_length += t->len;
	}
exit:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

/* This driver supports single master mode only. Hence
 * CMD_DONE is the only interrupt we care about
 */
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = (struct spi_master *)dev_id;
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	u8 intr;

	/* Read interupts and clear them immediately */
	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* A transfer completed */
	if (intr & SPI_INTR_CMD_DONE)
		complete(&bs->done);

	return IRQ_HANDLED;
}


static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
{
	struct resource *r;
	struct device *dev = &pdev->dev;
	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	int irq;
	struct spi_master *master;
	struct clk *clk;
	struct bcm63xx_spi *bs;
	int ret;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(dev, "no iomem\n");
		ret = -ENXIO;
		goto out;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "no irq\n");
		ret = -ENXIO;
		goto out;
	}

	clk = clk_get(dev, "spi");
	if (IS_ERR(clk)) {
		dev_err(dev, "no clock for device\n");
		ret = PTR_ERR(clk);
		goto out;
	}

	master = spi_alloc_master(dev, sizeof(*bs));
	if (!master) {
		dev_err(dev, "out of memory\n");
		ret = -ENOMEM;
		goto out_clk;
	}

	bs = spi_master_get_devdata(master);

	platform_set_drvdata(pdev, master);
	bs->pdev = pdev;

	if (!devm_request_mem_region(&pdev->dev, r->start,
					resource_size(r), PFX)) {
		dev_err(dev, "iomem request failed\n");
		ret = -ENXIO;
		goto out_err;
	}

	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
							resource_size(r));
	if (!bs->regs) {
		dev_err(dev, "unable to ioremap regs\n");
		ret = -ENOMEM;
		goto out_err;
	}

	bs->irq = irq;
	bs->clk = clk;
	bs->fifo_size = pdata->fifo_size;

	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
							pdev->name, master);
	if (ret) {
		dev_err(dev, "unable to request irq\n");
		goto out_err;
	}

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;
	master->setup = bcm63xx_spi_setup;
	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	master->transfer_one_message = bcm63xx_spi_transfer_one;
	master->mode_bits = MODEBITS;
	bs->speed_hz = pdata->speed_hz;
	bs->msg_type_shift = pdata->msg_type_shift;
	bs->msg_ctl_width = pdata->msg_ctl_width;
	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));

	switch (bs->msg_ctl_width) {
	case 8:
	case 16:
		break;
	default:
		dev_err(dev, "unsupported MSG_CTL width: %d\n",
			 bs->msg_ctl_width);
		goto out_clk_disable;
	}

	/* Initialize hardware */
	clk_enable(bs->clk);
	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);

	/* register and we are done */
	ret = spi_register_master(master);
	if (ret) {
		dev_err(dev, "spi register failed\n");
		goto out_clk_disable;
	}

	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
		 r->start, irq, bs->fifo_size);

	return 0;

out_clk_disable:
	clk_disable(clk);
out_err:
	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
out_clk:
	clk_put(clk);
out:
	return ret;
}

static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	spi_unregister_master(master);

	/* reset spi block */
	bcm_spi_writeb(bs, 0, SPI_INT_MASK);

	/* HW shutdown */
	clk_disable(bs->clk);
	clk_put(bs->clk);

	platform_set_drvdata(pdev, 0);

	spi_master_put(master);

	return 0;
}

#ifdef CONFIG_PM
static int bcm63xx_spi_suspend(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	clk_disable(bs->clk);

	return 0;
}

static int bcm63xx_spi_resume(struct device *dev)
{
	struct spi_master *master =
			platform_get_drvdata(to_platform_device(dev));
	struct bcm63xx_spi *bs = spi_master_get_devdata(master);

	clk_enable(bs->clk);

	return 0;
}

static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	.suspend	= bcm63xx_spi_suspend,
	.resume		= bcm63xx_spi_resume,
};

#define BCM63XX_SPI_PM_OPS	(&bcm63xx_spi_pm_ops)
#else
#define BCM63XX_SPI_PM_OPS	NULL
#endif

static struct platform_driver bcm63xx_spi_driver = {
	.driver = {
		.name	= "bcm63xx-spi",
		.owner	= THIS_MODULE,
		.pm	= BCM63XX_SPI_PM_OPS,
	},
	.probe		= bcm63xx_spi_probe,
	.remove		= __devexit_p(bcm63xx_spi_remove),
};

module_platform_driver(bcm63xx_spi_driver);

MODULE_ALIAS("platform:bcm63xx_spi");
MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b42dfed8 FF	1	/*
	2	* Broadcom BCM63xx SPI controller support
	3	*
cde4384e	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
b42dfed8 FF	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version 2
	10	* of the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the
	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/init.h>
	24	#include <linux/clk.h>
	25	#include <linux/io.h>
	26	#include <linux/module.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/delay.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/spi/spi.h>
	31	#include <linux/completion.h>
	32	#include <linux/err.h>
cde4384e FF	33	#include <linux/workqueue.h>
cde4384e FF	34	#include <linux/pm_runtime.h>
b42dfed8 FF	35
	36	#include <bcm63xx_dev_spi.h>
	37
	38	#define PFX KBUILD_MODNAME
b42dfed8 FF	39
b42dfed8 FF	40	struct bcm63xx_spi {
b42dfed8 FF	41	struct completion done;
	42
	43	void __iomem *regs;
	44	int irq;
	45
	46	/* Platform data */
	47	u32 speed_hz;
	48	unsigned fifo_size;
5a670445 FF	49	unsigned int msg_type_shift;
5a670445 FF	50	unsigned int msg_ctl_width;
b42dfed8 FF	51
	52	/* Data buffers */
	53	const unsigned char *tx_ptr;
	54	unsigned char *rx_ptr;
	55
	56	/* data iomem */
	57	u8 __iomem *tx_io;
	58	const u8 __iomem *rx_io;
	59
	60	int remaining_bytes;
	61
	62	struct clk *clk;
	63	struct platform_device *pdev;
	64	};
	65
	66	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
	67	unsigned int offset)
	68	{
	69	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
	70	}
	71
	72	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
	73	unsigned int offset)
	74	{
	75	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
	76	}
	77
	78	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
	79	u8 value, unsigned int offset)
	80	{
	81	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
	82	}
	83
	84	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
	85	u16 value, unsigned int offset)
	86	{
	87	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
	88	}
	89
	90	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
	91	{ 20000000, SPI_CLK_20MHZ },
	92	{ 12500000, SPI_CLK_12_50MHZ },
	93	{ 6250000, SPI_CLK_6_250MHZ },
	94	{ 3125000, SPI_CLK_3_125MHZ },
	95	{ 1563000, SPI_CLK_1_563MHZ },
	96	{ 781000, SPI_CLK_0_781MHZ },
	97	{ 391000, SPI_CLK_0_391MHZ }
	98	};
	99
cde4384e FF	100	static int bcm63xx_spi_check_transfer(struct spi_device *spi,
cde4384e FF	101	struct spi_transfer *t)
b42dfed8	102	{
b42dfed8	103	u8 bits_per_word;
b42dfed8 FF	104
b42dfed8 FF	105	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
b42dfed8 FF	106	if (bits_per_word != 8) {
	107	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
	108	__func__, bits_per_word);
	109	return -EINVAL;
	110	}
	111
	112	if (spi->chip_select > spi->master->num_chipselect) {
	113	dev_err(&spi->dev, "%s, unsupported slave %d\n",
	114	__func__, spi->chip_select);
	115	return -EINVAL;
	116	}
	117
cde4384e FF	118	return 0;
	119	}
	120
	121	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
	122	struct spi_transfer *t)
	123	{
	124	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	125	u32 hz;
	126	u8 clk_cfg, reg;
	127	int i;
	128
	129	hz = (t) ? t->speed_hz : spi->max_speed_hz;
	130
b42dfed8 FF	131	/* Find the closest clock configuration */
b42dfed8 FF	132	for (i = 0; i < SPI_CLK_MASK; i++) {
d76ea24a	133	if (hz >= bcm63xx_spi_freq_table[i][0]) {
b42dfed8 FF	134	clk_cfg = bcm63xx_spi_freq_table[i][1];
	135	break;
	136	}
	137	}
	138
	139	/* No matching configuration found, default to lowest */
	140	if (i == SPI_CLK_MASK)
	141	clk_cfg = SPI_CLK_0_391MHZ;
	142
	143	/* clear existing clock configuration bits of the register */
	144	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
	145	reg &= ~SPI_CLK_MASK;
	146	reg \|= clk_cfg;
	147
	148	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
	149	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
	150	clk_cfg, hz);
b42dfed8 FF	151	}
	152
	153	/* the spi->mode bits understood by this driver: */
	154	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
	155
	156	static int bcm63xx_spi_setup(struct spi_device *spi)
	157	{
	158	struct bcm63xx_spi *bs;
	159	int ret;
	160
	161	bs = spi_master_get_devdata(spi->master);
	162
b42dfed8 FF	163	if (!spi->bits_per_word)
	164	spi->bits_per_word = 8;
	165
	166	if (spi->mode & ~MODEBITS) {
	167	dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
	168	__func__, spi->mode & ~MODEBITS);
	169	return -EINVAL;
	170	}
	171
cde4384e	172	ret = bcm63xx_spi_check_transfer(spi, NULL);
b42dfed8 FF	173	if (ret < 0) {
	174	dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
	175	spi->mode & ~MODEBITS);
	176	return ret;
	177	}
	178
	179	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
	180	__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
	181
	182	return 0;
	183	}
	184
	185	/* Fill the TX FIFO with as many bytes as possible */
	186	static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
	187	{
	188	u8 size;
	189
	190	/* Fill the Tx FIFO with as many bytes as possible */
	191	size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
	192	bs->fifo_size;
	193	memcpy_toio(bs->tx_io, bs->tx_ptr, size);
	194	bs->remaining_bytes -= size;
	195	}
	196
cde4384e FF	197	static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
cde4384e FF	198	struct spi_transfer *t)
b42dfed8 FF	199	{
	200	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
	201	u16 msg_ctl;
	202	u16 cmd;
	203
cde4384e FF	204	/* Disable the CMD_DONE interrupt */
	205	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	206
b42dfed8 FF	207	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	208	t->tx_buf, t->rx_buf, t->len);
	209
	210	/* Transmitter is inhibited */
	211	bs->tx_ptr = t->tx_buf;
	212	bs->rx_ptr = t->rx_buf;
b42dfed8 FF	213
	214	if (t->tx_buf) {
	215	bs->remaining_bytes = t->len;
	216	bcm63xx_spi_fill_tx_fifo(bs);
	217	}
	218
cde4384e	219	init_completion(&bs->done);
b42dfed8 FF	220
	221	/* Fill in the Message control register */
	222	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
	223
	224	if (t->rx_buf && t->tx_buf)
5a670445	225	msg_ctl \|= (SPI_FD_RW << bs->msg_type_shift);
b42dfed8	226	else if (t->rx_buf)
5a670445	227	msg_ctl \|= (SPI_HD_R << bs->msg_type_shift);
b42dfed8	228	else if (t->tx_buf)
5a670445 FF	229	msg_ctl \|= (SPI_HD_W << bs->msg_type_shift);
	230
	231	switch (bs->msg_ctl_width) {
	232	case 8:
	233	bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
	234	break;
	235	case 16:
	236	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
	237	break;
	238	}
b42dfed8 FF	239
	240	/* Issue the transfer */
	241	cmd = SPI_CMD_START_IMMEDIATE;
	242	cmd \|= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
	243	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
	244	bcm_spi_writew(bs, cmd, SPI_CMD);
b42dfed8	245
cde4384e FF	246	/* Enable the CMD_DONE interrupt */
cde4384e FF	247	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
b42dfed8 FF	248
	249	return t->len - bs->remaining_bytes;
	250	}
	251
cde4384e	252	static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
b42dfed8	253	{
cde4384e	254	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8	255
cde4384e	256	pm_runtime_get_sync(&bs->pdev->dev);
b42dfed8	257
cde4384e FF	258	return 0;
	259	}
	260
	261	static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
	262	{
	263	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	264
	265	pm_runtime_put(&bs->pdev->dev);
	266
	267	return 0;
	268	}
	269
	270	static int bcm63xx_spi_transfer_one(struct spi_master *master,
	271	struct spi_message *m)
	272	{
	273	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	274	struct spi_transfer *t;
	275	struct spi_device *spi = m->spi;
	276	int status = 0;
	277	unsigned int timeout = 0;
b42dfed8 FF	278
b42dfed8 FF	279	list_for_each_entry(t, &m->transfers, transfer_list) {
cde4384e FF	280	unsigned int len = t->len;
	281	u8 rx_tail;
	282
	283	status = bcm63xx_spi_check_transfer(spi, t);
	284	if (status < 0)
	285	goto exit;
	286
	287	/* configure adapter for a new transfer */
	288	bcm63xx_spi_setup_transfer(spi, t);
	289
	290	while (len) {
	291	/* send the data */
	292	len -= bcm63xx_txrx_bufs(spi, t);
	293
	294	timeout = wait_for_completion_timeout(&bs->done, HZ);
	295	if (!timeout) {
	296	status = -ETIMEDOUT;
	297	goto exit;
	298	}
	299
	300	/* read out all data */
	301	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
	302
	303	/* Read out all the data */
	304	if (rx_tail)
	305	memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
	306	}
b42dfed8	307
cde4384e FF	308	m->actual_length += t->len;
	309	}
	310	exit:
	311	m->status = status;
	312	spi_finalize_current_message(master);
b42dfed8	313
cde4384e	314	return 0;
b42dfed8 FF	315	}
	316
	317	/* This driver supports single master mode only. Hence
	318	* CMD_DONE is the only interrupt we care about
	319	*/
	320	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
	321	{
	322	struct spi_master master = (struct spi_master )dev_id;
	323	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	324	u8 intr;
b42dfed8 FF	325
	326	/* Read interupts and clear them immediately */
	327	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
	328	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	329	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
	330
cde4384e FF	331	/* A transfer completed */
	332	if (intr & SPI_INTR_CMD_DONE)
	333	complete(&bs->done);
b42dfed8 FF	334
	335	return IRQ_HANDLED;
	336	}
	337
	338
	339	static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
	340	{
	341	struct resource *r;
	342	struct device *dev = &pdev->dev;
	343	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
	344	int irq;
	345	struct spi_master *master;
	346	struct clk *clk;
	347	struct bcm63xx_spi *bs;
	348	int ret;
	349
	350	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	351	if (!r) {
	352	dev_err(dev, "no iomem\n");
	353	ret = -ENXIO;
	354	goto out;
	355	}
	356
	357	irq = platform_get_irq(pdev, 0);
	358	if (irq < 0) {
	359	dev_err(dev, "no irq\n");
	360	ret = -ENXIO;
	361	goto out;
	362	}
	363
	364	clk = clk_get(dev, "spi");
	365	if (IS_ERR(clk)) {
	366	dev_err(dev, "no clock for device\n");
	367	ret = PTR_ERR(clk);
	368	goto out;
	369	}
	370
	371	master = spi_alloc_master(dev, sizeof(*bs));
	372	if (!master) {
	373	dev_err(dev, "out of memory\n");
	374	ret = -ENOMEM;
	375	goto out_clk;
	376	}
	377
	378	bs = spi_master_get_devdata(master);
b42dfed8 FF	379
	380	platform_set_drvdata(pdev, master);
	381	bs->pdev = pdev;
	382
	383	if (!devm_request_mem_region(&pdev->dev, r->start,
	384	resource_size(r), PFX)) {
	385	dev_err(dev, "iomem request failed\n");
	386	ret = -ENXIO;
	387	goto out_err;
	388	}
	389
	390	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
	391	resource_size(r));
	392	if (!bs->regs) {
	393	dev_err(dev, "unable to ioremap regs\n");
	394	ret = -ENOMEM;
	395	goto out_err;
	396	}
	397
	398	bs->irq = irq;
	399	bs->clk = clk;
	400	bs->fifo_size = pdata->fifo_size;
	401
	402	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
	403	pdev->name, master);
	404	if (ret) {
	405	dev_err(dev, "unable to request irq\n");
	406	goto out_err;
	407	}
	408
	409	master->bus_num = pdata->bus_num;
	410	master->num_chipselect = pdata->num_chipselect;
	411	master->setup = bcm63xx_spi_setup;
cde4384e FF	412	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
	413	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
	414	master->transfer_one_message = bcm63xx_spi_transfer_one;
88a3a255	415	master->mode_bits = MODEBITS;
b42dfed8	416	bs->speed_hz = pdata->speed_hz;
5a670445 FF	417	bs->msg_type_shift = pdata->msg_type_shift;
5a670445 FF	418	bs->msg_ctl_width = pdata->msg_ctl_width;
b42dfed8 FF	419	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
b42dfed8 FF	420	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
b42dfed8	421
5a670445 FF	422	switch (bs->msg_ctl_width) {
	423	case 8:
	424	case 16:
	425	break;
	426	default:
	427	dev_err(dev, "unsupported MSG_CTL width: %d\n",
	428	bs->msg_ctl_width);
	429	goto out_clk_disable;
	430	}
	431
b42dfed8 FF	432	/* Initialize hardware */
	433	clk_enable(bs->clk);
	434	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
	435
	436	/* register and we are done */
	437	ret = spi_register_master(master);
	438	if (ret) {
	439	dev_err(dev, "spi register failed\n");
	440	goto out_clk_disable;
	441	}
	442
61d15963 FF	443	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
61d15963 FF	444	r->start, irq, bs->fifo_size);
b42dfed8 FF	445
	446	return 0;
	447
	448	out_clk_disable:
	449	clk_disable(clk);
	450	out_err:
	451	platform_set_drvdata(pdev, NULL);
	452	spi_master_put(master);
	453	out_clk:
	454	clk_put(clk);
	455	out:
	456	return ret;
	457	}
	458
	459	static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
	460	{
1f682378	461	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
b42dfed8 FF	462	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
b42dfed8 FF	463
1e41dc0e FF	464	spi_unregister_master(master);
1e41dc0e FF	465
b42dfed8 FF	466	/* reset spi block */
b42dfed8 FF	467	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
b42dfed8 FF	468
	469	/* HW shutdown */
	470	clk_disable(bs->clk);
	471	clk_put(bs->clk);
	472
b42dfed8	473	platform_set_drvdata(pdev, 0);
b42dfed8	474
1f682378 GR	475	spi_master_put(master);
1f682378 GR	476
b42dfed8 FF	477	return 0;
	478	}
	479
	480	#ifdef CONFIG_PM
	481	static int bcm63xx_spi_suspend(struct device *dev)
	482	{
	483	struct spi_master *master =
	484	platform_get_drvdata(to_platform_device(dev));
	485	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	486
	487	clk_disable(bs->clk);
	488
	489	return 0;
	490	}
	491
	492	static int bcm63xx_spi_resume(struct device *dev)
	493	{
	494	struct spi_master *master =
	495	platform_get_drvdata(to_platform_device(dev));
	496	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
	497
	498	clk_enable(bs->clk);
	499
	500	return 0;
	501	}
	502
	503	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
	504	.suspend = bcm63xx_spi_suspend,
	505	.resume = bcm63xx_spi_resume,
	506	};
	507
	508	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
	509	#else
	510	#define BCM63XX_SPI_PM_OPS NULL
	511	#endif
	512
	513	static struct platform_driver bcm63xx_spi_driver = {
	514	.driver = {
	515	.name = "bcm63xx-spi",
	516	.owner = THIS_MODULE,
	517	.pm = BCM63XX_SPI_PM_OPS,
	518	},
	519	.probe = bcm63xx_spi_probe,
	520	.remove = __devexit_p(bcm63xx_spi_remove),
	521	};
	522
	523	module_platform_driver(bcm63xx_spi_driver);
	524
	525	MODULE_ALIAS("platform:bcm63xx_spi");
	526	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
	527	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
	528	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
	529	MODULE_LICENSE("GPL");