Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
9c0a788b | 4 | * Copyright 2004-2010 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
e8304d04 | 15 | #include <linux/gpio.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
131b17d4 | 17 | #include <linux/io.h> |
a5f6abd4 | 18 | #include <linux/ioport.h> |
131b17d4 | 19 | #include <linux/irq.h> |
a5f6abd4 WB |
20 | #include <linux/errno.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/workqueue.h> | |
a5f6abd4 | 26 | |
a5f6abd4 | 27 | #include <asm/dma.h> |
131b17d4 | 28 | #include <asm/portmux.h> |
a5f6abd4 | 29 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
30 | #include <asm/cacheflush.h> |
31 | ||
a32c691d BW |
32 | #define DRV_NAME "bfin-spi" |
33 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 34 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
35 | #define DRV_VERSION "1.0" |
36 | ||
37 | MODULE_AUTHOR(DRV_AUTHOR); | |
38 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
39 | MODULE_LICENSE("GPL"); |
40 | ||
bb90eb00 BW |
41 | #define START_STATE ((void *)0) |
42 | #define RUNNING_STATE ((void *)1) | |
43 | #define DONE_STATE ((void *)2) | |
44 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 45 | |
9c0a788b | 46 | struct bfin_spi_master_data; |
9c4542c7 | 47 | |
9c0a788b MF |
48 | struct bfin_spi_transfer_ops { |
49 | void (*write) (struct bfin_spi_master_data *); | |
50 | void (*read) (struct bfin_spi_master_data *); | |
51 | void (*duplex) (struct bfin_spi_master_data *); | |
9c4542c7 MF |
52 | }; |
53 | ||
9c0a788b | 54 | struct bfin_spi_master_data { |
a5f6abd4 WB |
55 | /* Driver model hookup */ |
56 | struct platform_device *pdev; | |
57 | ||
58 | /* SPI framework hookup */ | |
59 | struct spi_master *master; | |
60 | ||
bb90eb00 | 61 | /* Regs base of SPI controller */ |
47885ce8 | 62 | struct bfin_spi_regs __iomem *regs; |
bb90eb00 | 63 | |
003d9226 BW |
64 | /* Pin request list */ |
65 | u16 *pin_req; | |
66 | ||
a5f6abd4 WB |
67 | /* BFIN hookup */ |
68 | struct bfin5xx_spi_master *master_info; | |
69 | ||
70 | /* Driver message queue */ | |
71 | struct workqueue_struct *workqueue; | |
72 | struct work_struct pump_messages; | |
73 | spinlock_t lock; | |
74 | struct list_head queue; | |
75 | int busy; | |
f4f50c3f | 76 | bool running; |
a5f6abd4 WB |
77 | |
78 | /* Message Transfer pump */ | |
79 | struct tasklet_struct pump_transfers; | |
80 | ||
81 | /* Current message transfer state info */ | |
82 | struct spi_message *cur_msg; | |
83 | struct spi_transfer *cur_transfer; | |
9c0a788b | 84 | struct bfin_spi_slave_data *cur_chip; |
a5f6abd4 WB |
85 | size_t len_in_bytes; |
86 | size_t len; | |
87 | void *tx; | |
88 | void *tx_end; | |
89 | void *rx; | |
90 | void *rx_end; | |
bb90eb00 BW |
91 | |
92 | /* DMA stuffs */ | |
93 | int dma_channel; | |
a5f6abd4 | 94 | int dma_mapped; |
bb90eb00 | 95 | int dma_requested; |
a5f6abd4 WB |
96 | dma_addr_t rx_dma; |
97 | dma_addr_t tx_dma; | |
bb90eb00 | 98 | |
f6a6d966 YL |
99 | int irq_requested; |
100 | int spi_irq; | |
101 | ||
a5f6abd4 WB |
102 | size_t rx_map_len; |
103 | size_t tx_map_len; | |
104 | u8 n_bytes; | |
b052fd0a BS |
105 | u16 ctrl_reg; |
106 | u16 flag_reg; | |
107 | ||
fad91c89 | 108 | int cs_change; |
9c0a788b | 109 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
110 | }; |
111 | ||
9c0a788b | 112 | struct bfin_spi_slave_data { |
a5f6abd4 WB |
113 | u16 ctl_reg; |
114 | u16 baud; | |
115 | u16 flag; | |
116 | ||
117 | u8 chip_select_num; | |
a5f6abd4 | 118 | u8 enable_dma; |
62310e51 | 119 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 120 | u32 cs_gpio; |
93b61bdd | 121 | u16 idle_tx_val; |
f6a6d966 | 122 | u8 pio_interrupt; /* use spi data irq */ |
9c0a788b | 123 | const struct bfin_spi_transfer_ops *ops; |
a5f6abd4 WB |
124 | }; |
125 | ||
9c0a788b | 126 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 127 | { |
47885ce8 | 128 | bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE); |
a5f6abd4 WB |
129 | } |
130 | ||
9c0a788b | 131 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 132 | { |
47885ce8 | 133 | bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE); |
a5f6abd4 WB |
134 | } |
135 | ||
136 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
137 | static u16 hz_to_spi_baud(u32 speed_hz) | |
138 | { | |
139 | u_long sclk = get_sclk(); | |
140 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
141 | ||
142 | if ((sclk % (2 * speed_hz)) > 0) | |
143 | spi_baud++; | |
144 | ||
7513e006 MH |
145 | if (spi_baud < MIN_SPI_BAUD_VAL) |
146 | spi_baud = MIN_SPI_BAUD_VAL; | |
147 | ||
a5f6abd4 WB |
148 | return spi_baud; |
149 | } | |
150 | ||
9c0a788b | 151 | static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
152 | { |
153 | unsigned long limit = loops_per_jiffy << 1; | |
154 | ||
155 | /* wait for stop and clear stat */ | |
47885ce8 | 156 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 157 | cpu_relax(); |
a5f6abd4 | 158 | |
47885ce8 | 159 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 WB |
160 | |
161 | return limit; | |
162 | } | |
163 | ||
fad91c89 | 164 | /* Chip select operation functions for cs_change flag */ |
9c0a788b | 165 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) |
fad91c89 | 166 | { |
47885ce8 MF |
167 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
168 | bfin_write_and(&drv_data->regs->flg, ~chip->flag); | |
169 | else | |
42c78b2b | 170 | gpio_set_value(chip->cs_gpio, 0); |
fad91c89 BW |
171 | } |
172 | ||
9c0a788b MF |
173 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, |
174 | struct bfin_spi_slave_data *chip) | |
fad91c89 | 175 | { |
47885ce8 MF |
176 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
177 | bfin_write_or(&drv_data->regs->flg, chip->flag); | |
178 | else | |
42c78b2b | 179 | gpio_set_value(chip->cs_gpio, 1); |
62310e51 BW |
180 | |
181 | /* Move delay here for consistency */ | |
182 | if (chip->cs_chg_udelay) | |
183 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
184 | } |
185 | ||
8221610e | 186 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
9c0a788b MF |
187 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, |
188 | struct bfin_spi_slave_data *chip) | |
8221610e | 189 | { |
47885ce8 MF |
190 | if (chip->chip_select_num < MAX_CTRL_CS) |
191 | bfin_write_or(&drv_data->regs->flg, chip->flag >> 8); | |
8221610e BS |
192 | } |
193 | ||
9c0a788b MF |
194 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, |
195 | struct bfin_spi_slave_data *chip) | |
8221610e | 196 | { |
47885ce8 MF |
197 | if (chip->chip_select_num < MAX_CTRL_CS) |
198 | bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8)); | |
8221610e BS |
199 | } |
200 | ||
a5f6abd4 | 201 | /* stop controller and re-config current chip*/ |
9c0a788b | 202 | static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 203 | { |
9c0a788b | 204 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
12e17c42 | 205 | |
a5f6abd4 | 206 | /* Clear status and disable clock */ |
47885ce8 | 207 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
a5f6abd4 | 208 | bfin_spi_disable(drv_data); |
88b40369 | 209 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 210 | |
9677b0de BS |
211 | SSYNC(); |
212 | ||
5fec5b5a | 213 | /* Load the registers */ |
47885ce8 MF |
214 | bfin_write(&drv_data->regs->ctl, chip->ctl_reg); |
215 | bfin_write(&drv_data->regs->baud, chip->baud); | |
cc487e73 SZ |
216 | |
217 | bfin_spi_enable(drv_data); | |
138f97cd | 218 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
219 | } |
220 | ||
93b61bdd | 221 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
9c0a788b | 222 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 223 | { |
47885ce8 | 224 | (void) bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
225 | } |
226 | ||
9c0a788b | 227 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 228 | { |
93b61bdd WM |
229 | /* clear RXS (we check for RXS inside the loop) */ |
230 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 231 | |
a5f6abd4 | 232 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 233 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
93b61bdd WM |
234 | /* wait until transfer finished. |
235 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 236 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 237 | cpu_relax(); |
93b61bdd WM |
238 | /* discard RX data and clear RXS */ |
239 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 240 | } |
a5f6abd4 WB |
241 | } |
242 | ||
9c0a788b | 243 | static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 244 | { |
93b61bdd | 245 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 246 | |
93b61bdd | 247 | /* discard old RX data and clear RXS */ |
138f97cd | 248 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 249 | |
93b61bdd | 250 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
251 | bfin_write(&drv_data->regs->tdbr, tx_val); |
252 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 253 | cpu_relax(); |
47885ce8 | 254 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 255 | } |
a5f6abd4 WB |
256 | } |
257 | ||
9c0a788b | 258 | static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 259 | { |
93b61bdd WM |
260 | /* discard old RX data and clear RXS */ |
261 | bfin_spi_dummy_read(drv_data); | |
262 | ||
a5f6abd4 | 263 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
264 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
265 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 266 | cpu_relax(); |
47885ce8 | 267 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
268 | } |
269 | } | |
270 | ||
9c0a788b | 271 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { |
9c4542c7 MF |
272 | .write = bfin_spi_u8_writer, |
273 | .read = bfin_spi_u8_reader, | |
274 | .duplex = bfin_spi_u8_duplex, | |
275 | }; | |
276 | ||
9c0a788b | 277 | static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 278 | { |
93b61bdd WM |
279 | /* clear RXS (we check for RXS inside the loop) */ |
280 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 281 | |
a5f6abd4 | 282 | while (drv_data->tx < drv_data->tx_end) { |
47885ce8 | 283 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 284 | drv_data->tx += 2; |
93b61bdd WM |
285 | /* wait until transfer finished. |
286 | checking SPIF or TXS may not guarantee transfer completion */ | |
47885ce8 | 287 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
93b61bdd WM |
288 | cpu_relax(); |
289 | /* discard RX data and clear RXS */ | |
290 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 291 | } |
a5f6abd4 WB |
292 | } |
293 | ||
9c0a788b | 294 | static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 295 | { |
93b61bdd | 296 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 297 | |
93b61bdd | 298 | /* discard old RX data and clear RXS */ |
138f97cd | 299 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 300 | |
93b61bdd | 301 | while (drv_data->rx < drv_data->rx_end) { |
47885ce8 MF |
302 | bfin_write(&drv_data->regs->tdbr, tx_val); |
303 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) | |
d8c05008 | 304 | cpu_relax(); |
47885ce8 | 305 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 WB |
306 | drv_data->rx += 2; |
307 | } | |
a5f6abd4 WB |
308 | } |
309 | ||
9c0a788b | 310 | static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 311 | { |
93b61bdd WM |
312 | /* discard old RX data and clear RXS */ |
313 | bfin_spi_dummy_read(drv_data); | |
314 | ||
315 | while (drv_data->rx < drv_data->rx_end) { | |
47885ce8 | 316 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
93b61bdd | 317 | drv_data->tx += 2; |
47885ce8 | 318 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
d8c05008 | 319 | cpu_relax(); |
47885ce8 | 320 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
a5f6abd4 | 321 | drv_data->rx += 2; |
a5f6abd4 WB |
322 | } |
323 | } | |
324 | ||
9c0a788b | 325 | static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { |
9c4542c7 MF |
326 | .write = bfin_spi_u16_writer, |
327 | .read = bfin_spi_u16_reader, | |
328 | .duplex = bfin_spi_u16_duplex, | |
329 | }; | |
330 | ||
e3595405 | 331 | /* test if there is more transfer to be done */ |
9c0a788b | 332 | static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
333 | { |
334 | struct spi_message *msg = drv_data->cur_msg; | |
335 | struct spi_transfer *trans = drv_data->cur_transfer; | |
336 | ||
337 | /* Move to next transfer */ | |
338 | if (trans->transfer_list.next != &msg->transfers) { | |
339 | drv_data->cur_transfer = | |
340 | list_entry(trans->transfer_list.next, | |
341 | struct spi_transfer, transfer_list); | |
342 | return RUNNING_STATE; | |
343 | } else | |
344 | return DONE_STATE; | |
345 | } | |
346 | ||
347 | /* | |
348 | * caller already set message->status; | |
349 | * dma and pio irqs are blocked give finished message back | |
350 | */ | |
9c0a788b | 351 | static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data) |
a5f6abd4 | 352 | { |
9c0a788b | 353 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
354 | unsigned long flags; |
355 | struct spi_message *msg; | |
356 | ||
357 | spin_lock_irqsave(&drv_data->lock, flags); | |
358 | msg = drv_data->cur_msg; | |
359 | drv_data->cur_msg = NULL; | |
360 | drv_data->cur_transfer = NULL; | |
361 | drv_data->cur_chip = NULL; | |
362 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
363 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
364 | ||
a5f6abd4 WB |
365 | msg->state = NULL; |
366 | ||
fad91c89 | 367 | if (!drv_data->cs_change) |
138f97cd | 368 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 369 | |
b9b2a76a YL |
370 | /* Not stop spi in autobuffer mode */ |
371 | if (drv_data->tx_dma != 0xFFFF) | |
372 | bfin_spi_disable(drv_data); | |
373 | ||
a5f6abd4 WB |
374 | if (msg->complete) |
375 | msg->complete(msg->context); | |
376 | } | |
377 | ||
f6a6d966 YL |
378 | /* spi data irq handler */ |
379 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
380 | { | |
9c0a788b MF |
381 | struct bfin_spi_master_data *drv_data = dev_id; |
382 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
383 | struct spi_message *msg = drv_data->cur_msg; |
384 | int n_bytes = drv_data->n_bytes; | |
4d676fc5 | 385 | int loop = 0; |
f6a6d966 YL |
386 | |
387 | /* wait until transfer finished. */ | |
47885ce8 | 388 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
f6a6d966 YL |
389 | cpu_relax(); |
390 | ||
391 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
392 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
393 | /* last read */ | |
394 | if (drv_data->rx) { | |
395 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
128465ca | 396 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
397 | u16 *buf = (u16 *)drv_data->rx; |
398 | for (loop = 0; loop < n_bytes / 2; loop++) | |
47885ce8 | 399 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 BL |
400 | } else { |
401 | u8 *buf = (u8 *)drv_data->rx; | |
402 | for (loop = 0; loop < n_bytes; loop++) | |
47885ce8 | 403 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
4d676fc5 | 404 | } |
f6a6d966 YL |
405 | drv_data->rx += n_bytes; |
406 | } | |
407 | ||
408 | msg->actual_length += drv_data->len_in_bytes; | |
409 | if (drv_data->cs_change) | |
410 | bfin_spi_cs_deactive(drv_data, chip); | |
411 | /* Move to next transfer */ | |
412 | msg->state = bfin_spi_next_transfer(drv_data); | |
413 | ||
7370ed6b | 414 | disable_irq_nosync(drv_data->spi_irq); |
f6a6d966 YL |
415 | |
416 | /* Schedule transfer tasklet */ | |
417 | tasklet_schedule(&drv_data->pump_transfers); | |
418 | return IRQ_HANDLED; | |
419 | } | |
420 | ||
421 | if (drv_data->rx && drv_data->tx) { | |
422 | /* duplex */ | |
423 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
128465ca | 424 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
425 | u16 *buf = (u16 *)drv_data->rx; |
426 | u16 *buf2 = (u16 *)drv_data->tx; | |
427 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
428 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
429 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 BL |
430 | } |
431 | } else { | |
432 | u8 *buf = (u8 *)drv_data->rx; | |
433 | u8 *buf2 = (u8 *)drv_data->tx; | |
434 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
435 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
436 | bfin_write(&drv_data->regs->tdbr, *buf2++); | |
4d676fc5 | 437 | } |
f6a6d966 YL |
438 | } |
439 | } else if (drv_data->rx) { | |
440 | /* read */ | |
441 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
128465ca | 442 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
443 | u16 *buf = (u16 *)drv_data->rx; |
444 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
445 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
446 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
447 | } |
448 | } else { | |
449 | u8 *buf = (u8 *)drv_data->rx; | |
450 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
451 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
452 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); | |
4d676fc5 BL |
453 | } |
454 | } | |
f6a6d966 YL |
455 | } else if (drv_data->tx) { |
456 | /* write */ | |
457 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
128465ca | 458 | if (!(n_bytes % 2)) { |
4d676fc5 BL |
459 | u16 *buf = (u16 *)drv_data->tx; |
460 | for (loop = 0; loop < n_bytes / 2; loop++) { | |
47885ce8 MF |
461 | bfin_read(&drv_data->regs->rdbr); |
462 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
463 | } |
464 | } else { | |
465 | u8 *buf = (u8 *)drv_data->tx; | |
466 | for (loop = 0; loop < n_bytes; loop++) { | |
47885ce8 MF |
467 | bfin_read(&drv_data->regs->rdbr); |
468 | bfin_write(&drv_data->regs->tdbr, *buf++); | |
4d676fc5 BL |
469 | } |
470 | } | |
f6a6d966 YL |
471 | } |
472 | ||
473 | if (drv_data->tx) | |
474 | drv_data->tx += n_bytes; | |
475 | if (drv_data->rx) | |
476 | drv_data->rx += n_bytes; | |
477 | ||
478 | return IRQ_HANDLED; | |
479 | } | |
480 | ||
138f97cd | 481 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 482 | { |
9c0a788b MF |
483 | struct bfin_spi_master_data *drv_data = dev_id; |
484 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 485 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 486 | unsigned long timeout; |
d24bd1d0 | 487 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
47885ce8 | 488 | u16 spistat = bfin_read(&drv_data->regs->stat); |
a5f6abd4 | 489 | |
d24bd1d0 MF |
490 | dev_dbg(&drv_data->pdev->dev, |
491 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
492 | dmastat, spistat); | |
493 | ||
782a8956 | 494 | if (drv_data->rx != NULL) { |
47885ce8 | 495 | u16 cr = bfin_read(&drv_data->regs->ctl); |
782a8956 MH |
496 | /* discard old RX data and clear RXS */ |
497 | bfin_spi_dummy_read(drv_data); | |
47885ce8 MF |
498 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ |
499 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */ | |
500 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */ | |
782a8956 MH |
501 | } |
502 | ||
bb90eb00 | 503 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
504 | |
505 | /* | |
d6fe89b0 BW |
506 | * wait for the last transaction shifted out. HRM states: |
507 | * at this point there may still be data in the SPI DMA FIFO waiting | |
508 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
509 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
510 | */ |
511 | if (drv_data->tx != NULL) { | |
47885ce8 MF |
512 | while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) || |
513 | (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS)) | |
d8c05008 | 514 | cpu_relax(); |
a5f6abd4 WB |
515 | } |
516 | ||
aaaf939c MF |
517 | dev_dbg(&drv_data->pdev->dev, |
518 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
47885ce8 | 519 | dmastat, bfin_read(&drv_data->regs->stat)); |
aaaf939c MF |
520 | |
521 | timeout = jiffies + HZ; | |
47885ce8 | 522 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
aaaf939c | 523 | if (!time_before(jiffies, timeout)) { |
a1829d2b | 524 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n"); |
aaaf939c MF |
525 | break; |
526 | } else | |
527 | cpu_relax(); | |
a5f6abd4 | 528 | |
90008a64 | 529 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
530 | msg->state = ERROR_STATE; |
531 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
532 | } else { | |
533 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 534 | |
04b95d2f | 535 | if (drv_data->cs_change) |
138f97cd | 536 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 537 | |
04b95d2f | 538 | /* Move to next transfer */ |
138f97cd | 539 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 540 | } |
a5f6abd4 WB |
541 | |
542 | /* Schedule transfer tasklet */ | |
543 | tasklet_schedule(&drv_data->pump_transfers); | |
544 | ||
545 | /* free the irq handler before next transfer */ | |
88b40369 BW |
546 | dev_dbg(&drv_data->pdev->dev, |
547 | "disable dma channel irq%d\n", | |
bb90eb00 | 548 | drv_data->dma_channel); |
a75bd65b | 549 | dma_disable_irq_nosync(drv_data->dma_channel); |
a5f6abd4 WB |
550 | |
551 | return IRQ_HANDLED; | |
552 | } | |
553 | ||
138f97cd | 554 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 555 | { |
9c0a788b | 556 | struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data; |
a5f6abd4 WB |
557 | struct spi_message *message = NULL; |
558 | struct spi_transfer *transfer = NULL; | |
559 | struct spi_transfer *previous = NULL; | |
9c0a788b | 560 | struct bfin_spi_slave_data *chip = NULL; |
033f44bd | 561 | unsigned int bits_per_word; |
057f6061 | 562 | u16 cr, cr_width = 0, dma_width, dma_config; |
a5f6abd4 | 563 | u32 tranf_success = 1; |
8eeb12e5 | 564 | u8 full_duplex = 0; |
a5f6abd4 WB |
565 | |
566 | /* Get current state information */ | |
567 | message = drv_data->cur_msg; | |
568 | transfer = drv_data->cur_transfer; | |
569 | chip = drv_data->cur_chip; | |
092e1fda | 570 | |
a5f6abd4 WB |
571 | /* |
572 | * if msg is error or done, report it back using complete() callback | |
573 | */ | |
574 | ||
575 | /* Handle for abort */ | |
576 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 577 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 578 | message->status = -EIO; |
138f97cd | 579 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
580 | return; |
581 | } | |
582 | ||
583 | /* Handle end of message */ | |
584 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 585 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 586 | message->status = 0; |
2431a815 | 587 | bfin_spi_flush(drv_data); |
138f97cd | 588 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
589 | return; |
590 | } | |
591 | ||
592 | /* Delay if requested at end of transfer */ | |
593 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 594 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
595 | previous = list_entry(transfer->transfer_list.prev, |
596 | struct spi_transfer, transfer_list); | |
597 | if (previous->delay_usecs) | |
598 | udelay(previous->delay_usecs); | |
599 | } | |
600 | ||
ab09e040 | 601 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 602 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
603 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
604 | message->status = -EIO; | |
138f97cd | 605 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
606 | return; |
607 | } | |
608 | ||
93b61bdd WM |
609 | if (transfer->len == 0) { |
610 | /* Move to next transfer of this msg */ | |
611 | message->state = bfin_spi_next_transfer(drv_data); | |
612 | /* Schedule next transfer tasklet */ | |
613 | tasklet_schedule(&drv_data->pump_transfers); | |
1974eba6 | 614 | return; |
93b61bdd WM |
615 | } |
616 | ||
a5f6abd4 WB |
617 | if (transfer->tx_buf != NULL) { |
618 | drv_data->tx = (void *)transfer->tx_buf; | |
619 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
620 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
621 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
622 | } else { |
623 | drv_data->tx = NULL; | |
624 | } | |
625 | ||
626 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 627 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
628 | drv_data->rx = transfer->rx_buf; |
629 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
630 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
631 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
632 | } else { |
633 | drv_data->rx = NULL; | |
634 | } | |
635 | ||
636 | drv_data->rx_dma = transfer->rx_dma; | |
637 | drv_data->tx_dma = transfer->tx_dma; | |
638 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 639 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 640 | |
092e1fda | 641 | /* Bits per word setup */ |
766ed704 | 642 | bits_per_word = transfer->bits_per_word; |
24778be2 | 643 | if (bits_per_word == 16) { |
4d676fc5 | 644 | drv_data->n_bytes = bits_per_word/8; |
5e8592dc MF |
645 | drv_data->len = (transfer->len) >> 1; |
646 | cr_width = BIT_CTL_WORDSIZE; | |
9c0a788b | 647 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u16; |
24778be2 | 648 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
649 | drv_data->n_bytes = bits_per_word/8; |
650 | drv_data->len = transfer->len; | |
4d676fc5 | 651 | drv_data->ops = &bfin_bfin_spi_transfer_ops_u8; |
092e1fda | 652 | } |
47885ce8 | 653 | cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); |
5e8592dc | 654 | cr |= cr_width; |
47885ce8 | 655 | bfin_write(&drv_data->regs->ctl, cr); |
092e1fda | 656 | |
4fb98efa | 657 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 | 658 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
9c0a788b | 659 | drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8); |
a5f6abd4 | 660 | |
a5f6abd4 WB |
661 | message->state = RUNNING_STATE; |
662 | dma_config = 0; | |
663 | ||
092e1fda BW |
664 | /* Speed setup (surely valid because already checked) */ |
665 | if (transfer->speed_hz) | |
47885ce8 | 666 | bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz)); |
092e1fda | 667 | else |
47885ce8 | 668 | bfin_write(&drv_data->regs->baud, chip->baud); |
092e1fda | 669 | |
47885ce8 | 670 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
e72dcde7 | 671 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 672 | |
88b40369 BW |
673 | dev_dbg(&drv_data->pdev->dev, |
674 | "now pumping a transfer: width is %d, len is %d\n", | |
5e8592dc | 675 | cr_width, transfer->len); |
a5f6abd4 WB |
676 | |
677 | /* | |
8cf5858c VM |
678 | * Try to map dma buffer and do a dma transfer. If successful use, |
679 | * different way to r/w according to the enable_dma settings and if | |
680 | * we are not doing a full duplex transfer (since the hardware does | |
681 | * not support full duplex DMA transfers). | |
a5f6abd4 | 682 | */ |
8eeb12e5 VM |
683 | if (!full_duplex && drv_data->cur_chip->enable_dma |
684 | && drv_data->len > 6) { | |
a5f6abd4 | 685 | |
11d6f599 | 686 | unsigned long dma_start_addr, flags; |
7aec3566 | 687 | |
bb90eb00 BW |
688 | disable_dma(drv_data->dma_channel); |
689 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
690 | |
691 | /* config dma channel */ | |
88b40369 | 692 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 693 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
5e8592dc | 694 | if (cr_width == BIT_CTL_WORDSIZE) { |
bb90eb00 | 695 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
696 | dma_width = WDSIZE_16; |
697 | } else { | |
bb90eb00 | 698 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
699 | dma_width = WDSIZE_8; |
700 | } | |
701 | ||
3f479a65 | 702 | /* poll for SPI completion before start */ |
47885ce8 | 703 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
d8c05008 | 704 | cpu_relax(); |
3f479a65 | 705 | |
a5f6abd4 WB |
706 | /* dirty hack for autobuffer DMA mode */ |
707 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
708 | dev_dbg(&drv_data->pdev->dev, |
709 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
710 | |
711 | /* no irq in autobuffer mode */ | |
712 | dma_config = | |
713 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
714 | set_dma_config(drv_data->dma_channel, dma_config); |
715 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 716 | (unsigned long)drv_data->tx); |
bb90eb00 | 717 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 718 | |
07612e5f | 719 | /* start SPI transfer */ |
47885ce8 | 720 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
721 | |
722 | /* just return here, there can only be one transfer | |
723 | * in this mode | |
724 | */ | |
a5f6abd4 | 725 | message->status = 0; |
138f97cd | 726 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
727 | return; |
728 | } | |
729 | ||
730 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 731 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
732 | if (drv_data->rx != NULL) { |
733 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
734 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
735 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 736 | |
8cf5858c | 737 | /* invalidate caches, if needed */ |
67834fa9 | 738 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
739 | invalidate_dcache_range((unsigned long) drv_data->rx, |
740 | (unsigned long) (drv_data->rx + | |
ace32865 | 741 | drv_data->len_in_bytes)); |
8cf5858c | 742 | |
7aec3566 MF |
743 | dma_config |= WNR; |
744 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 745 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 746 | |
a5f6abd4 | 747 | } else if (drv_data->tx != NULL) { |
88b40369 | 748 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 749 | |
8cf5858c | 750 | /* flush caches, if needed */ |
67834fa9 | 751 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
752 | flush_dcache_range((unsigned long) drv_data->tx, |
753 | (unsigned long) (drv_data->tx + | |
ace32865 | 754 | drv_data->len_in_bytes)); |
8cf5858c | 755 | |
7aec3566 | 756 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 757 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
758 | |
759 | } else | |
760 | BUG(); | |
761 | ||
11d6f599 MF |
762 | /* oh man, here there be monsters ... and i dont mean the |
763 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
764 | * your data, kick your dog, and love it all. do *not* try | |
765 | * and change these lines unless you (1) heavily test DMA | |
766 | * with SPI flashes on a loaded system (e.g. ping floods), | |
767 | * (2) know just how broken the DMA engine interaction with | |
768 | * the SPI peripheral is, and (3) have someone else to blame | |
769 | * when you screw it all up anyways. | |
770 | */ | |
7aec3566 | 771 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
772 | set_dma_config(drv_data->dma_channel, dma_config); |
773 | local_irq_save(flags); | |
a963ea83 | 774 | SSYNC(); |
47885ce8 | 775 | bfin_write(&drv_data->regs->ctl, cr); |
a963ea83 | 776 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
777 | dma_enable_irq(drv_data->dma_channel); |
778 | local_irq_restore(flags); | |
07612e5f | 779 | |
f6a6d966 YL |
780 | return; |
781 | } | |
a5f6abd4 | 782 | |
5e8592dc MF |
783 | /* |
784 | * We always use SPI_WRITE mode (transfer starts with TDBR write). | |
785 | * SPI_READ mode (transfer starts with RDBR read) seems to have | |
786 | * problems with setting up the output value in TDBR prior to the | |
787 | * start of the transfer. | |
788 | */ | |
47885ce8 | 789 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD); |
5e8592dc | 790 | |
f6a6d966 | 791 | if (chip->pio_interrupt) { |
5e8592dc | 792 | /* SPI irq should have been disabled by now */ |
93b61bdd | 793 | |
f6a6d966 YL |
794 | /* discard old RX data and clear RXS */ |
795 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 796 | |
f6a6d966 YL |
797 | /* start transfer */ |
798 | if (drv_data->tx == NULL) | |
47885ce8 | 799 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
f6a6d966 | 800 | else { |
4d676fc5 | 801 | int loop; |
24778be2 | 802 | if (bits_per_word == 16) { |
4d676fc5 BL |
803 | u16 *buf = (u16 *)drv_data->tx; |
804 | for (loop = 0; loop < bits_per_word / 16; | |
805 | loop++) { | |
47885ce8 | 806 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 | 807 | } |
24778be2 | 808 | } else if (bits_per_word == 8) { |
4d676fc5 BL |
809 | u8 *buf = (u8 *)drv_data->tx; |
810 | for (loop = 0; loop < bits_per_word / 8; loop++) | |
47885ce8 | 811 | bfin_write(&drv_data->regs->tdbr, *buf++); |
4d676fc5 BL |
812 | } |
813 | ||
f6a6d966 YL |
814 | drv_data->tx += drv_data->n_bytes; |
815 | } | |
a5f6abd4 | 816 | |
f6a6d966 YL |
817 | /* once TDBR is empty, interrupt is triggered */ |
818 | enable_irq(drv_data->spi_irq); | |
819 | return; | |
820 | } | |
a5f6abd4 | 821 | |
f6a6d966 YL |
822 | /* IO mode */ |
823 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
824 | ||
f6a6d966 YL |
825 | if (full_duplex) { |
826 | /* full duplex mode */ | |
827 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
828 | (drv_data->rx_end - drv_data->rx)); | |
829 | dev_dbg(&drv_data->pdev->dev, | |
830 | "IO duplex: cr is 0x%x\n", cr); | |
831 | ||
9c4542c7 | 832 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
833 | |
834 | if (drv_data->tx != drv_data->tx_end) | |
835 | tranf_success = 0; | |
836 | } else if (drv_data->tx != NULL) { | |
837 | /* write only half duplex */ | |
838 | dev_dbg(&drv_data->pdev->dev, | |
839 | "IO write: cr is 0x%x\n", cr); | |
840 | ||
9c4542c7 | 841 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
842 | |
843 | if (drv_data->tx != drv_data->tx_end) | |
844 | tranf_success = 0; | |
845 | } else if (drv_data->rx != NULL) { | |
846 | /* read only half duplex */ | |
847 | dev_dbg(&drv_data->pdev->dev, | |
848 | "IO read: cr is 0x%x\n", cr); | |
849 | ||
9c4542c7 | 850 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
851 | if (drv_data->rx != drv_data->rx_end) |
852 | tranf_success = 0; | |
853 | } | |
a5f6abd4 | 854 | |
f6a6d966 YL |
855 | if (!tranf_success) { |
856 | dev_dbg(&drv_data->pdev->dev, | |
857 | "IO write error!\n"); | |
858 | message->state = ERROR_STATE; | |
859 | } else { | |
25985edc | 860 | /* Update total byte transferred */ |
f6a6d966 YL |
861 | message->actual_length += drv_data->len_in_bytes; |
862 | /* Move to next transfer of this msg */ | |
863 | message->state = bfin_spi_next_transfer(drv_data); | |
2431a815 SJ |
864 | if (drv_data->cs_change && message->state != DONE_STATE) { |
865 | bfin_spi_flush(drv_data); | |
f6a6d966 | 866 | bfin_spi_cs_deactive(drv_data, chip); |
2431a815 | 867 | } |
a5f6abd4 | 868 | } |
f6a6d966 YL |
869 | |
870 | /* Schedule next transfer tasklet */ | |
871 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
872 | } |
873 | ||
874 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 875 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 876 | { |
9c0a788b | 877 | struct bfin_spi_master_data *drv_data; |
a5f6abd4 WB |
878 | unsigned long flags; |
879 | ||
9c0a788b | 880 | drv_data = container_of(work, struct bfin_spi_master_data, pump_messages); |
131b17d4 | 881 | |
a5f6abd4 WB |
882 | /* Lock queue and check for queue work */ |
883 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 884 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
885 | /* pumper kicked off but no work to do */ |
886 | drv_data->busy = 0; | |
887 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
888 | return; | |
889 | } | |
890 | ||
891 | /* Make sure we are not already running a message */ | |
892 | if (drv_data->cur_msg) { | |
893 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
894 | return; | |
895 | } | |
896 | ||
897 | /* Extract head of queue */ | |
898 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
899 | struct spi_message, queue); | |
5fec5b5a BW |
900 | |
901 | /* Setup the SSP using the per chip configuration */ | |
902 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 903 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 904 | |
a5f6abd4 WB |
905 | list_del_init(&drv_data->cur_msg->queue); |
906 | ||
907 | /* Initial message state */ | |
908 | drv_data->cur_msg->state = START_STATE; | |
909 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
910 | struct spi_transfer, transfer_list); | |
911 | ||
f6bd03a7 JN |
912 | dev_dbg(&drv_data->pdev->dev, |
913 | "got a message to pump, state is set to: baud " | |
914 | "%d, flag 0x%x, ctl 0x%x\n", | |
5fec5b5a BW |
915 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, |
916 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
917 | |
918 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
919 | "the first transfer len is %d\n", |
920 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
921 | |
922 | /* Mark as busy and launch transfers */ | |
923 | tasklet_schedule(&drv_data->pump_transfers); | |
924 | ||
925 | drv_data->busy = 1; | |
926 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
927 | } | |
928 | ||
929 | /* | |
930 | * got a msg to transfer, queue it in drv_data->queue. | |
931 | * And kick off message pumper | |
932 | */ | |
138f97cd | 933 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 934 | { |
9c0a788b | 935 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
936 | unsigned long flags; |
937 | ||
938 | spin_lock_irqsave(&drv_data->lock, flags); | |
939 | ||
f4f50c3f | 940 | if (!drv_data->running) { |
a5f6abd4 WB |
941 | spin_unlock_irqrestore(&drv_data->lock, flags); |
942 | return -ESHUTDOWN; | |
943 | } | |
944 | ||
945 | msg->actual_length = 0; | |
946 | msg->status = -EINPROGRESS; | |
947 | msg->state = START_STATE; | |
948 | ||
88b40369 | 949 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
950 | list_add_tail(&msg->queue, &drv_data->queue); |
951 | ||
f4f50c3f | 952 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
953 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
954 | ||
955 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
12e17c42 SZ |
960 | #define MAX_SPI_SSEL 7 |
961 | ||
ddc0bf13 | 962 | static const u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
963 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
964 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
965 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
966 | ||
967 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
968 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
969 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
970 | ||
971 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
972 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
973 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
974 | }; | |
975 | ||
ab09e040 | 976 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 977 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 978 | { |
ac01e97d | 979 | struct bfin5xx_spi_chip *chip_info; |
9c0a788b MF |
980 | struct bfin_spi_slave_data *chip = NULL; |
981 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
5b47bcd4 | 982 | u16 bfin_ctl_reg; |
ac01e97d | 983 | int ret = -EINVAL; |
a5f6abd4 | 984 | |
a5f6abd4 | 985 | /* Only alloc (or use chip_info) on first setup */ |
ac01e97d | 986 | chip_info = NULL; |
a5f6abd4 WB |
987 | chip = spi_get_ctldata(spi); |
988 | if (chip == NULL) { | |
ac01e97d DM |
989 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
990 | if (!chip) { | |
991 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
992 | ret = -ENOMEM; | |
993 | goto error; | |
994 | } | |
a5f6abd4 WB |
995 | |
996 | chip->enable_dma = 0; | |
997 | chip_info = spi->controller_data; | |
998 | } | |
999 | ||
5b47bcd4 MF |
1000 | /* Let people set non-standard bits directly */ |
1001 | bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | | |
1002 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ; | |
1003 | ||
a5f6abd4 WB |
1004 | /* chip_info isn't always needed */ |
1005 | if (chip_info) { | |
2ed35516 MF |
1006 | /* Make sure people stop trying to set fields via ctl_reg |
1007 | * when they should actually be using common SPI framework. | |
90008a64 | 1008 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1009 | * Not sure if a user actually needs/uses any of these, |
1010 | * but let's assume (for now) they do. | |
1011 | */ | |
5b47bcd4 | 1012 | if (chip_info->ctl_reg & ~bfin_ctl_reg) { |
f6bd03a7 JN |
1013 | dev_err(&spi->dev, |
1014 | "do not set bits in ctl_reg that the SPI framework manages\n"); | |
ac01e97d | 1015 | goto error; |
2ed35516 | 1016 | } |
a5f6abd4 WB |
1017 | chip->enable_dma = chip_info->enable_dma != 0 |
1018 | && drv_data->master_info->enable_dma; | |
1019 | chip->ctl_reg = chip_info->ctl_reg; | |
a5f6abd4 | 1020 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1021 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1022 | chip->pio_interrupt = chip_info->pio_interrupt; |
5b47bcd4 MF |
1023 | } else { |
1024 | /* force a default base state */ | |
1025 | chip->ctl_reg &= bfin_ctl_reg; | |
033f44bd MF |
1026 | } |
1027 | ||
a5f6abd4 WB |
1028 | /* translate common spi framework into our register */ |
1029 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1030 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1031 | if (spi->mode & SPI_CPHA) |
90008a64 | 1032 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1033 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1034 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1035 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1036 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1037 | |
a5f6abd4 WB |
1038 | /* |
1039 | * Notice: for blackfin, the speed_hz is the value of register | |
1040 | * SPI_BAUD, not the real baudrate | |
1041 | */ | |
1042 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1043 | chip->chip_select_num = spi->chip_select; |
4190f6a5 BS |
1044 | if (chip->chip_select_num < MAX_CTRL_CS) { |
1045 | if (!(spi->mode & SPI_CPHA)) | |
f6bd03a7 JN |
1046 | dev_warn(&spi->dev, |
1047 | "Warning: SPI CPHA not set: Slave Select not under software control!\n" | |
1048 | "See Documentation/blackfin/bfin-spi-notes.txt\n"); | |
4190f6a5 | 1049 | |
d3cc71f7 | 1050 | chip->flag = (1 << spi->chip_select) << 8; |
4190f6a5 | 1051 | } else |
d3cc71f7 | 1052 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; |
a5f6abd4 | 1053 | |
f6a6d966 | 1054 | if (chip->enable_dma && chip->pio_interrupt) { |
f6bd03a7 JN |
1055 | dev_err(&spi->dev, |
1056 | "enable_dma is set, do not set pio_interrupt\n"); | |
f6a6d966 YL |
1057 | goto error; |
1058 | } | |
ac01e97d DM |
1059 | /* |
1060 | * if any one SPI chip is registered and wants DMA, request the | |
1061 | * DMA channel for it | |
1062 | */ | |
1063 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1064 | /* register dma irq handler */ | |
1065 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1066 | if (ret) { | |
1067 | dev_err(&spi->dev, | |
1068 | "Unable to request BlackFin SPI DMA channel\n"); | |
1069 | goto error; | |
1070 | } | |
1071 | drv_data->dma_requested = 1; | |
1072 | ||
1073 | ret = set_dma_callback(drv_data->dma_channel, | |
1074 | bfin_spi_dma_irq_handler, drv_data); | |
1075 | if (ret) { | |
1076 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1077 | goto error; | |
1078 | } | |
1079 | dma_disable_irq(drv_data->dma_channel); | |
1080 | } | |
1081 | ||
f6a6d966 YL |
1082 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1083 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
38ada214 | 1084 | 0, "BFIN_SPI", drv_data); |
f6a6d966 YL |
1085 | if (ret) { |
1086 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1087 | goto error; | |
1088 | } | |
1089 | drv_data->irq_requested = 1; | |
1090 | /* we use write mode, spi irq has to be disabled here */ | |
1091 | disable_irq(drv_data->spi_irq); | |
1092 | } | |
1093 | ||
d3cc71f7 | 1094 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
73e1ac16 MH |
1095 | /* Only request on first setup */ |
1096 | if (spi_get_ctldata(spi) == NULL) { | |
1097 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1098 | if (ret) { | |
1099 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1100 | goto pin_error; | |
1101 | } | |
1102 | gpio_direction_output(chip->cs_gpio, 1); | |
ac01e97d | 1103 | } |
a5f6abd4 WB |
1104 | } |
1105 | ||
898eb71c | 1106 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
033f44bd | 1107 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
88b40369 | 1108 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1109 | chip->ctl_reg, chip->flag); |
1110 | ||
1111 | spi_set_ctldata(spi, chip); | |
1112 | ||
12e17c42 | 1113 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1114 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1115 | ret = peripheral_request(ssel[spi->master->bus_num] |
1116 | [chip->chip_select_num-1], spi->modalias); | |
1117 | if (ret) { | |
1118 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1119 | goto pin_error; | |
1120 | } | |
1121 | } | |
12e17c42 | 1122 | |
8221610e | 1123 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1124 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1125 | |
a5f6abd4 | 1126 | return 0; |
ac01e97d DM |
1127 | |
1128 | pin_error: | |
d3cc71f7 | 1129 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1130 | gpio_free(chip->cs_gpio); |
1131 | else | |
1132 | peripheral_free(ssel[spi->master->bus_num] | |
1133 | [chip->chip_select_num - 1]); | |
1134 | error: | |
1135 | if (chip) { | |
1136 | if (drv_data->dma_requested) | |
1137 | free_dma(drv_data->dma_channel); | |
1138 | drv_data->dma_requested = 0; | |
1139 | ||
1140 | kfree(chip); | |
1141 | /* prevent free 'chip' twice */ | |
1142 | spi_set_ctldata(spi, NULL); | |
1143 | } | |
1144 | ||
1145 | return ret; | |
a5f6abd4 WB |
1146 | } |
1147 | ||
1148 | /* | |
1149 | * callback for spi framework. | |
1150 | * clean driver specific data | |
1151 | */ | |
138f97cd | 1152 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1153 | { |
9c0a788b MF |
1154 | struct bfin_spi_slave_data *chip = spi_get_ctldata(spi); |
1155 | struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1156 | |
e7d02e3c MF |
1157 | if (!chip) |
1158 | return; | |
1159 | ||
d3cc71f7 | 1160 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1161 | peripheral_free(ssel[spi->master->bus_num] |
1162 | [chip->chip_select_num-1]); | |
8221610e | 1163 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1164 | } else |
42c78b2b MH |
1165 | gpio_free(chip->cs_gpio); |
1166 | ||
a5f6abd4 | 1167 | kfree(chip); |
ac01e97d DM |
1168 | /* prevent free 'chip' twice */ |
1169 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1170 | } |
1171 | ||
c52d4e5f | 1172 | static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1173 | { |
1174 | INIT_LIST_HEAD(&drv_data->queue); | |
1175 | spin_lock_init(&drv_data->lock); | |
1176 | ||
f4f50c3f | 1177 | drv_data->running = false; |
a5f6abd4 WB |
1178 | drv_data->busy = 0; |
1179 | ||
1180 | /* init transfer tasklet */ | |
1181 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1182 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1183 | |
1184 | /* init messages workqueue */ | |
138f97cd | 1185 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1186 | drv_data->workqueue = create_singlethread_workqueue( |
1187 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1188 | if (drv_data->workqueue == NULL) |
1189 | return -EBUSY; | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
c52d4e5f | 1194 | static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1195 | { |
1196 | unsigned long flags; | |
1197 | ||
1198 | spin_lock_irqsave(&drv_data->lock, flags); | |
1199 | ||
f4f50c3f | 1200 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1201 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1202 | return -EBUSY; | |
1203 | } | |
1204 | ||
f4f50c3f | 1205 | drv_data->running = true; |
a5f6abd4 WB |
1206 | drv_data->cur_msg = NULL; |
1207 | drv_data->cur_transfer = NULL; | |
1208 | drv_data->cur_chip = NULL; | |
1209 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1210 | ||
1211 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
c52d4e5f | 1216 | static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1217 | { |
1218 | unsigned long flags; | |
1219 | unsigned limit = 500; | |
1220 | int status = 0; | |
1221 | ||
1222 | spin_lock_irqsave(&drv_data->lock, flags); | |
1223 | ||
1224 | /* | |
1225 | * This is a bit lame, but is optimized for the common execution path. | |
1226 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1227 | * execution path (pump_messages) would be required to call wake_up or | |
1228 | * friends on every SPI message. Do this instead | |
1229 | */ | |
f4f50c3f | 1230 | drv_data->running = false; |
850a28ec | 1231 | while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) { |
a5f6abd4 WB |
1232 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1233 | msleep(10); | |
1234 | spin_lock_irqsave(&drv_data->lock, flags); | |
1235 | } | |
1236 | ||
1237 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1238 | status = -EBUSY; | |
1239 | ||
1240 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1241 | ||
1242 | return status; | |
1243 | } | |
1244 | ||
c52d4e5f | 1245 | static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data) |
a5f6abd4 WB |
1246 | { |
1247 | int status; | |
1248 | ||
138f97cd | 1249 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1250 | if (status != 0) |
1251 | return status; | |
1252 | ||
1253 | destroy_workqueue(drv_data->workqueue); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
2deff8d6 | 1258 | static int bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1259 | { |
1260 | struct device *dev = &pdev->dev; | |
1261 | struct bfin5xx_spi_master *platform_info; | |
1262 | struct spi_master *master; | |
9c0a788b | 1263 | struct bfin_spi_master_data *drv_data; |
a32c691d | 1264 | struct resource *res; |
a5f6abd4 WB |
1265 | int status = 0; |
1266 | ||
8074cf06 | 1267 | platform_info = dev_get_platdata(dev); |
a5f6abd4 WB |
1268 | |
1269 | /* Allocate master with space for drv_data */ | |
2a045131 | 1270 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1271 | if (!master) { |
1272 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1273 | return -ENOMEM; | |
1274 | } | |
131b17d4 | 1275 | |
a5f6abd4 WB |
1276 | drv_data = spi_master_get_devdata(master); |
1277 | drv_data->master = master; | |
1278 | drv_data->master_info = platform_info; | |
1279 | drv_data->pdev = pdev; | |
003d9226 | 1280 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1281 | |
e7db06b5 DB |
1282 | /* the spi->mode bits supported by this driver: */ |
1283 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
24778be2 | 1284 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
a5f6abd4 WB |
1285 | master->bus_num = pdev->id; |
1286 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1287 | master->cleanup = bfin_spi_cleanup; |
1288 | master->setup = bfin_spi_setup; | |
1289 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1290 | |
a32c691d BW |
1291 | /* Find and map our resources */ |
1292 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1293 | if (res == NULL) { | |
1294 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1295 | status = -ENOENT; | |
1296 | goto out_error_get_res; | |
1297 | } | |
1298 | ||
47885ce8 MF |
1299 | drv_data->regs = ioremap(res->start, resource_size(res)); |
1300 | if (drv_data->regs == NULL) { | |
a32c691d BW |
1301 | dev_err(dev, "Cannot map IO\n"); |
1302 | status = -ENXIO; | |
1303 | goto out_error_ioremap; | |
1304 | } | |
1305 | ||
f6a6d966 YL |
1306 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1307 | if (res == NULL) { | |
a32c691d BW |
1308 | dev_err(dev, "No DMA channel specified\n"); |
1309 | status = -ENOENT; | |
f6a6d966 YL |
1310 | goto out_error_free_io; |
1311 | } | |
1312 | drv_data->dma_channel = res->start; | |
1313 | ||
1314 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1315 | if (drv_data->spi_irq < 0) { | |
1316 | dev_err(dev, "No spi pio irq specified\n"); | |
1317 | status = -ENOENT; | |
1318 | goto out_error_free_io; | |
a32c691d BW |
1319 | } |
1320 | ||
a5f6abd4 | 1321 | /* Initial and start queue */ |
138f97cd | 1322 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1323 | if (status != 0) { |
a32c691d | 1324 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1325 | goto out_error_queue_alloc; |
1326 | } | |
a32c691d | 1327 | |
138f97cd | 1328 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1329 | if (status != 0) { |
a32c691d | 1330 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1331 | goto out_error_queue_alloc; |
1332 | } | |
1333 | ||
f9e522ca VM |
1334 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1335 | if (status != 0) { | |
1336 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1337 | goto out_error_queue_alloc; | |
1338 | } | |
1339 | ||
bb8beecd WM |
1340 | /* Reset SPI registers. If these registers were used by the boot loader, |
1341 | * the sky may fall on your head if you enable the dma controller. | |
1342 | */ | |
47885ce8 MF |
1343 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1344 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
bb8beecd | 1345 | |
a5f6abd4 WB |
1346 | /* Register with the SPI framework */ |
1347 | platform_set_drvdata(pdev, drv_data); | |
1348 | status = spi_register_master(master); | |
1349 | if (status != 0) { | |
a32c691d | 1350 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1351 | goto out_error_queue_alloc; |
1352 | } | |
a32c691d | 1353 | |
47885ce8 MF |
1354 | dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n", |
1355 | DRV_DESC, DRV_VERSION, drv_data->regs, | |
bb90eb00 | 1356 | drv_data->dma_channel); |
a5f6abd4 WB |
1357 | return status; |
1358 | ||
cc2f81a6 | 1359 | out_error_queue_alloc: |
138f97cd | 1360 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1361 | out_error_free_io: |
47885ce8 | 1362 | iounmap(drv_data->regs); |
a32c691d BW |
1363 | out_error_ioremap: |
1364 | out_error_get_res: | |
a5f6abd4 | 1365 | spi_master_put(master); |
cc2f81a6 | 1366 | |
a5f6abd4 WB |
1367 | return status; |
1368 | } | |
1369 | ||
1370 | /* stop hardware and remove the driver */ | |
fd4a319b | 1371 | static int bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1372 | { |
9c0a788b | 1373 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1374 | int status = 0; |
1375 | ||
1376 | if (!drv_data) | |
1377 | return 0; | |
1378 | ||
1379 | /* Remove the queue */ | |
138f97cd | 1380 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1381 | if (status != 0) |
1382 | return status; | |
1383 | ||
1384 | /* Disable the SSP at the peripheral and SOC level */ | |
1385 | bfin_spi_disable(drv_data); | |
1386 | ||
1387 | /* Release DMA */ | |
1388 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1389 | if (dma_channel_active(drv_data->dma_channel)) |
1390 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1391 | } |
1392 | ||
f6a6d966 YL |
1393 | if (drv_data->irq_requested) { |
1394 | free_irq(drv_data->spi_irq, drv_data); | |
1395 | drv_data->irq_requested = 0; | |
1396 | } | |
1397 | ||
a5f6abd4 WB |
1398 | /* Disconnect from the SPI framework */ |
1399 | spi_unregister_master(drv_data->master); | |
1400 | ||
003d9226 | 1401 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1402 | |
a5f6abd4 WB |
1403 | return 0; |
1404 | } | |
1405 | ||
fbbfd68b JH |
1406 | #ifdef CONFIG_PM_SLEEP |
1407 | static int bfin_spi_suspend(struct device *dev) | |
a5f6abd4 | 1408 | { |
fbbfd68b | 1409 | struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev); |
a5f6abd4 WB |
1410 | int status = 0; |
1411 | ||
138f97cd | 1412 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1413 | if (status != 0) |
1414 | return status; | |
1415 | ||
47885ce8 MF |
1416 | drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl); |
1417 | drv_data->flag_reg = bfin_read(&drv_data->regs->flg); | |
b052fd0a BS |
1418 | |
1419 | /* | |
1420 | * reset SPI_CTL and SPI_FLG registers | |
1421 | */ | |
47885ce8 MF |
1422 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1423 | bfin_write(&drv_data->regs->flg, 0xFF00); | |
a5f6abd4 WB |
1424 | |
1425 | return 0; | |
1426 | } | |
1427 | ||
fbbfd68b | 1428 | static int bfin_spi_resume(struct device *dev) |
a5f6abd4 | 1429 | { |
fbbfd68b | 1430 | struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev); |
a5f6abd4 WB |
1431 | int status = 0; |
1432 | ||
47885ce8 MF |
1433 | bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg); |
1434 | bfin_write(&drv_data->regs->flg, drv_data->flag_reg); | |
a5f6abd4 WB |
1435 | |
1436 | /* Start the queue running */ | |
138f97cd | 1437 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1438 | if (status != 0) { |
fbbfd68b | 1439 | dev_err(dev, "problem starting queue (%d)\n", status); |
a5f6abd4 WB |
1440 | return status; |
1441 | } | |
1442 | ||
1443 | return 0; | |
1444 | } | |
fbbfd68b JH |
1445 | |
1446 | static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume); | |
1447 | ||
1448 | #define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops) | |
a5f6abd4 | 1449 | #else |
fbbfd68b JH |
1450 | #define BFIN_SPI_PM_OPS NULL |
1451 | #endif | |
a5f6abd4 | 1452 | |
7e38c3c4 | 1453 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1454 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1455 | .driver = { |
a32c691d | 1456 | .name = DRV_NAME, |
fbbfd68b | 1457 | .pm = BFIN_SPI_PM_OPS, |
88b40369 | 1458 | }, |
db9371b8 | 1459 | .probe = bfin_spi_probe, |
fd4a319b | 1460 | .remove = bfin_spi_remove, |
a5f6abd4 WB |
1461 | }; |
1462 | ||
138f97cd | 1463 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1464 | { |
db9371b8 | 1465 | return platform_driver_register(&bfin_spi_driver); |
a5f6abd4 | 1466 | } |
6f7c17f4 | 1467 | subsys_initcall(bfin_spi_init); |
a5f6abd4 | 1468 | |
138f97cd | 1469 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1470 | { |
138f97cd | 1471 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1472 | } |
138f97cd | 1473 | module_exit(bfin_spi_exit); |