[deliverable/linux.git] / drivers / spi / spi-clps711x.c

/*
 *  CLPS711X SPI bus driver
 *
 *  Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/io.h>
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/spi-clps711x.h>

#include <mach/hardware.h>

#define DRIVER_NAME	"spi-clps711x"

struct spi_clps711x_data {
	struct completion	done;

	struct clk		*spi_clk;
	u32			max_speed_hz;

	u8			*tx_buf;
	u8			*rx_buf;
	unsigned int		bpw;
	int			len;
};

static int spi_clps711x_setup(struct spi_device *spi)
{
	/* We are expect that SPI-device is not selected */
	gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));

	return 0;
}

static void spi_clps711x_setup_mode(struct spi_device *spi)
{
	/* Setup edge for transfer */
	if (spi->mode & SPI_CPHA)
		clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
	else
		clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
}

static void spi_clps711x_setup_xfer(struct spi_device *spi,
				    struct spi_transfer *xfer)
{
	u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
	struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);

	/* Setup SPI frequency divider */
	if (!speed || (speed >= hw->max_speed_hz))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(3), SYSCON1);
	else if (speed >= (hw->max_speed_hz / 2))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(2), SYSCON1);
	else if (speed >= (hw->max_speed_hz / 8))
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(1), SYSCON1);
	else
		clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
			    SYSCON1_ADCKSEL(0), SYSCON1);
}

static int spi_clps711x_transfer_one_message(struct spi_master *master,
					     struct spi_message *msg)
{
	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
	struct spi_device *spi = msg->spi;
	struct spi_transfer *xfer;

	spi_clps711x_setup_mode(spi);

	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		u8 data;

		spi_clps711x_setup_xfer(spi, xfer);

		gpio_set_value(spi->cs_gpio, !!(spi->mode & SPI_CS_HIGH));

		reinit_completion(&hw->done);

		hw->len = xfer->len;
		hw->bpw = xfer->bits_per_word ? : spi->bits_per_word;
		hw->tx_buf = (u8 *)xfer->tx_buf;
		hw->rx_buf = (u8 *)xfer->rx_buf;

		/* Initiate transfer */
		data = hw->tx_buf ? *hw->tx_buf++ : 0;
		clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
			    SYNCIO);

		wait_for_completion(&hw->done);

		if (xfer->delay_usecs)
			udelay(xfer->delay_usecs);

		if (xfer->cs_change ||
		    list_is_last(&xfer->transfer_list, &msg->transfers))
			gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));

		msg->actual_length += xfer->len;
	}

	msg->status = 0;
	spi_finalize_current_message(master);

	return 0;
}

static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
{
	struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id;
	u8 data;

	/* Handle RX */
	data = clps_readb(SYNCIO);
	if (hw->rx_buf)
		*hw->rx_buf++ = data;

	/* Handle TX */
	if (--hw->len > 0) {
		data = hw->tx_buf ? *hw->tx_buf++ : 0;
		clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
			    SYNCIO);
	} else
		complete(&hw->done);

	return IRQ_HANDLED;
}

static int spi_clps711x_probe(struct platform_device *pdev)
{
	int i, ret;
	struct spi_master *master;
	struct spi_clps711x_data *hw;
	struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);

	if (!pdata) {
		dev_err(&pdev->dev, "No platform data supplied\n");
		return -EINVAL;
	}

	if (pdata->num_chipselect < 1) {
		dev_err(&pdev->dev, "At least one CS must be defined\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(*hw));
	if (!master)
		return -ENOMEM;

	master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
					pdata->num_chipselect, GFP_KERNEL);
	if (!master->cs_gpios) {
		ret = -ENOMEM;
		goto err_out;
	}

	master->bus_num = pdev->id;
	master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
	master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(1, 8);
	master->num_chipselect = pdata->num_chipselect;
	master->setup = spi_clps711x_setup;
	master->transfer_one_message = spi_clps711x_transfer_one_message;

	hw = spi_master_get_devdata(master);

	for (i = 0; i < master->num_chipselect; i++) {
		master->cs_gpios[i] = pdata->chipselect[i];
		if (!gpio_is_valid(master->cs_gpios[i])) {
			dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i);
			ret = -EINVAL;
			goto err_out;
		}
		if (devm_gpio_request(&pdev->dev, master->cs_gpios[i], NULL)) {
			dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
			ret = -EINVAL;
			goto err_out;
		}
	}

	hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
	if (IS_ERR(hw->spi_clk)) {
		dev_err(&pdev->dev, "Can't get clocks\n");
		ret = PTR_ERR(hw->spi_clk);
		goto err_out;
	}
	hw->max_speed_hz = clk_get_rate(hw->spi_clk);

	init_completion(&hw->done);
	platform_set_drvdata(pdev, master);

	/* Disable extended mode due hardware problems */
	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);

	/* Clear possible pending interrupt */
	clps_readl(SYNCIO);

	ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
			       dev_name(&pdev->dev), hw);
	if (ret) {
		dev_err(&pdev->dev, "Can't request IRQ\n");
		goto err_out;
	}

	ret = devm_spi_register_master(&pdev->dev, master);
	if (!ret) {
		dev_info(&pdev->dev,
			 "SPI bus driver initialized. Master clock %u Hz\n",
			 hw->max_speed_hz);
		return 0;
	}

	dev_err(&pdev->dev, "Failed to register master\n");

err_out:
	spi_master_put(master);

	return ret;
}

static struct platform_driver clps711x_spi_driver = {
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	},
	.probe	= spi_clps711x_probe,
};
module_platform_driver(clps711x_spi_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("CLPS711X SPI bus driver");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
161b96c3 AS	1	/*
	2	* CLPS711X SPI bus driver
	3	*
98984796	4	* Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
161b96c3 AS	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/clk.h>
	14	#include <linux/init.h>
	15	#include <linux/gpio.h>
	16	#include <linux/delay.h>
	17	#include <linux/module.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/spi/spi.h>
	21	#include <linux/platform_data/spi-clps711x.h>
	22
	23	#include <mach/hardware.h>
	24
	25	#define DRIVER_NAME "spi-clps711x"
	26
	27	struct spi_clps711x_data {
	28	struct completion done;
	29
	30	struct clk *spi_clk;
	31	u32 max_speed_hz;
	32
	33	u8 *tx_buf;
	34	u8 *rx_buf;
8dda9d9a	35	unsigned int bpw;
161b96c3	36	int len;
161b96c3 AS	37	};
	38
	39	static int spi_clps711x_setup(struct spi_device *spi)
	40	{
161b96c3	41	/* We are expect that SPI-device is not selected */
3e9ea4b4	42	gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
161b96c3 AS	43
	44	return 0;
	45	}
	46
	47	static void spi_clps711x_setup_mode(struct spi_device *spi)
	48	{
	49	/* Setup edge for transfer */
	50	if (spi->mode & SPI_CPHA)
	51	clps_writew(clps_readw(SYSCON3) \| SYSCON3_ADCCKNSEN, SYSCON3);
	52	else
	53	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
	54	}
	55
8dda9d9a AS	56	static void spi_clps711x_setup_xfer(struct spi_device *spi,
8dda9d9a AS	57	struct spi_transfer *xfer)
161b96c3 AS	58	{
161b96c3 AS	59	u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
161b96c3 AS	60	struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
161b96c3 AS	61
161b96c3 AS	62	/* Setup SPI frequency divider */
	63	if (!speed \|\| (speed >= hw->max_speed_hz))
	64	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	65	SYSCON1_ADCKSEL(3), SYSCON1);
	66	else if (speed >= (hw->max_speed_hz / 2))
	67	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	68	SYSCON1_ADCKSEL(2), SYSCON1);
	69	else if (speed >= (hw->max_speed_hz / 8))
	70	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	71	SYSCON1_ADCKSEL(1), SYSCON1);
	72	else
	73	clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) \|
	74	SYSCON1_ADCKSEL(0), SYSCON1);
161b96c3 AS	75	}
	76
	77	static int spi_clps711x_transfer_one_message(struct spi_master *master,
	78	struct spi_message *msg)
	79	{
	80	struct spi_clps711x_data *hw = spi_master_get_devdata(master);
8dda9d9a	81	struct spi_device *spi = msg->spi;
161b96c3	82	struct spi_transfer *xfer;
161b96c3	83
8dda9d9a	84	spi_clps711x_setup_mode(spi);
161b96c3 AS	85
161b96c3 AS	86	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
c7a26f12 AS	87	u8 data;
c7a26f12 AS	88
8dda9d9a	89	spi_clps711x_setup_xfer(spi, xfer);
161b96c3	90
3e9ea4b4	91	gpio_set_value(spi->cs_gpio, !!(spi->mode & SPI_CS_HIGH));
161b96c3	92
16735d02	93	reinit_completion(&hw->done);
161b96c3	94
161b96c3	95	hw->len = xfer->len;
8dda9d9a	96	hw->bpw = xfer->bits_per_word ? : spi->bits_per_word;
161b96c3 AS	97	hw->tx_buf = (u8 *)xfer->tx_buf;
	98	hw->rx_buf = (u8 *)xfer->rx_buf;
	99
	100	/* Initiate transfer */
c7a26f12	101	data = hw->tx_buf ? *hw->tx_buf++ : 0;
8dda9d9a AS	102	clps_writel(data \| SYNCIO_FRMLEN(hw->bpw) \| SYNCIO_TXFRMEN,
8dda9d9a AS	103	SYNCIO);
161b96c3 AS	104
	105	wait_for_completion(&hw->done);
	106
	107	if (xfer->delay_usecs)
	108	udelay(xfer->delay_usecs);
	109
	110	if (xfer->cs_change \|\|
	111	list_is_last(&xfer->transfer_list, &msg->transfers))
3e9ea4b4	112	gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
161b96c3 AS	113
	114	msg->actual_length += xfer->len;
	115	}
	116
8dda9d9a	117	msg->status = 0;
161b96c3 AS	118	spi_finalize_current_message(master);
	119
	120	return 0;
	121	}
	122
	123	static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
	124	{
	125	struct spi_clps711x_data hw = (struct spi_clps711x_data )dev_id;
c7a26f12	126	u8 data;
161b96c3 AS	127
	128	/* Handle RX */
	129	data = clps_readb(SYNCIO);
	130	if (hw->rx_buf)
c7a26f12	131	*hw->rx_buf++ = data;
161b96c3 AS	132
161b96c3 AS	133	/* Handle TX */
c7a26f12 AS	134	if (--hw->len > 0) {
c7a26f12 AS	135	data = hw->tx_buf ? *hw->tx_buf++ : 0;
8dda9d9a AS	136	clps_writel(data \| SYNCIO_FRMLEN(hw->bpw) \| SYNCIO_TXFRMEN,
8dda9d9a AS	137	SYNCIO);
161b96c3 AS	138	} else
	139	complete(&hw->done);
	140
	141	return IRQ_HANDLED;
	142	}
	143
fd4a319b	144	static int spi_clps711x_probe(struct platform_device *pdev)
161b96c3 AS	145	{
	146	int i, ret;
	147	struct spi_master *master;
	148	struct spi_clps711x_data *hw;
	149	struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
	150
	151	if (!pdata) {
	152	dev_err(&pdev->dev, "No platform data supplied\n");
	153	return -EINVAL;
	154	}
	155
	156	if (pdata->num_chipselect < 1) {
	157	dev_err(&pdev->dev, "At least one CS must be defined\n");
	158	return -EINVAL;
	159	}
	160
3e9ea4b4 AS	161	master = spi_alloc_master(&pdev->dev, sizeof(*hw));
3e9ea4b4 AS	162	if (!master)
161b96c3	163	return -ENOMEM;
3e9ea4b4 AS	164
	165	master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) *
	166	pdata->num_chipselect, GFP_KERNEL);
	167	if (!master->cs_gpios) {
	168	ret = -ENOMEM;
	169	goto err_out;
161b96c3 AS	170	}
	171
	172	master->bus_num = pdev->id;
	173	master->mode_bits = SPI_CPHA \| SPI_CS_HIGH;
8dda9d9a	174	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
161b96c3 AS	175	master->num_chipselect = pdata->num_chipselect;
	176	master->setup = spi_clps711x_setup;
	177	master->transfer_one_message = spi_clps711x_transfer_one_message;
	178
	179	hw = spi_master_get_devdata(master);
	180
	181	for (i = 0; i < master->num_chipselect; i++) {
3e9ea4b4 AS	182	master->cs_gpios[i] = pdata->chipselect[i];
3e9ea4b4 AS	183	if (!gpio_is_valid(master->cs_gpios[i])) {
161b96c3 AS	184	dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i);
	185	ret = -EINVAL;
	186	goto err_out;
	187	}
3e9ea4b4	188	if (devm_gpio_request(&pdev->dev, master->cs_gpios[i], NULL)) {
161b96c3 AS	189	dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
	190	ret = -EINVAL;
	191	goto err_out;
	192	}
	193	}
	194
	195	hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
	196	if (IS_ERR(hw->spi_clk)) {
	197	dev_err(&pdev->dev, "Can't get clocks\n");
	198	ret = PTR_ERR(hw->spi_clk);
	199	goto err_out;
	200	}
	201	hw->max_speed_hz = clk_get_rate(hw->spi_clk);
	202
	203	init_completion(&hw->done);
	204	platform_set_drvdata(pdev, master);
	205
	206	/* Disable extended mode due hardware problems */
	207	clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);
	208
	209	/* Clear possible pending interrupt */
	210	clps_readl(SYNCIO);
	211
	212	ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
	213	dev_name(&pdev->dev), hw);
	214	if (ret) {
	215	dev_err(&pdev->dev, "Can't request IRQ\n");
c7083790	216	goto err_out;
161b96c3 AS	217	}
161b96c3 AS	218
c493fc4b	219	ret = devm_spi_register_master(&pdev->dev, master);
161b96c3 AS	220	if (!ret) {
	221	dev_info(&pdev->dev,
	222	"SPI bus driver initialized. Master clock %u Hz\n",
	223	hw->max_speed_hz);
	224	return 0;
	225	}
	226
	227	dev_err(&pdev->dev, "Failed to register master\n");
161b96c3	228
161b96c3	229	err_out:
161b96c3	230	spi_master_put(master);
161b96c3 AS	231
	232	return ret;
	233	}
	234
161b96c3 AS	235	static struct platform_driver clps711x_spi_driver = {
	236	.driver = {
	237	.name = DRIVER_NAME,
	238	.owner = THIS_MODULE,
	239	},
	240	.probe = spi_clps711x_probe,
161b96c3 AS	241	};
	242	module_platform_driver(clps711x_spi_driver);
	243
	244	MODULE_LICENSE("GPL");
	245	MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
	246	MODULE_DESCRIPTION("CLPS711X SPI bus driver");
350a9b33	247	MODULE_ALIAS("platform:" DRIVER_NAME);