[deliverable/linux.git] / drivers / spi / spi-coldfire-qspi.c

/*
 * Freescale/Motorola Coldfire Queued SPI driver
 *
 * Copyright 2010 Steven King <sfking@fdwdc.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
 *
*/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/pm_runtime.h>

#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfqspi.h>

#define	DRIVER_NAME "mcfqspi"

#define	MCFQSPI_BUSCLK			(MCF_BUSCLK / 2)

#define	MCFQSPI_QMR			0x00
#define		MCFQSPI_QMR_MSTR	0x8000
#define		MCFQSPI_QMR_CPOL	0x0200
#define		MCFQSPI_QMR_CPHA	0x0100
#define	MCFQSPI_QDLYR			0x04
#define		MCFQSPI_QDLYR_SPE	0x8000
#define	MCFQSPI_QWR			0x08
#define		MCFQSPI_QWR_HALT	0x8000
#define		MCFQSPI_QWR_WREN	0x4000
#define		MCFQSPI_QWR_CSIV	0x1000
#define	MCFQSPI_QIR			0x0C
#define		MCFQSPI_QIR_WCEFB	0x8000
#define		MCFQSPI_QIR_ABRTB	0x4000
#define		MCFQSPI_QIR_ABRTL	0x1000
#define		MCFQSPI_QIR_WCEFE	0x0800
#define		MCFQSPI_QIR_ABRTE	0x0400
#define		MCFQSPI_QIR_SPIFE	0x0100
#define		MCFQSPI_QIR_WCEF	0x0008
#define		MCFQSPI_QIR_ABRT	0x0004
#define		MCFQSPI_QIR_SPIF	0x0001
#define	MCFQSPI_QAR			0x010
#define		MCFQSPI_QAR_TXBUF	0x00
#define		MCFQSPI_QAR_RXBUF	0x10
#define		MCFQSPI_QAR_CMDBUF	0x20
#define	MCFQSPI_QDR			0x014
#define	MCFQSPI_QCR			0x014
#define		MCFQSPI_QCR_CONT	0x8000
#define		MCFQSPI_QCR_BITSE	0x4000
#define		MCFQSPI_QCR_DT		0x2000

struct mcfqspi {
	void __iomem *iobase;
	int irq;
	struct clk *clk;
	struct mcfqspi_cs_control *cs_control;

	wait_queue_head_t waitq;

	struct device *dev;
};

static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
}

static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
}

static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
}

static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
}

static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
}

static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
}

static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
{
	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
}

static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
{
	return readw(mcfqspi->iobase + MCFQSPI_QDR);
}

static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
			    bool cs_high)
{
	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
}

static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
				bool cs_high)
{
	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
}

static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
{
	return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ?
		mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
}

static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
{
	if (mcfqspi->cs_control && mcfqspi->cs_control->teardown)
		mcfqspi->cs_control->teardown(mcfqspi->cs_control);
}

static u8 mcfqspi_qmr_baud(u32 speed_hz)
{
	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
}

static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
{
	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
}

static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
{
	struct mcfqspi *mcfqspi = dev_id;

	/* clear interrupt */
	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
	wake_up(&mcfqspi->waitq);

	return IRQ_HANDLED;
}

static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
				  const u8 *txbuf, u8 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
				   const u16 *txbuf, u16 *rxbuf)
{
	unsigned i, n, offset = 0;

	n = min(count, 16u);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
	for (i = 0; i < n; ++i)
		mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);

	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
	if (txbuf)
		for (i = 0; i < n; ++i)
			mcfqspi_wr_qdr(mcfqspi, *txbuf++);
	else
		for (i = 0; i < count; ++i)
			mcfqspi_wr_qdr(mcfqspi, 0);

	count -= n;
	if (count) {
		u16 qwr = 0xf08;
		mcfqspi_wr_qwr(mcfqspi, 0x700);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);

		do {
			wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
			mcfqspi_wr_qwr(mcfqspi, qwr);
			mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
			if (rxbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_RXBUF + offset);
				for (i = 0; i < 8; ++i)
					*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			}
			n = min(count, 8u);
			if (txbuf) {
				mcfqspi_wr_qar(mcfqspi,
					       MCFQSPI_QAR_TXBUF + offset);
				for (i = 0; i < n; ++i)
					mcfqspi_wr_qdr(mcfqspi, *txbuf++);
			}
			qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
			offset ^= 8;
			count -= n;
		} while (count);
		wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
		mcfqspi_wr_qwr(mcfqspi, qwr);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
		if (rxbuf) {
			mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
			for (i = 0; i < 8; ++i)
				*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
			offset ^= 8;
		}
	} else {
		mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
		mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
	}
	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
	if (rxbuf) {
		mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
		for (i = 0; i < n; ++i)
			*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
	}
}

static int mcfqspi_transfer_one_message(struct spi_master *master,
					 struct spi_message *msg)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	struct spi_device *spi = msg->spi;
	struct spi_transfer *t;
	int status = 0;

	list_for_each_entry(t, &msg->transfers, transfer_list) {
		bool cs_high = spi->mode & SPI_CS_HIGH;
		u16 qmr = MCFQSPI_QMR_MSTR;

		if (t->bits_per_word)
			qmr |= t->bits_per_word << 10;
		else
			qmr |= spi->bits_per_word << 10;
		if (spi->mode & SPI_CPHA)
			qmr |= MCFQSPI_QMR_CPHA;
		if (spi->mode & SPI_CPOL)
			qmr |= MCFQSPI_QMR_CPOL;
		if (t->speed_hz)
			qmr |= mcfqspi_qmr_baud(t->speed_hz);
		else
			qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
		mcfqspi_wr_qmr(mcfqspi, qmr);

		mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);

		mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
		if (t->bits_per_word == 8)
			mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf,
					t->rx_buf);
		else
			mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
					t->rx_buf);
		mcfqspi_wr_qir(mcfqspi, 0);

		if (t->delay_usecs)
			udelay(t->delay_usecs);
		if (t->cs_change) {
			if (!list_is_last(&t->transfer_list, &msg->transfers))
				mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
						cs_high);
		} else {
			if (list_is_last(&t->transfer_list, &msg->transfers))
				mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
						cs_high);
		}
		msg->actual_length += t->len;
	}
	msg->status = status;
	spi_finalize_current_message(master);

	return status;

}

static int mcfqspi_prepare_transfer_hw(struct spi_master *master)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	pm_runtime_get_sync(mcfqspi->dev);

	return 0;
}

static int mcfqspi_unprepare_transfer_hw(struct spi_master *master)
{
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	pm_runtime_put_sync(mcfqspi->dev);

	return 0;
}

static int mcfqspi_setup(struct spi_device *spi)
{
	if ((spi->bits_per_word < 8) || (spi->bits_per_word > 16)) {
		dev_dbg(&spi->dev, "%d bits per word is not supported\n",
			spi->bits_per_word);
		return -EINVAL;
	}
	if (spi->chip_select >= spi->master->num_chipselect) {
		dev_dbg(&spi->dev, "%d chip select is out of range\n",
			spi->chip_select);
		return -EINVAL;
	}

	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
			    spi->chip_select, spi->mode & SPI_CS_HIGH);

	dev_dbg(&spi->dev,
			"bits per word %d, chip select %d, speed %d KHz\n",
			spi->bits_per_word, spi->chip_select,
			(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
			/ 1000);

	return 0;
}

static int mcfqspi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mcfqspi *mcfqspi;
	struct resource *res;
	struct mcfqspi_platform_data *pdata;
	int status;

	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	if (master == NULL) {
		dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
		return -ENOMEM;
	}

	mcfqspi = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_dbg(&pdev->dev, "platform_get_resource failed\n");
		status = -ENXIO;
		goto fail0;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_dbg(&pdev->dev, "request_mem_region failed\n");
		status = -EBUSY;
		goto fail0;
	}

	mcfqspi->iobase = ioremap(res->start, resource_size(res));
	if (!mcfqspi->iobase) {
		dev_dbg(&pdev->dev, "ioremap failed\n");
		status = -ENOMEM;
		goto fail1;
	}

	mcfqspi->irq = platform_get_irq(pdev, 0);
	if (mcfqspi->irq < 0) {
		dev_dbg(&pdev->dev, "platform_get_irq failed\n");
		status = -ENXIO;
		goto fail2;
	}

	status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0,
			     pdev->name, mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "request_irq failed\n");
		goto fail2;
	}

	mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk");
	if (IS_ERR(mcfqspi->clk)) {
		dev_dbg(&pdev->dev, "clk_get failed\n");
		status = PTR_ERR(mcfqspi->clk);
		goto fail3;
	}
	clk_enable(mcfqspi->clk);

	pdata = pdev->dev.platform_data;
	if (!pdata) {
		dev_dbg(&pdev->dev, "platform data is missing\n");
		goto fail4;
	}
	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->num_chipselect;

	mcfqspi->cs_control = pdata->cs_control;
	status = mcfqspi_cs_setup(mcfqspi);
	if (status) {
		dev_dbg(&pdev->dev, "error initializing cs_control\n");
		goto fail4;
	}

	init_waitqueue_head(&mcfqspi->waitq);
	mcfqspi->dev = &pdev->dev;

	master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
	master->setup = mcfqspi_setup;
	master->transfer_one_message = mcfqspi_transfer_one_message;
	master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
	master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw;

	platform_set_drvdata(pdev, master);

	status = spi_register_master(master);
	if (status) {
		dev_dbg(&pdev->dev, "spi_register_master failed\n");
		goto fail5;
	}
	pm_runtime_enable(mcfqspi->dev);

	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");

	return 0;

fail5:
	mcfqspi_cs_teardown(mcfqspi);
fail4:
	clk_disable(mcfqspi->clk);
	clk_put(mcfqspi->clk);
fail3:
	free_irq(mcfqspi->irq, mcfqspi);
fail2:
	iounmap(mcfqspi->iobase);
fail1:
	release_mem_region(res->start, resource_size(res));
fail0:
	spi_master_put(master);

	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");

	return status;
}

static int mcfqspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_disable(mcfqspi->dev);
	/* disable the hardware (set the baud rate to 0) */
	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);

	platform_set_drvdata(pdev, NULL);
	mcfqspi_cs_teardown(mcfqspi);
	clk_disable(mcfqspi->clk);
	clk_put(mcfqspi->clk);
	free_irq(mcfqspi->irq, mcfqspi);
	iounmap(mcfqspi->iobase);
	release_mem_region(res->start, resource_size(res));
	spi_unregister_master(master);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mcfqspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	spi_master_suspend(master);

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);

	spi_master_resume(master);

	clk_enable(mcfqspi->clk);

	return 0;
}
#endif

#ifdef CONFIG_PM_RUNTIME
static int mcfqspi_runtime_suspend(struct device *dev)
{
	struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));

	clk_disable(mcfqspi->clk);

	return 0;
}

static int mcfqspi_runtime_resume(struct device *dev)
{
	struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));

	clk_enable(mcfqspi->clk);

	return 0;
}
#endif

static const struct dev_pm_ops mcfqspi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
			NULL)
};

static struct platform_driver mcfqspi_driver = {
	.driver.name	= DRIVER_NAME,
	.driver.owner	= THIS_MODULE,
	.driver.pm	= &mcfqspi_pm,
	.probe		= mcfqspi_probe,
	.remove		= mcfqspi_remove,
};
module_platform_driver(mcfqspi_driver);

MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
34b8c661 SK	1	/*
	2	* Freescale/Motorola Coldfire Queued SPI driver
	3	*
	4	* Copyright 2010 Steven King <sfking@fdwdc.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/errno.h>
	26	#include <linux/platform_device.h>
5e1c5335	27	#include <linux/sched.h>
34b8c661 SK	28	#include <linux/delay.h>
	29	#include <linux/io.h>
	30	#include <linux/clk.h>
	31	#include <linux/err.h>
	32	#include <linux/spi/spi.h>
bc98d13f	33	#include <linux/pm_runtime.h>
34b8c661 SK	34
34b8c661 SK	35	#include <asm/coldfire.h>
0b4bf782	36	#include <asm/mcfsim.h>
34b8c661 SK	37	#include <asm/mcfqspi.h>
	38
	39	#define DRIVER_NAME "mcfqspi"
	40
	41	#define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
	42
	43	#define MCFQSPI_QMR 0x00
	44	#define MCFQSPI_QMR_MSTR 0x8000
	45	#define MCFQSPI_QMR_CPOL 0x0200
	46	#define MCFQSPI_QMR_CPHA 0x0100
	47	#define MCFQSPI_QDLYR 0x04
	48	#define MCFQSPI_QDLYR_SPE 0x8000
	49	#define MCFQSPI_QWR 0x08
	50	#define MCFQSPI_QWR_HALT 0x8000
	51	#define MCFQSPI_QWR_WREN 0x4000
	52	#define MCFQSPI_QWR_CSIV 0x1000
	53	#define MCFQSPI_QIR 0x0C
	54	#define MCFQSPI_QIR_WCEFB 0x8000
	55	#define MCFQSPI_QIR_ABRTB 0x4000
	56	#define MCFQSPI_QIR_ABRTL 0x1000
	57	#define MCFQSPI_QIR_WCEFE 0x0800
	58	#define MCFQSPI_QIR_ABRTE 0x0400
	59	#define MCFQSPI_QIR_SPIFE 0x0100
	60	#define MCFQSPI_QIR_WCEF 0x0008
	61	#define MCFQSPI_QIR_ABRT 0x0004
	62	#define MCFQSPI_QIR_SPIF 0x0001
	63	#define MCFQSPI_QAR 0x010
	64	#define MCFQSPI_QAR_TXBUF 0x00
	65	#define MCFQSPI_QAR_RXBUF 0x10
	66	#define MCFQSPI_QAR_CMDBUF 0x20
	67	#define MCFQSPI_QDR 0x014
	68	#define MCFQSPI_QCR 0x014
	69	#define MCFQSPI_QCR_CONT 0x8000
	70	#define MCFQSPI_QCR_BITSE 0x4000
	71	#define MCFQSPI_QCR_DT 0x2000
	72
	73	struct mcfqspi {
	74	void __iomem *iobase;
	75	int irq;
	76	struct clk *clk;
	77	struct mcfqspi_cs_control *cs_control;
	78
	79	wait_queue_head_t waitq;
	80
bc98d13f	81	struct device *dev;
34b8c661 SK	82	};
	83
	84	static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
	85	{
	86	writew(val, mcfqspi->iobase + MCFQSPI_QMR);
	87	}
	88
	89	static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
	90	{
	91	writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
	92	}
	93
	94	static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
	95	{
	96	return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
	97	}
	98
	99	static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
	100	{
	101	writew(val, mcfqspi->iobase + MCFQSPI_QWR);
	102	}
	103
	104	static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
	105	{
	106	writew(val, mcfqspi->iobase + MCFQSPI_QIR);
	107	}
	108
	109	static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
	110	{
	111	writew(val, mcfqspi->iobase + MCFQSPI_QAR);
	112	}
	113
	114	static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
	115	{
	116	writew(val, mcfqspi->iobase + MCFQSPI_QDR);
	117	}
	118
	119	static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
	120	{
	121	return readw(mcfqspi->iobase + MCFQSPI_QDR);
	122	}
	123
	124	static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
	125	bool cs_high)
	126	{
	127	mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
	128	}
	129
	130	static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
	131	bool cs_high)
	132	{
	133	mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
	134	}
	135
	136	static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
	137	{
	138	return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ?
	139	mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
	140	}
	141
	142	static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
	143	{
	144	if (mcfqspi->cs_control && mcfqspi->cs_control->teardown)
	145	mcfqspi->cs_control->teardown(mcfqspi->cs_control);
146	}
147
148	static u8 mcfqspi_qmr_baud(u32 speed_hz)
149	{
150	return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
151	}
152
153	static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
154	{
155	return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
156	}
157
158	static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
159	{
160	struct mcfqspi *mcfqspi = dev_id;
161
162	/* clear interrupt */
163	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE \| MCFQSPI_QIR_SPIF);
164	wake_up(&mcfqspi->waitq);
165
166	return IRQ_HANDLED;
167	}
168
169	static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
170	const u8 txbuf, u8 rxbuf)
171	{
172	unsigned i, n, offset = 0;
173
174	n = min(count, 16u);
175
176	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
177	for (i = 0; i < n; ++i)
178	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
179
180	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
181	if (txbuf)
182	for (i = 0; i < n; ++i)
183	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
184	else
185	for (i = 0; i < count; ++i)
186	mcfqspi_wr_qdr(mcfqspi, 0);
187
188	count -= n;
189	if (count) {
190	u16 qwr = 0xf08;
191	mcfqspi_wr_qwr(mcfqspi, 0x700);
192	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
193
194	do {
195	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
196	mcfqspi_wr_qwr(mcfqspi, qwr);
197	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
198	if (rxbuf) {
199	mcfqspi_wr_qar(mcfqspi,
200	MCFQSPI_QAR_RXBUF + offset);
201	for (i = 0; i < 8; ++i)
202	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
203	}
204	n = min(count, 8u);
205	if (txbuf) {
206	mcfqspi_wr_qar(mcfqspi,
207	MCFQSPI_QAR_TXBUF + offset);
208	for (i = 0; i < n; ++i)
209	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
210	}
211	qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
212	offset ^= 8;
213	count -= n;
214	} while (count);
215	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
216	mcfqspi_wr_qwr(mcfqspi, qwr);
217	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
218	if (rxbuf) {
219	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
220	for (i = 0; i < 8; ++i)
221	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
222	offset ^= 8;
223	}
224	} else {
225	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
226	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
227	}
228	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
229	if (rxbuf) {
230	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
231	for (i = 0; i < n; ++i)
232	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
233	}
234	}
235
236	static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
237	const u16 txbuf, u16 rxbuf)
238	{
239	unsigned i, n, offset = 0;
240
241	n = min(count, 16u);
242
243	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
244	for (i = 0; i < n; ++i)
245	mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
246
247	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
248	if (txbuf)
249	for (i = 0; i < n; ++i)
250	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
251	else
252	for (i = 0; i < count; ++i)
253	mcfqspi_wr_qdr(mcfqspi, 0);
254
255	count -= n;
256	if (count) {
257	u16 qwr = 0xf08;
258	mcfqspi_wr_qwr(mcfqspi, 0x700);
259	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
260
261	do {
262	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
263	mcfqspi_wr_qwr(mcfqspi, qwr);
264	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
265	if (rxbuf) {
266	mcfqspi_wr_qar(mcfqspi,
267	MCFQSPI_QAR_RXBUF + offset);
268	for (i = 0; i < 8; ++i)
269	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
270	}
271	n = min(count, 8u);
272	if (txbuf) {
273	mcfqspi_wr_qar(mcfqspi,
274	MCFQSPI_QAR_TXBUF + offset);
275	for (i = 0; i < n; ++i)
276	mcfqspi_wr_qdr(mcfqspi, *txbuf++);
277	}
278	qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
279	offset ^= 8;
280	count -= n;
281	} while (count);
282	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
283	mcfqspi_wr_qwr(mcfqspi, qwr);
284	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
285	if (rxbuf) {
286	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
287	for (i = 0; i < 8; ++i)
288	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
289	offset ^= 8;
290	}
291	} else {
292	mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
293	mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
294	}
295	wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
296	if (rxbuf) {
297	mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
298	for (i = 0; i < n; ++i)
299	*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
300	}
301	}
302
bc98d13f SK	303	static int mcfqspi_transfer_one_message(struct spi_master *master,
bc98d13f SK	304	struct spi_message *msg)
34b8c661	305	{
bc98d13f SK	306	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	307	struct spi_device *spi = msg->spi;
	308	struct spi_transfer *t;
	309	int status = 0;
	310
	311	list_for_each_entry(t, &msg->transfers, transfer_list) {
	312	bool cs_high = spi->mode & SPI_CS_HIGH;
	313	u16 qmr = MCFQSPI_QMR_MSTR;
	314
	315	if (t->bits_per_word)
	316	qmr \|= t->bits_per_word << 10;
	317	else
	318	qmr \|= spi->bits_per_word << 10;
	319	if (spi->mode & SPI_CPHA)
	320	qmr \|= MCFQSPI_QMR_CPHA;
	321	if (spi->mode & SPI_CPOL)
	322	qmr \|= MCFQSPI_QMR_CPOL;
	323	if (t->speed_hz)
	324	qmr \|= mcfqspi_qmr_baud(t->speed_hz);
	325	else
	326	qmr \|= mcfqspi_qmr_baud(spi->max_speed_hz);
	327	mcfqspi_wr_qmr(mcfqspi, qmr);
	328
	329	mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
	330
	331	mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
766ed704	332	if (t->bits_per_word == 8)
bc98d13f SK	333	mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf,
	334	t->rx_buf);
	335	else
	336	mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
	337	t->rx_buf);
	338	mcfqspi_wr_qir(mcfqspi, 0);
	339
	340	if (t->delay_usecs)
	341	udelay(t->delay_usecs);
	342	if (t->cs_change) {
	343	if (!list_is_last(&t->transfer_list, &msg->transfers))
	344	mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
	345	cs_high);
	346	} else {
	347	if (list_is_last(&t->transfer_list, &msg->transfers))
	348	mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
	349	cs_high);
34b8c661	350	}
bc98d13f	351	msg->actual_length += t->len;
34b8c661	352	}
bc98d13f SK	353	msg->status = status;
	354	spi_finalize_current_message(master);
	355
	356	return status;
	357
34b8c661 SK	358	}
34b8c661 SK	359
bc98d13f	360	static int mcfqspi_prepare_transfer_hw(struct spi_master *master)
34b8c661	361	{
bc98d13f	362	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
34b8c661	363
bc98d13f SK	364	pm_runtime_get_sync(mcfqspi->dev);
	365
	366	return 0;
	367	}
	368
	369	static int mcfqspi_unprepare_transfer_hw(struct spi_master *master)
	370	{
	371	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	372
	373	pm_runtime_put_sync(mcfqspi->dev);
34b8c661 SK	374
34b8c661 SK	375	return 0;
34b8c661 SK	376	}
	377
	378	static int mcfqspi_setup(struct spi_device *spi)
	379	{
	380	if ((spi->bits_per_word < 8) \|\| (spi->bits_per_word > 16)) {
	381	dev_dbg(&spi->dev, "%d bits per word is not supported\n",
	382	spi->bits_per_word);
	383	return -EINVAL;
	384	}
	385	if (spi->chip_select >= spi->master->num_chipselect) {
	386	dev_dbg(&spi->dev, "%d chip select is out of range\n",
	387	spi->chip_select);
	388	return -EINVAL;
	389	}
	390
	391	mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
	392	spi->chip_select, spi->mode & SPI_CS_HIGH);
	393
	394	dev_dbg(&spi->dev,
	395	"bits per word %d, chip select %d, speed %d KHz\n",
	396	spi->bits_per_word, spi->chip_select,
	397	(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
	398	/ 1000);
	399
	400	return 0;
	401	}
	402
fd4a319b	403	static int mcfqspi_probe(struct platform_device *pdev)
34b8c661 SK	404	{
	405	struct spi_master *master;
	406	struct mcfqspi *mcfqspi;
	407	struct resource *res;
	408	struct mcfqspi_platform_data *pdata;
	409	int status;
	410
	411	master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
	412	if (master == NULL) {
	413	dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
	414	return -ENOMEM;
	415	}
	416
	417	mcfqspi = spi_master_get_devdata(master);
	418
	419	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	420	if (!res) {
	421	dev_dbg(&pdev->dev, "platform_get_resource failed\n");
	422	status = -ENXIO;
	423	goto fail0;
	424	}
	425
	426	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	427	dev_dbg(&pdev->dev, "request_mem_region failed\n");
	428	status = -EBUSY;
	429	goto fail0;
	430	}
	431
	432	mcfqspi->iobase = ioremap(res->start, resource_size(res));
	433	if (!mcfqspi->iobase) {
	434	dev_dbg(&pdev->dev, "ioremap failed\n");
	435	status = -ENOMEM;
	436	goto fail1;
	437	}
	438
	439	mcfqspi->irq = platform_get_irq(pdev, 0);
	440	if (mcfqspi->irq < 0) {
	441	dev_dbg(&pdev->dev, "platform_get_irq failed\n");
	442	status = -ENXIO;
	443	goto fail2;
	444	}
	445
38ada214	446	status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0,
34b8c661 SK	447	pdev->name, mcfqspi);
	448	if (status) {
	449	dev_dbg(&pdev->dev, "request_irq failed\n");
	450	goto fail2;
	451	}
	452
	453	mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk");
	454	if (IS_ERR(mcfqspi->clk)) {
	455	dev_dbg(&pdev->dev, "clk_get failed\n");
	456	status = PTR_ERR(mcfqspi->clk);
	457	goto fail3;
	458	}
	459	clk_enable(mcfqspi->clk);
	460
34b8c661 SK	461	pdata = pdev->dev.platform_data;
	462	if (!pdata) {
	463	dev_dbg(&pdev->dev, "platform data is missing\n");
bc98d13f	464	goto fail4;
34b8c661 SK	465	}
	466	master->bus_num = pdata->bus_num;
	467	master->num_chipselect = pdata->num_chipselect;
	468
	469	mcfqspi->cs_control = pdata->cs_control;
	470	status = mcfqspi_cs_setup(mcfqspi);
	471	if (status) {
	472	dev_dbg(&pdev->dev, "error initializing cs_control\n");
bc98d13f	473	goto fail4;
34b8c661 SK	474	}
34b8c661 SK	475
bc98d13f SK	476	init_waitqueue_head(&mcfqspi->waitq);
	477	mcfqspi->dev = &pdev->dev;
	478
34b8c661 SK	479	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
34b8c661 SK	480	master->setup = mcfqspi_setup;
bc98d13f SK	481	master->transfer_one_message = mcfqspi_transfer_one_message;
	482	master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
	483	master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw;
34b8c661 SK	484
	485	platform_set_drvdata(pdev, master);
	486
	487	status = spi_register_master(master);
	488	if (status) {
	489	dev_dbg(&pdev->dev, "spi_register_master failed\n");
bc98d13f	490	goto fail5;
34b8c661	491	}
bc98d13f SK	492	pm_runtime_enable(mcfqspi->dev);
bc98d13f SK	493
34b8c661 SK	494	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
	495
	496	return 0;
	497
34b8c661	498	fail5:
bc98d13f	499	mcfqspi_cs_teardown(mcfqspi);
34b8c661 SK	500	fail4:
	501	clk_disable(mcfqspi->clk);
	502	clk_put(mcfqspi->clk);
	503	fail3:
	504	free_irq(mcfqspi->irq, mcfqspi);
	505	fail2:
	506	iounmap(mcfqspi->iobase);
	507	fail1:
	508	release_mem_region(res->start, resource_size(res));
	509	fail0:
	510	spi_master_put(master);
	511
	512	dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
	513
	514	return status;
	515	}
	516
fd4a319b	517	static int mcfqspi_remove(struct platform_device *pdev)
34b8c661 SK	518	{
	519	struct spi_master *master = platform_get_drvdata(pdev);
	520	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	521	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	522
bc98d13f	523	pm_runtime_disable(mcfqspi->dev);
34b8c661 SK	524	/* disable the hardware (set the baud rate to 0) */
	525	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
	526
	527	platform_set_drvdata(pdev, NULL);
	528	mcfqspi_cs_teardown(mcfqspi);
34b8c661 SK	529	clk_disable(mcfqspi->clk);
	530	clk_put(mcfqspi->clk);
	531	free_irq(mcfqspi->irq, mcfqspi);
	532	iounmap(mcfqspi->iobase);
	533	release_mem_region(res->start, resource_size(res));
	534	spi_unregister_master(master);
34b8c661 SK	535
	536	return 0;
	537	}
	538
bc98d13f	539	#ifdef CONFIG_PM_SLEEP
34b8c661 SK	540	static int mcfqspi_suspend(struct device *dev)
34b8c661 SK	541	{
af361079	542	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f SK	543	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	544
	545	spi_master_suspend(master);
34b8c661 SK	546
	547	clk_disable(mcfqspi->clk);
	548
	549	return 0;
	550	}
	551
	552	static int mcfqspi_resume(struct device *dev)
	553	{
af361079	554	struct spi_master *master = dev_get_drvdata(dev);
bc98d13f SK	555	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	556
	557	spi_master_resume(master);
34b8c661 SK	558
	559	clk_enable(mcfqspi->clk);
	560
	561	return 0;
	562	}
bc98d13f	563	#endif
34b8c661	564
bc98d13f SK	565	#ifdef CONFIG_PM_RUNTIME
	566	static int mcfqspi_runtime_suspend(struct device *dev)
	567	{
	568	struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
34b8c661	569
bc98d13f SK	570	clk_disable(mcfqspi->clk);
	571
	572	return 0;
	573	}
	574
	575	static int mcfqspi_runtime_resume(struct device *dev)
	576	{
	577	struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
	578
	579	clk_enable(mcfqspi->clk);
	580
	581	return 0;
	582	}
34b8c661 SK	583	#endif
34b8c661 SK	584
bc98d13f SK	585	static const struct dev_pm_ops mcfqspi_pm = {
	586	SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	587	SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
	588	NULL)
	589	};
	590
34b8c661 SK	591	static struct platform_driver mcfqspi_driver = {
	592	.driver.name = DRIVER_NAME,
	593	.driver.owner = THIS_MODULE,
bc98d13f	594	.driver.pm = &mcfqspi_pm,
940ab889	595	.probe = mcfqspi_probe,
fd4a319b	596	.remove = mcfqspi_remove,
34b8c661	597	};
940ab889	598	module_platform_driver(mcfqspi_driver);
34b8c661 SK	599
	600	MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
	601	MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
	602	MODULE_LICENSE("GPL");
	603	MODULE_ALIAS("platform:" DRIVER_NAME);