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34b8c661 SK |
1 | /* |
2 | * Freescale/Motorola Coldfire Queued SPI driver | |
3 | * | |
4 | * Copyright 2010 Steven King <sfking@fdwdc.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/platform_device.h> | |
5e1c5335 | 27 | #include <linux/sched.h> |
34b8c661 SK |
28 | #include <linux/delay.h> |
29 | #include <linux/io.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/spi/spi.h> | |
bc98d13f | 33 | #include <linux/pm_runtime.h> |
34b8c661 SK |
34 | |
35 | #include <asm/coldfire.h> | |
0b4bf782 | 36 | #include <asm/mcfsim.h> |
34b8c661 SK |
37 | #include <asm/mcfqspi.h> |
38 | ||
39 | #define DRIVER_NAME "mcfqspi" | |
40 | ||
41 | #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2) | |
42 | ||
43 | #define MCFQSPI_QMR 0x00 | |
44 | #define MCFQSPI_QMR_MSTR 0x8000 | |
45 | #define MCFQSPI_QMR_CPOL 0x0200 | |
46 | #define MCFQSPI_QMR_CPHA 0x0100 | |
47 | #define MCFQSPI_QDLYR 0x04 | |
48 | #define MCFQSPI_QDLYR_SPE 0x8000 | |
49 | #define MCFQSPI_QWR 0x08 | |
50 | #define MCFQSPI_QWR_HALT 0x8000 | |
51 | #define MCFQSPI_QWR_WREN 0x4000 | |
52 | #define MCFQSPI_QWR_CSIV 0x1000 | |
53 | #define MCFQSPI_QIR 0x0C | |
54 | #define MCFQSPI_QIR_WCEFB 0x8000 | |
55 | #define MCFQSPI_QIR_ABRTB 0x4000 | |
56 | #define MCFQSPI_QIR_ABRTL 0x1000 | |
57 | #define MCFQSPI_QIR_WCEFE 0x0800 | |
58 | #define MCFQSPI_QIR_ABRTE 0x0400 | |
59 | #define MCFQSPI_QIR_SPIFE 0x0100 | |
60 | #define MCFQSPI_QIR_WCEF 0x0008 | |
61 | #define MCFQSPI_QIR_ABRT 0x0004 | |
62 | #define MCFQSPI_QIR_SPIF 0x0001 | |
63 | #define MCFQSPI_QAR 0x010 | |
64 | #define MCFQSPI_QAR_TXBUF 0x00 | |
65 | #define MCFQSPI_QAR_RXBUF 0x10 | |
66 | #define MCFQSPI_QAR_CMDBUF 0x20 | |
67 | #define MCFQSPI_QDR 0x014 | |
68 | #define MCFQSPI_QCR 0x014 | |
69 | #define MCFQSPI_QCR_CONT 0x8000 | |
70 | #define MCFQSPI_QCR_BITSE 0x4000 | |
71 | #define MCFQSPI_QCR_DT 0x2000 | |
72 | ||
73 | struct mcfqspi { | |
74 | void __iomem *iobase; | |
75 | int irq; | |
76 | struct clk *clk; | |
77 | struct mcfqspi_cs_control *cs_control; | |
78 | ||
79 | wait_queue_head_t waitq; | |
34b8c661 SK |
80 | }; |
81 | ||
82 | static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) | |
83 | { | |
84 | writew(val, mcfqspi->iobase + MCFQSPI_QMR); | |
85 | } | |
86 | ||
87 | static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val) | |
88 | { | |
89 | writew(val, mcfqspi->iobase + MCFQSPI_QDLYR); | |
90 | } | |
91 | ||
92 | static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi) | |
93 | { | |
94 | return readw(mcfqspi->iobase + MCFQSPI_QDLYR); | |
95 | } | |
96 | ||
97 | static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val) | |
98 | { | |
99 | writew(val, mcfqspi->iobase + MCFQSPI_QWR); | |
100 | } | |
101 | ||
102 | static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val) | |
103 | { | |
104 | writew(val, mcfqspi->iobase + MCFQSPI_QIR); | |
105 | } | |
106 | ||
107 | static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val) | |
108 | { | |
109 | writew(val, mcfqspi->iobase + MCFQSPI_QAR); | |
110 | } | |
111 | ||
112 | static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val) | |
113 | { | |
114 | writew(val, mcfqspi->iobase + MCFQSPI_QDR); | |
115 | } | |
116 | ||
117 | static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi) | |
118 | { | |
119 | return readw(mcfqspi->iobase + MCFQSPI_QDR); | |
120 | } | |
121 | ||
122 | static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select, | |
123 | bool cs_high) | |
124 | { | |
125 | mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high); | |
126 | } | |
127 | ||
128 | static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select, | |
129 | bool cs_high) | |
130 | { | |
131 | mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high); | |
132 | } | |
133 | ||
134 | static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) | |
135 | { | |
136 | return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ? | |
137 | mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; | |
138 | } | |
139 | ||
140 | static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) | |
141 | { | |
142 | if (mcfqspi->cs_control && mcfqspi->cs_control->teardown) | |
143 | mcfqspi->cs_control->teardown(mcfqspi->cs_control); | |
144 | } | |
145 | ||
146 | static u8 mcfqspi_qmr_baud(u32 speed_hz) | |
147 | { | |
148 | return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u); | |
149 | } | |
150 | ||
151 | static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi) | |
152 | { | |
153 | return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE; | |
154 | } | |
155 | ||
156 | static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id) | |
157 | { | |
158 | struct mcfqspi *mcfqspi = dev_id; | |
159 | ||
160 | /* clear interrupt */ | |
161 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF); | |
162 | wake_up(&mcfqspi->waitq); | |
163 | ||
164 | return IRQ_HANDLED; | |
165 | } | |
166 | ||
167 | static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count, | |
168 | const u8 *txbuf, u8 *rxbuf) | |
169 | { | |
170 | unsigned i, n, offset = 0; | |
171 | ||
172 | n = min(count, 16u); | |
173 | ||
174 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
175 | for (i = 0; i < n; ++i) | |
176 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
177 | ||
178 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
179 | if (txbuf) | |
180 | for (i = 0; i < n; ++i) | |
181 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
182 | else | |
183 | for (i = 0; i < count; ++i) | |
184 | mcfqspi_wr_qdr(mcfqspi, 0); | |
185 | ||
186 | count -= n; | |
187 | if (count) { | |
188 | u16 qwr = 0xf08; | |
189 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
190 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
191 | ||
192 | do { | |
193 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
194 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
195 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
196 | if (rxbuf) { | |
197 | mcfqspi_wr_qar(mcfqspi, | |
198 | MCFQSPI_QAR_RXBUF + offset); | |
199 | for (i = 0; i < 8; ++i) | |
200 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
201 | } | |
202 | n = min(count, 8u); | |
203 | if (txbuf) { | |
204 | mcfqspi_wr_qar(mcfqspi, | |
205 | MCFQSPI_QAR_TXBUF + offset); | |
206 | for (i = 0; i < n; ++i) | |
207 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
208 | } | |
209 | qwr = (offset ? 0x808 : 0) + ((n - 1) << 8); | |
210 | offset ^= 8; | |
211 | count -= n; | |
212 | } while (count); | |
213 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
214 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
215 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
216 | if (rxbuf) { | |
217 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
218 | for (i = 0; i < 8; ++i) | |
219 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
220 | offset ^= 8; | |
221 | } | |
222 | } else { | |
223 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
224 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
225 | } | |
226 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
227 | if (rxbuf) { | |
228 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
229 | for (i = 0; i < n; ++i) | |
230 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
231 | } | |
232 | } | |
233 | ||
234 | static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, | |
235 | const u16 *txbuf, u16 *rxbuf) | |
236 | { | |
237 | unsigned i, n, offset = 0; | |
238 | ||
239 | n = min(count, 16u); | |
240 | ||
241 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
242 | for (i = 0; i < n; ++i) | |
243 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
244 | ||
245 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
246 | if (txbuf) | |
247 | for (i = 0; i < n; ++i) | |
248 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
249 | else | |
250 | for (i = 0; i < count; ++i) | |
251 | mcfqspi_wr_qdr(mcfqspi, 0); | |
252 | ||
253 | count -= n; | |
254 | if (count) { | |
255 | u16 qwr = 0xf08; | |
256 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
257 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
258 | ||
259 | do { | |
260 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
261 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
262 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
263 | if (rxbuf) { | |
264 | mcfqspi_wr_qar(mcfqspi, | |
265 | MCFQSPI_QAR_RXBUF + offset); | |
266 | for (i = 0; i < 8; ++i) | |
267 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
268 | } | |
269 | n = min(count, 8u); | |
270 | if (txbuf) { | |
271 | mcfqspi_wr_qar(mcfqspi, | |
272 | MCFQSPI_QAR_TXBUF + offset); | |
273 | for (i = 0; i < n; ++i) | |
274 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
275 | } | |
276 | qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8); | |
277 | offset ^= 8; | |
278 | count -= n; | |
279 | } while (count); | |
280 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
281 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
282 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
283 | if (rxbuf) { | |
284 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
285 | for (i = 0; i < 8; ++i) | |
286 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
287 | offset ^= 8; | |
288 | } | |
289 | } else { | |
290 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
291 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
292 | } | |
293 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
294 | if (rxbuf) { | |
295 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
296 | for (i = 0; i < n; ++i) | |
297 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
298 | } | |
299 | } | |
300 | ||
3531b717 | 301 | static void mcfqspi_set_cs(struct spi_device *spi, bool enable) |
34b8c661 | 302 | { |
3531b717 AL |
303 | struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master); |
304 | bool cs_high = spi->mode & SPI_CS_HIGH; | |
bc98d13f | 305 | |
3531b717 | 306 | if (enable) |
bc98d13f | 307 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); |
3531b717 AL |
308 | else |
309 | mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high); | |
310 | } | |
bc98d13f | 311 | |
3531b717 AL |
312 | static int mcfqspi_transfer_one(struct spi_master *master, |
313 | struct spi_device *spi, | |
314 | struct spi_transfer *t) | |
315 | { | |
316 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
317 | u16 qmr = MCFQSPI_QMR_MSTR; | |
318 | ||
319 | qmr |= t->bits_per_word << 10; | |
320 | if (spi->mode & SPI_CPHA) | |
321 | qmr |= MCFQSPI_QMR_CPHA; | |
322 | if (spi->mode & SPI_CPOL) | |
323 | qmr |= MCFQSPI_QMR_CPOL; | |
324 | if (t->speed_hz) | |
325 | qmr |= mcfqspi_qmr_baud(t->speed_hz); | |
326 | else | |
327 | qmr |= mcfqspi_qmr_baud(spi->max_speed_hz); | |
328 | mcfqspi_wr_qmr(mcfqspi, qmr); | |
bc98d13f | 329 | |
3531b717 AL |
330 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); |
331 | if (t->bits_per_word == 8) | |
332 | mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf); | |
333 | else | |
334 | mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf, | |
335 | t->rx_buf); | |
336 | mcfqspi_wr_qir(mcfqspi, 0); | |
bc98d13f | 337 | |
3531b717 | 338 | return 0; |
34b8c661 SK |
339 | } |
340 | ||
34b8c661 SK |
341 | static int mcfqspi_setup(struct spi_device *spi) |
342 | { | |
34b8c661 SK |
343 | if (spi->chip_select >= spi->master->num_chipselect) { |
344 | dev_dbg(&spi->dev, "%d chip select is out of range\n", | |
345 | spi->chip_select); | |
346 | return -EINVAL; | |
347 | } | |
348 | ||
349 | mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), | |
350 | spi->chip_select, spi->mode & SPI_CS_HIGH); | |
351 | ||
352 | dev_dbg(&spi->dev, | |
353 | "bits per word %d, chip select %d, speed %d KHz\n", | |
354 | spi->bits_per_word, spi->chip_select, | |
355 | (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz)) | |
356 | / 1000); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
fd4a319b | 361 | static int mcfqspi_probe(struct platform_device *pdev) |
34b8c661 SK |
362 | { |
363 | struct spi_master *master; | |
364 | struct mcfqspi *mcfqspi; | |
365 | struct resource *res; | |
366 | struct mcfqspi_platform_data *pdata; | |
367 | int status; | |
368 | ||
8074cf06 | 369 | pdata = dev_get_platdata(&pdev->dev); |
4a577f52 WY |
370 | if (!pdata) { |
371 | dev_dbg(&pdev->dev, "platform data is missing\n"); | |
372 | return -ENOENT; | |
373 | } | |
374 | ||
34b8c661 SK |
375 | master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); |
376 | if (master == NULL) { | |
377 | dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); | |
378 | return -ENOMEM; | |
379 | } | |
380 | ||
381 | mcfqspi = spi_master_get_devdata(master); | |
382 | ||
383 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9a3ced19 JH |
384 | mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res); |
385 | if (IS_ERR(mcfqspi->iobase)) { | |
386 | status = PTR_ERR(mcfqspi->iobase); | |
34b8c661 SK |
387 | goto fail0; |
388 | } | |
389 | ||
34b8c661 SK |
390 | mcfqspi->irq = platform_get_irq(pdev, 0); |
391 | if (mcfqspi->irq < 0) { | |
392 | dev_dbg(&pdev->dev, "platform_get_irq failed\n"); | |
393 | status = -ENXIO; | |
9a3ced19 | 394 | goto fail0; |
34b8c661 SK |
395 | } |
396 | ||
9a3ced19 JH |
397 | status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler, |
398 | 0, pdev->name, mcfqspi); | |
34b8c661 SK |
399 | if (status) { |
400 | dev_dbg(&pdev->dev, "request_irq failed\n"); | |
9a3ced19 | 401 | goto fail0; |
34b8c661 SK |
402 | } |
403 | ||
9a3ced19 | 404 | mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk"); |
34b8c661 SK |
405 | if (IS_ERR(mcfqspi->clk)) { |
406 | dev_dbg(&pdev->dev, "clk_get failed\n"); | |
407 | status = PTR_ERR(mcfqspi->clk); | |
9a3ced19 | 408 | goto fail0; |
34b8c661 SK |
409 | } |
410 | clk_enable(mcfqspi->clk); | |
411 | ||
34b8c661 SK |
412 | master->bus_num = pdata->bus_num; |
413 | master->num_chipselect = pdata->num_chipselect; | |
414 | ||
415 | mcfqspi->cs_control = pdata->cs_control; | |
416 | status = mcfqspi_cs_setup(mcfqspi); | |
417 | if (status) { | |
418 | dev_dbg(&pdev->dev, "error initializing cs_control\n"); | |
9a3ced19 | 419 | goto fail1; |
34b8c661 SK |
420 | } |
421 | ||
bc98d13f | 422 | init_waitqueue_head(&mcfqspi->waitq); |
bc98d13f | 423 | |
34b8c661 | 424 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; |
24778be2 | 425 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); |
34b8c661 | 426 | master->setup = mcfqspi_setup; |
3531b717 AL |
427 | master->set_cs = mcfqspi_set_cs; |
428 | master->transfer_one = mcfqspi_transfer_one; | |
3f36e80a | 429 | master->auto_runtime_pm = true; |
34b8c661 SK |
430 | |
431 | platform_set_drvdata(pdev, master); | |
432 | ||
9a3ced19 | 433 | status = devm_spi_register_master(&pdev->dev, master); |
34b8c661 SK |
434 | if (status) { |
435 | dev_dbg(&pdev->dev, "spi_register_master failed\n"); | |
9a3ced19 | 436 | goto fail2; |
34b8c661 | 437 | } |
8bd31345 | 438 | pm_runtime_enable(&pdev->dev); |
bc98d13f | 439 | |
34b8c661 SK |
440 | dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); |
441 | ||
442 | return 0; | |
443 | ||
34b8c661 | 444 | fail2: |
9a3ced19 | 445 | mcfqspi_cs_teardown(mcfqspi); |
34b8c661 | 446 | fail1: |
9a3ced19 | 447 | clk_disable(mcfqspi->clk); |
34b8c661 SK |
448 | fail0: |
449 | spi_master_put(master); | |
450 | ||
451 | dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n"); | |
452 | ||
453 | return status; | |
454 | } | |
455 | ||
fd4a319b | 456 | static int mcfqspi_remove(struct platform_device *pdev) |
34b8c661 SK |
457 | { |
458 | struct spi_master *master = platform_get_drvdata(pdev); | |
459 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
34b8c661 | 460 | |
8bd31345 | 461 | pm_runtime_disable(&pdev->dev); |
34b8c661 SK |
462 | /* disable the hardware (set the baud rate to 0) */ |
463 | mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); | |
464 | ||
34b8c661 | 465 | mcfqspi_cs_teardown(mcfqspi); |
34b8c661 | 466 | clk_disable(mcfqspi->clk); |
34b8c661 SK |
467 | |
468 | return 0; | |
469 | } | |
470 | ||
bc98d13f | 471 | #ifdef CONFIG_PM_SLEEP |
34b8c661 SK |
472 | static int mcfqspi_suspend(struct device *dev) |
473 | { | |
af361079 | 474 | struct spi_master *master = dev_get_drvdata(dev); |
bc98d13f | 475 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); |
2aa237f4 | 476 | int ret; |
bc98d13f | 477 | |
2aa237f4 AL |
478 | ret = spi_master_suspend(master); |
479 | if (ret) | |
480 | return ret; | |
34b8c661 SK |
481 | |
482 | clk_disable(mcfqspi->clk); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int mcfqspi_resume(struct device *dev) | |
488 | { | |
af361079 | 489 | struct spi_master *master = dev_get_drvdata(dev); |
bc98d13f SK |
490 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); |
491 | ||
34b8c661 SK |
492 | clk_enable(mcfqspi->clk); |
493 | ||
2aa237f4 | 494 | return spi_master_resume(master); |
34b8c661 | 495 | } |
bc98d13f | 496 | #endif |
34b8c661 | 497 | |
bc98d13f SK |
498 | #ifdef CONFIG_PM_RUNTIME |
499 | static int mcfqspi_runtime_suspend(struct device *dev) | |
500 | { | |
a1216394 | 501 | struct mcfqspi *mcfqspi = dev_get_drvdata(dev); |
34b8c661 | 502 | |
bc98d13f SK |
503 | clk_disable(mcfqspi->clk); |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | static int mcfqspi_runtime_resume(struct device *dev) | |
509 | { | |
a1216394 | 510 | struct mcfqspi *mcfqspi = dev_get_drvdata(dev); |
bc98d13f SK |
511 | |
512 | clk_enable(mcfqspi->clk); | |
513 | ||
514 | return 0; | |
515 | } | |
34b8c661 SK |
516 | #endif |
517 | ||
bc98d13f SK |
518 | static const struct dev_pm_ops mcfqspi_pm = { |
519 | SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume) | |
520 | SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume, | |
521 | NULL) | |
522 | }; | |
523 | ||
34b8c661 SK |
524 | static struct platform_driver mcfqspi_driver = { |
525 | .driver.name = DRIVER_NAME, | |
526 | .driver.owner = THIS_MODULE, | |
bc98d13f | 527 | .driver.pm = &mcfqspi_pm, |
940ab889 | 528 | .probe = mcfqspi_probe, |
fd4a319b | 529 | .remove = mcfqspi_remove, |
34b8c661 | 530 | }; |
940ab889 | 531 | module_platform_driver(mcfqspi_driver); |
34b8c661 SK |
532 | |
533 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); | |
534 | MODULE_DESCRIPTION("Coldfire QSPI Controller Driver"); | |
535 | MODULE_LICENSE("GPL"); | |
536 | MODULE_ALIAS("platform:" DRIVER_NAME); |