[deliverable/linux.git] / drivers / spi / spi-dw-mid.c

/*
 * Special handling for DW core on Intel MID platform
 *
 * Copyright (c) 2009, 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/types.h>

#include "spi-dw.h"

#ifdef CONFIG_SPI_DW_MID_DMA
#include <linux/intel_mid_dma.h>
#include <linux/pci.h>

#define RX_BUSY		0
#define TX_BUSY		1

struct mid_dma {
	struct intel_mid_dma_slave	dmas_tx;
	struct intel_mid_dma_slave	dmas_rx;
};

static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
{
	struct dw_spi *dws = param;

	return dws->dma_dev == chan->device->dev;
}

static int mid_spi_dma_init(struct dw_spi *dws)
{
	struct mid_dma *dw_dma = dws->dma_priv;
	struct pci_dev *dma_dev;
	struct intel_mid_dma_slave *rxs, *txs;
	dma_cap_mask_t mask;

	/*
	 * Get pci device for DMA controller, currently it could only
	 * be the DMA controller of Medfield
	 */
	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	if (!dma_dev)
		return -ENODEV;

	dws->dma_dev = &dma_dev->dev;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* 1. Init rx channel */
	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->rxchan)
		goto err_exit;
	rxs = &dw_dma->dmas_rx;
	rxs->hs_mode = LNW_DMA_HW_HS;
	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	dws->rxchan->private = rxs;

	/* 2. Init tx channel */
	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	if (!dws->txchan)
		goto free_rxchan;
	txs = &dw_dma->dmas_tx;
	txs->hs_mode = LNW_DMA_HW_HS;
	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	dws->txchan->private = txs;

	dws->dma_inited = 1;
	return 0;

free_rxchan:
	dma_release_channel(dws->rxchan);
err_exit:
	return -EBUSY;
}

static void mid_spi_dma_exit(struct dw_spi *dws)
{
	if (!dws->dma_inited)
		return;

	dmaengine_terminate_all(dws->txchan);
	dma_release_channel(dws->txchan);

	dmaengine_terminate_all(dws->rxchan);
	dma_release_channel(dws->rxchan);
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_tx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(TX_BUSY, &dws->dma_chan_busy);
	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
		return;
	dw_spi_xfer_done(dws);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
{
	struct dma_slave_config txconf;
	struct dma_async_tx_descriptor *txdesc;

	if (!dws->tx_dma)
		return NULL;

	txconf.direction = DMA_MEM_TO_DEV;
	txconf.dst_addr = dws->dma_addr;
	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	txconf.dst_addr_width = dws->dma_width;
	txconf.device_fc = false;

	dmaengine_slave_config(dws->txchan, &txconf);

	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	dws->tx_sgl.dma_address = dws->tx_dma;
	dws->tx_sgl.length = dws->len;

	txdesc = dmaengine_prep_slave_sg(dws->txchan,
				&dws->tx_sgl,
				1,
				DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!txdesc)
		return NULL;

	txdesc->callback = dw_spi_dma_tx_done;
	txdesc->callback_param = dws;

	return txdesc;
}

/*
 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 * channel will clear a corresponding bit.
 */
static void dw_spi_dma_rx_done(void *arg)
{
	struct dw_spi *dws = arg;

	clear_bit(RX_BUSY, &dws->dma_chan_busy);
	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
		return;
	dw_spi_xfer_done(dws);
}

static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
{
	struct dma_slave_config rxconf;
	struct dma_async_tx_descriptor *rxdesc;

	if (!dws->rx_dma)
		return NULL;

	rxconf.direction = DMA_DEV_TO_MEM;
	rxconf.src_addr = dws->dma_addr;
	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	rxconf.src_addr_width = dws->dma_width;
	rxconf.device_fc = false;

	dmaengine_slave_config(dws->rxchan, &rxconf);

	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	dws->rx_sgl.dma_address = dws->rx_dma;
	dws->rx_sgl.length = dws->len;

	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
				&dws->rx_sgl,
				1,
				DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!rxdesc)
		return NULL;

	rxdesc->callback = dw_spi_dma_rx_done;
	rxdesc->callback_param = dws;

	return rxdesc;
}

static void dw_spi_dma_setup(struct dw_spi *dws)
{
	u16 dma_ctrl = 0;

	spi_enable_chip(dws, 0);

	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	dw_writew(dws, DW_SPI_DMATDLR, 0x10);

	if (dws->tx_dma)
		dma_ctrl |= SPI_DMA_TDMAE;
	if (dws->rx_dma)
		dma_ctrl |= SPI_DMA_RDMAE;
	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);

	spi_enable_chip(dws, 1);
}

static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
{
	struct dma_async_tx_descriptor *txdesc, *rxdesc;

	/* 1. setup DMA related registers */
	if (cs_change)
		dw_spi_dma_setup(dws);

	/* 2. Prepare the TX dma transfer */
	txdesc = dw_spi_dma_prepare_tx(dws);

	/* 3. Prepare the RX dma transfer */
	rxdesc = dw_spi_dma_prepare_rx(dws);

	/* rx must be started before tx due to spi instinct */
	if (rxdesc) {
		set_bit(RX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(rxdesc);
		dma_async_issue_pending(dws->rxchan);
	}

	if (txdesc) {
		set_bit(TX_BUSY, &dws->dma_chan_busy);
		dmaengine_submit(txdesc);
		dma_async_issue_pending(dws->txchan);
	}

	return 0;
}

static struct dw_spi_dma_ops mid_dma_ops = {
	.dma_init	= mid_spi_dma_init,
	.dma_exit	= mid_spi_dma_exit,
	.dma_transfer	= mid_spi_dma_transfer,
};
#endif

/* Some specific info for SPI0 controller on Intel MID */

/* HW info for MRST Clk Control Unit, 32b reg per controller */
#define MRST_SPI_CLK_BASE	100000000	/* 100m */
#define MRST_CLK_SPI_REG	0xff11d86c
#define CLK_SPI_BDIV_OFFSET	0
#define CLK_SPI_BDIV_MASK	0x00000007
#define CLK_SPI_CDIV_OFFSET	9
#define CLK_SPI_CDIV_MASK	0x00000e00
#define CLK_SPI_DISABLE_OFFSET	8

int dw_spi_mid_init(struct dw_spi *dws)
{
	void __iomem *clk_reg;
	u32 clk_cdiv;

	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
	if (!clk_reg)
		return -ENOMEM;

	/* Get SPI controller operating freq info */
	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	clk_cdiv &= CLK_SPI_CDIV_MASK;
	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);

	iounmap(clk_reg);

#ifdef CONFIG_SPI_DW_MID_DMA
	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	if (!dws->dma_priv)
		return -ENOMEM;
	dws->dma_ops = &mid_dma_ops;
#endif
	return 0;
}
Commit	Line	Data
7063c0d9	1	/*
ca632f55	2	* Special handling for DW core on Intel MID platform
7063c0d9	3	*
197e96b4	4	* Copyright (c) 2009, 2014 Intel Corporation.
7063c0d9 FT	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
7063c0d9 FT	14	*/
	15
	16	#include <linux/dma-mapping.h>
	17	#include <linux/dmaengine.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/slab.h>
	20	#include <linux/spi/spi.h>
258aea76	21	#include <linux/types.h>
568a60ed	22
ca632f55	23	#include "spi-dw.h"
7063c0d9 FT	24
	25	#ifdef CONFIG_SPI_DW_MID_DMA
	26	#include <linux/intel_mid_dma.h>
	27	#include <linux/pci.h>
	28
30c8eb52 AS	29	#define RX_BUSY 0
	30	#define TX_BUSY 1
	31
7063c0d9 FT	32	struct mid_dma {
	33	struct intel_mid_dma_slave dmas_tx;
	34	struct intel_mid_dma_slave dmas_rx;
	35	};
	36
	37	static bool mid_spi_dma_chan_filter(struct dma_chan chan, void param)
	38	{
	39	struct dw_spi *dws = param;
	40
b89e9c87	41	return dws->dma_dev == chan->device->dev;
7063c0d9 FT	42	}
	43
	44	static int mid_spi_dma_init(struct dw_spi *dws)
	45	{
	46	struct mid_dma *dw_dma = dws->dma_priv;
b89e9c87	47	struct pci_dev *dma_dev;
7063c0d9 FT	48	struct intel_mid_dma_slave rxs, txs;
	49	dma_cap_mask_t mask;
	50
	51	/*
	52	* Get pci device for DMA controller, currently it could only
ea092455	53	* be the DMA controller of Medfield
7063c0d9	54	*/
b89e9c87 AS	55	dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
	56	if (!dma_dev)
	57	return -ENODEV;
	58
	59	dws->dma_dev = &dma_dev->dev;
7063c0d9 FT	60
	61	dma_cap_zero(mask);
	62	dma_cap_set(DMA_SLAVE, mask);
	63
	64	/* 1. Init rx channel */
	65	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	66	if (!dws->rxchan)
	67	goto err_exit;
	68	rxs = &dw_dma->dmas_rx;
	69	rxs->hs_mode = LNW_DMA_HW_HS;
	70	rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
	71	dws->rxchan->private = rxs;
	72
	73	/* 2. Init tx channel */
	74	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
	75	if (!dws->txchan)
	76	goto free_rxchan;
	77	txs = &dw_dma->dmas_tx;
	78	txs->hs_mode = LNW_DMA_HW_HS;
	79	txs->cfg_mode = LNW_DMA_MEM_TO_PER;
	80	dws->txchan->private = txs;
	81
	82	dws->dma_inited = 1;
	83	return 0;
	84
	85	free_rxchan:
	86	dma_release_channel(dws->rxchan);
	87	err_exit:
b89e9c87	88	return -EBUSY;
7063c0d9 FT	89	}
	90
	91	static void mid_spi_dma_exit(struct dw_spi *dws)
	92	{
fb57862e AS	93	if (!dws->dma_inited)
fb57862e AS	94	return;
8e45ef68 AS	95
8e45ef68 AS	96	dmaengine_terminate_all(dws->txchan);
7063c0d9	97	dma_release_channel(dws->txchan);
8e45ef68 AS	98
8e45ef68 AS	99	dmaengine_terminate_all(dws->rxchan);
7063c0d9 FT	100	dma_release_channel(dws->rxchan);
	101	}
	102
	103	/*
30c8eb52 AS	104	* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
30c8eb52 AS	105	* channel will clear a corresponding bit.
7063c0d9	106	*/
30c8eb52	107	static void dw_spi_dma_tx_done(void *arg)
7063c0d9 FT	108	{
	109	struct dw_spi *dws = arg;
	110
854d2f24 AS	111	clear_bit(TX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	112	if (test_bit(RX_BUSY, &dws->dma_chan_busy))
7063c0d9 FT	113	return;
	114	dw_spi_xfer_done(dws);
	115	}
	116
a5c2db96	117	static struct dma_async_tx_descriptor dw_spi_dma_prepare_tx(struct dw_spi dws)
7063c0d9	118	{
a5c2db96 AS	119	struct dma_slave_config txconf;
a5c2db96 AS	120	struct dma_async_tx_descriptor *txdesc;
7063c0d9	121
30c8eb52 AS	122	if (!dws->tx_dma)
	123	return NULL;
	124
a485df4b	125	txconf.direction = DMA_MEM_TO_DEV;
7063c0d9 FT	126	txconf.dst_addr = dws->dma_addr;
	127	txconf.dst_maxburst = LNW_DMA_MSIZE_16;
	128	txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	129	txconf.dst_addr_width = dws->dma_width;
258aea76	130	txconf.device_fc = false;
7063c0d9	131
2a285299	132	dmaengine_slave_config(dws->txchan, &txconf);
7063c0d9 FT	133
	134	memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
	135	dws->tx_sgl.dma_address = dws->tx_dma;
	136	dws->tx_sgl.length = dws->len;
	137
2a285299	138	txdesc = dmaengine_prep_slave_sg(dws->txchan,
7063c0d9 FT	139	&dws->tx_sgl,
7063c0d9 FT	140	1,
a485df4b	141	DMA_MEM_TO_DEV,
f7477c2b	142	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	143	if (!txdesc)
	144	return NULL;
	145
30c8eb52	146	txdesc->callback = dw_spi_dma_tx_done;
7063c0d9 FT	147	txdesc->callback_param = dws;
7063c0d9 FT	148
a5c2db96 AS	149	return txdesc;
	150	}
	151
30c8eb52 AS	152	/*
	153	* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
	154	* channel will clear a corresponding bit.
	155	*/
	156	static void dw_spi_dma_rx_done(void *arg)
	157	{
	158	struct dw_spi *dws = arg;
	159
854d2f24 AS	160	clear_bit(RX_BUSY, &dws->dma_chan_busy);
854d2f24 AS	161	if (test_bit(TX_BUSY, &dws->dma_chan_busy))
30c8eb52 AS	162	return;
	163	dw_spi_xfer_done(dws);
	164	}
	165
a5c2db96 AS	166	static struct dma_async_tx_descriptor dw_spi_dma_prepare_rx(struct dw_spi dws)
	167	{
	168	struct dma_slave_config rxconf;
	169	struct dma_async_tx_descriptor *rxdesc;
	170
30c8eb52 AS	171	if (!dws->rx_dma)
	172	return NULL;
	173
a485df4b	174	rxconf.direction = DMA_DEV_TO_MEM;
7063c0d9 FT	175	rxconf.src_addr = dws->dma_addr;
	176	rxconf.src_maxburst = LNW_DMA_MSIZE_16;
	177	rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
b41583e7	178	rxconf.src_addr_width = dws->dma_width;
258aea76	179	rxconf.device_fc = false;
7063c0d9	180
2a285299	181	dmaengine_slave_config(dws->rxchan, &rxconf);
7063c0d9 FT	182
	183	memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
	184	dws->rx_sgl.dma_address = dws->rx_dma;
	185	dws->rx_sgl.length = dws->len;
	186
2a285299	187	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
7063c0d9 FT	188	&dws->rx_sgl,
7063c0d9 FT	189	1,
a485df4b	190	DMA_DEV_TO_MEM,
f7477c2b	191	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
c9dafb27 AS	192	if (!rxdesc)
	193	return NULL;
	194
30c8eb52	195	rxdesc->callback = dw_spi_dma_rx_done;
7063c0d9 FT	196	rxdesc->callback_param = dws;
7063c0d9 FT	197
a5c2db96 AS	198	return rxdesc;
	199	}
	200
	201	static void dw_spi_dma_setup(struct dw_spi *dws)
	202	{
	203	u16 dma_ctrl = 0;
	204
	205	spi_enable_chip(dws, 0);
	206
	207	dw_writew(dws, DW_SPI_DMARDLR, 0xf);
	208	dw_writew(dws, DW_SPI_DMATDLR, 0x10);
	209
	210	if (dws->tx_dma)
	211	dma_ctrl \|= SPI_DMA_TDMAE;
	212	if (dws->rx_dma)
	213	dma_ctrl \|= SPI_DMA_RDMAE;
	214	dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
	215
	216	spi_enable_chip(dws, 1);
	217	}
	218
	219	static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
	220	{
	221	struct dma_async_tx_descriptor txdesc, rxdesc;
	222
	223	/* 1. setup DMA related registers */
	224	if (cs_change)
	225	dw_spi_dma_setup(dws);
	226
a5c2db96 AS	227	/* 2. Prepare the TX dma transfer */
	228	txdesc = dw_spi_dma_prepare_tx(dws);
	229
	230	/* 3. Prepare the RX dma transfer */
	231	rxdesc = dw_spi_dma_prepare_rx(dws);
	232
7063c0d9	233	/* rx must be started before tx due to spi instinct */
30c8eb52 AS	234	if (rxdesc) {
	235	set_bit(RX_BUSY, &dws->dma_chan_busy);
	236	dmaengine_submit(rxdesc);
	237	dma_async_issue_pending(dws->rxchan);
	238	}
	239
	240	if (txdesc) {
	241	set_bit(TX_BUSY, &dws->dma_chan_busy);
	242	dmaengine_submit(txdesc);
	243	dma_async_issue_pending(dws->txchan);
	244	}
f7477c2b	245
7063c0d9 FT	246	return 0;
	247	}
	248
	249	static struct dw_spi_dma_ops mid_dma_ops = {
	250	.dma_init = mid_spi_dma_init,
	251	.dma_exit = mid_spi_dma_exit,
	252	.dma_transfer = mid_spi_dma_transfer,
	253	};
	254	#endif
	255
ea092455	256	/* Some specific info for SPI0 controller on Intel MID */
7063c0d9	257
d9c14743	258	/* HW info for MRST Clk Control Unit, 32b reg per controller */
7063c0d9	259	#define MRST_SPI_CLK_BASE 100000000 /* 100m */
d9c14743	260	#define MRST_CLK_SPI_REG 0xff11d86c
7063c0d9 FT	261	#define CLK_SPI_BDIV_OFFSET 0
	262	#define CLK_SPI_BDIV_MASK 0x00000007
	263	#define CLK_SPI_CDIV_OFFSET 9
	264	#define CLK_SPI_CDIV_MASK 0x00000e00
	265	#define CLK_SPI_DISABLE_OFFSET 8
	266
	267	int dw_spi_mid_init(struct dw_spi *dws)
	268	{
7eb187b3 HS	269	void __iomem *clk_reg;
7eb187b3 HS	270	u32 clk_cdiv;
7063c0d9	271
d9c14743	272	clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
7063c0d9 FT	273	if (!clk_reg)
	274	return -ENOMEM;
	275
d9c14743 AS	276	/* Get SPI controller operating freq info */
	277	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
	278	clk_cdiv &= CLK_SPI_CDIV_MASK;
	279	clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
7063c0d9	280	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
d9c14743	281
7063c0d9 FT	282	iounmap(clk_reg);
7063c0d9 FT	283
7063c0d9 FT	284	#ifdef CONFIG_SPI_DW_MID_DMA
	285	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
	286	if (!dws->dma_priv)
	287	return -ENOMEM;
	288	dws->dma_ops = &mid_dma_ops;
	289	#endif
	290	return 0;
	291	}