Commit | Line | Data |
---|---|---|
e24c7452 | 1 | /* |
ca632f55 | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
3 | * |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
e24c7452 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/interrupt.h> | |
d7614de4 | 18 | #include <linux/module.h> |
e24c7452 FT |
19 | #include <linux/highmem.h> |
20 | #include <linux/delay.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e24c7452 | 22 | #include <linux/spi/spi.h> |
d9c73bb8 | 23 | #include <linux/gpio.h> |
e24c7452 | 24 | |
ca632f55 | 25 | #include "spi-dw.h" |
568a60ed | 26 | |
e24c7452 FT |
27 | #ifdef CONFIG_DEBUG_FS |
28 | #include <linux/debugfs.h> | |
29 | #endif | |
30 | ||
e24c7452 FT |
31 | /* Slave spi_dev related */ |
32 | struct chip_data { | |
33 | u16 cr0; | |
34 | u8 cs; /* chip select pin */ | |
35 | u8 n_bytes; /* current is a 1/2/4 byte op */ | |
36 | u8 tmode; /* TR/TO/RO/EEPROM */ | |
37 | u8 type; /* SPI/SSP/MicroWire */ | |
38 | ||
39 | u8 poll_mode; /* 1 means use poll mode */ | |
40 | ||
41 | u32 dma_width; | |
42 | u32 rx_threshold; | |
43 | u32 tx_threshold; | |
44 | u8 enable_dma; | |
45 | u8 bits_per_word; | |
46 | u16 clk_div; /* baud rate divider */ | |
47 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
48 | void (*cs_control)(u32 command); |
49 | }; | |
50 | ||
51 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 52 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
53 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
54 | size_t count, loff_t *ppos) | |
e24c7452 | 55 | { |
53288fe9 | 56 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
57 | char *buf; |
58 | u32 len = 0; | |
59 | ssize_t ret; | |
60 | ||
e24c7452 FT |
61 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
62 | if (!buf) | |
63 | return 0; | |
64 | ||
65 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
53288fe9 | 66 | "%s registers:\n", dev_name(&dws->master->dev)); |
e24c7452 FT |
67 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
68 | "=================================\n"); | |
69 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
7eb187b3 | 70 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
e24c7452 | 71 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 72 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
e24c7452 | 73 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 74 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
e24c7452 | 75 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 76 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
e24c7452 | 77 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 78 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
e24c7452 | 79 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 80 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
e24c7452 | 81 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 82 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
e24c7452 | 83 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 84 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
e24c7452 | 85 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 86 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
e24c7452 | 87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 88 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
e24c7452 | 89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 90 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
e24c7452 | 91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 92 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
e24c7452 | 93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 94 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
e24c7452 | 95 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 96 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
e24c7452 | 97 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 98 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
e24c7452 FT |
99 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
100 | "=================================\n"); | |
101 | ||
53288fe9 | 102 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
103 | kfree(buf); |
104 | return ret; | |
105 | } | |
106 | ||
53288fe9 | 107 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 108 | .owner = THIS_MODULE, |
234e3405 | 109 | .open = simple_open, |
53288fe9 | 110 | .read = dw_spi_show_regs, |
6038f373 | 111 | .llseek = default_llseek, |
e24c7452 FT |
112 | }; |
113 | ||
53288fe9 | 114 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 115 | { |
53288fe9 | 116 | dws->debugfs = debugfs_create_dir("dw_spi", NULL); |
e24c7452 FT |
117 | if (!dws->debugfs) |
118 | return -ENOMEM; | |
119 | ||
120 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 121 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
122 | return 0; |
123 | } | |
124 | ||
53288fe9 | 125 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 126 | { |
fadcace7 | 127 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
128 | } |
129 | ||
130 | #else | |
53288fe9 | 131 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 132 | { |
20a588fc | 133 | return 0; |
e24c7452 FT |
134 | } |
135 | ||
53288fe9 | 136 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
137 | { |
138 | } | |
139 | #endif /* CONFIG_DEBUG_FS */ | |
140 | ||
c22c62db AS |
141 | static void dw_spi_set_cs(struct spi_device *spi, bool enable) |
142 | { | |
143 | struct dw_spi *dws = spi_master_get_devdata(spi->master); | |
144 | struct chip_data *chip = spi_get_ctldata(spi); | |
145 | ||
146 | /* Chip select logic is inverted from spi_set_cs() */ | |
207cda93 | 147 | if (chip && chip->cs_control) |
c22c62db AS |
148 | chip->cs_control(!enable); |
149 | ||
150 | if (!enable) | |
151 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); | |
152 | } | |
153 | ||
2ff271bf AD |
154 | /* Return the max entries we can fill into tx fifo */ |
155 | static inline u32 tx_max(struct dw_spi *dws) | |
156 | { | |
157 | u32 tx_left, tx_room, rxtx_gap; | |
158 | ||
159 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
dd114443 | 160 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
2ff271bf AD |
161 | |
162 | /* | |
163 | * Another concern is about the tx/rx mismatch, we | |
164 | * though to use (dws->fifo_len - rxflr - txflr) as | |
165 | * one maximum value for tx, but it doesn't cover the | |
166 | * data which is out of tx/rx fifo and inside the | |
167 | * shift registers. So a control from sw point of | |
168 | * view is taken. | |
169 | */ | |
170 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
171 | / dws->n_bytes; | |
172 | ||
173 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
174 | } | |
175 | ||
176 | /* Return the max entries we should read out of rx fifo */ | |
177 | static inline u32 rx_max(struct dw_spi *dws) | |
178 | { | |
179 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
180 | ||
dd114443 | 181 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
182 | } |
183 | ||
3b8a4dd3 | 184 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 185 | { |
2ff271bf | 186 | u32 max = tx_max(dws); |
de6efe0a | 187 | u16 txw = 0; |
e24c7452 | 188 | |
2ff271bf AD |
189 | while (max--) { |
190 | /* Set the tx word if the transfer's original "tx" is not null */ | |
191 | if (dws->tx_end - dws->len) { | |
192 | if (dws->n_bytes == 1) | |
193 | txw = *(u8 *)(dws->tx); | |
194 | else | |
195 | txw = *(u16 *)(dws->tx); | |
196 | } | |
dd114443 | 197 | dw_writel(dws, DW_SPI_DR, txw); |
2ff271bf | 198 | dws->tx += dws->n_bytes; |
e24c7452 | 199 | } |
e24c7452 FT |
200 | } |
201 | ||
3b8a4dd3 | 202 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 203 | { |
2ff271bf | 204 | u32 max = rx_max(dws); |
de6efe0a | 205 | u16 rxw; |
e24c7452 | 206 | |
2ff271bf | 207 | while (max--) { |
dd114443 | 208 | rxw = dw_readl(dws, DW_SPI_DR); |
de6efe0a FT |
209 | /* Care rx only if the transfer's original "rx" is not null */ |
210 | if (dws->rx_end - dws->len) { | |
211 | if (dws->n_bytes == 1) | |
212 | *(u8 *)(dws->rx) = rxw; | |
213 | else | |
214 | *(u16 *)(dws->rx) = rxw; | |
215 | } | |
216 | dws->rx += dws->n_bytes; | |
e24c7452 | 217 | } |
e24c7452 FT |
218 | } |
219 | ||
e24c7452 FT |
220 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
221 | { | |
45746e82 | 222 | spi_reset_chip(dws); |
e24c7452 FT |
223 | |
224 | dev_err(&dws->master->dev, "%s\n", msg); | |
c22c62db AS |
225 | dws->master->cur_msg->status = -EIO; |
226 | spi_finalize_current_transfer(dws->master); | |
e24c7452 FT |
227 | } |
228 | ||
e24c7452 FT |
229 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
230 | { | |
dd114443 | 231 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
e24c7452 | 232 | |
e24c7452 FT |
233 | /* Error handling */ |
234 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
dd114443 | 235 | dw_readl(dws, DW_SPI_ICR); |
3b8a4dd3 | 236 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
237 | return IRQ_HANDLED; |
238 | } | |
239 | ||
3b8a4dd3 AD |
240 | dw_reader(dws); |
241 | if (dws->rx_end == dws->rx) { | |
242 | spi_mask_intr(dws, SPI_INT_TXEI); | |
c22c62db | 243 | spi_finalize_current_transfer(dws->master); |
3b8a4dd3 AD |
244 | return IRQ_HANDLED; |
245 | } | |
552e4509 FT |
246 | if (irq_status & SPI_INT_TXEI) { |
247 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
248 | dw_writer(dws); |
249 | /* Enable TX irq always, it will be disabled when RX finished */ | |
250 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
251 | } |
252 | ||
e24c7452 FT |
253 | return IRQ_HANDLED; |
254 | } | |
255 | ||
256 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
257 | { | |
c22c62db AS |
258 | struct spi_master *master = dev_id; |
259 | struct dw_spi *dws = spi_master_get_devdata(master); | |
dd114443 | 260 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 261 | |
cbcc062a YW |
262 | if (!irq_status) |
263 | return IRQ_NONE; | |
e24c7452 | 264 | |
c22c62db | 265 | if (!master->cur_msg) { |
e24c7452 | 266 | spi_mask_intr(dws, SPI_INT_TXEI); |
e24c7452 FT |
267 | return IRQ_HANDLED; |
268 | } | |
269 | ||
270 | return dws->transfer_handler(dws); | |
271 | } | |
272 | ||
273 | /* Must be called inside pump_transfers() */ | |
c22c62db | 274 | static int poll_transfer(struct dw_spi *dws) |
e24c7452 | 275 | { |
2ff271bf AD |
276 | do { |
277 | dw_writer(dws); | |
de6efe0a | 278 | dw_reader(dws); |
2ff271bf AD |
279 | cpu_relax(); |
280 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 281 | |
c22c62db | 282 | return 0; |
e24c7452 FT |
283 | } |
284 | ||
c22c62db AS |
285 | static int dw_spi_transfer_one(struct spi_master *master, |
286 | struct spi_device *spi, struct spi_transfer *transfer) | |
e24c7452 | 287 | { |
c22c62db AS |
288 | struct dw_spi *dws = spi_master_get_devdata(master); |
289 | struct chip_data *chip = spi_get_ctldata(spi); | |
e24c7452 | 290 | u8 imask = 0; |
ea11370f | 291 | u16 txlevel = 0; |
e24c7452 FT |
292 | u16 clk_div = 0; |
293 | u32 speed = 0; | |
294 | u32 cr0 = 0; | |
9f14538e | 295 | int ret; |
e24c7452 | 296 | |
f89a6d8f | 297 | dws->dma_mapped = 0; |
e24c7452 FT |
298 | dws->n_bytes = chip->n_bytes; |
299 | dws->dma_width = chip->dma_width; | |
e24c7452 | 300 | |
e24c7452 FT |
301 | dws->tx = (void *)transfer->tx_buf; |
302 | dws->tx_end = dws->tx + transfer->len; | |
303 | dws->rx = transfer->rx_buf; | |
304 | dws->rx_end = dws->rx + transfer->len; | |
c22c62db | 305 | dws->len = transfer->len; |
e24c7452 | 306 | |
0b2e8915 AS |
307 | spi_enable_chip(dws, 0); |
308 | ||
e24c7452 FT |
309 | cr0 = chip->cr0; |
310 | ||
311 | /* Handle per transfer options for bpw and speed */ | |
312 | if (transfer->speed_hz) { | |
313 | speed = chip->speed_hz; | |
314 | ||
341c7dc7 | 315 | if ((transfer->speed_hz != speed) || !chip->clk_div) { |
e24c7452 | 316 | speed = transfer->speed_hz; |
e24c7452 FT |
317 | |
318 | /* clk_div doesn't support odd number */ | |
341c7dc7 | 319 | clk_div = (dws->max_freq / speed + 1) & 0xfffe; |
e24c7452 FT |
320 | |
321 | chip->speed_hz = speed; | |
322 | chip->clk_div = clk_div; | |
0b2e8915 AS |
323 | |
324 | spi_set_clk(dws, chip->clk_div); | |
e24c7452 FT |
325 | } |
326 | } | |
327 | if (transfer->bits_per_word) { | |
e31abce7 AS |
328 | if (transfer->bits_per_word == 8) { |
329 | dws->n_bytes = 1; | |
330 | dws->dma_width = 1; | |
331 | } else if (transfer->bits_per_word == 16) { | |
332 | dws->n_bytes = 2; | |
333 | dws->dma_width = 2; | |
334 | } | |
335 | cr0 = (transfer->bits_per_word - 1) | |
e24c7452 FT |
336 | | (chip->type << SPI_FRF_OFFSET) |
337 | | (spi->mode << SPI_MODE_OFFSET) | |
338 | | (chip->tmode << SPI_TMOD_OFFSET); | |
339 | } | |
e24c7452 | 340 | |
052dc7c4 GS |
341 | /* |
342 | * Adjust transfer mode if necessary. Requires platform dependent | |
343 | * chipselect mechanism. | |
344 | */ | |
c22c62db | 345 | if (chip->cs_control) { |
052dc7c4 | 346 | if (dws->rx && dws->tx) |
e3e55ff5 | 347 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 348 | else if (dws->rx) |
e3e55ff5 | 349 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 350 | else |
e3e55ff5 | 351 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 352 | |
e3e55ff5 | 353 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
354 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
355 | } | |
356 | ||
dd114443 | 357 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
0b2e8915 | 358 | |
e24c7452 | 359 | /* Check if current transfer is a DMA transaction */ |
f89a6d8f AS |
360 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
361 | dws->dma_mapped = master->cur_msg_mapped; | |
e24c7452 | 362 | |
0b2e8915 AS |
363 | /* For poll mode just disable all interrupts */ |
364 | spi_mask_intr(dws, 0xff); | |
365 | ||
552e4509 FT |
366 | /* |
367 | * Interrupt mode | |
368 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
369 | */ | |
9f14538e | 370 | if (dws->dma_mapped) { |
f89a6d8f | 371 | ret = dws->dma_ops->dma_setup(dws, transfer); |
9f14538e AS |
372 | if (ret < 0) { |
373 | spi_enable_chip(dws, 1); | |
374 | return ret; | |
375 | } | |
376 | } else if (!chip->poll_mode) { | |
ea11370f | 377 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
dd114443 | 378 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
552e4509 | 379 | |
0b2e8915 | 380 | /* Set the interrupt mask */ |
fadcace7 JH |
381 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
382 | SPI_INT_RXUI | SPI_INT_RXOI; | |
0b2e8915 AS |
383 | spi_umask_intr(dws, imask); |
384 | ||
e24c7452 FT |
385 | dws->transfer_handler = interrupt_transfer; |
386 | } | |
387 | ||
0b2e8915 | 388 | spi_enable_chip(dws, 1); |
e24c7452 | 389 | |
9f14538e | 390 | if (dws->dma_mapped) { |
f89a6d8f | 391 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
9f14538e AS |
392 | if (ret < 0) |
393 | return ret; | |
394 | } | |
e24c7452 FT |
395 | |
396 | if (chip->poll_mode) | |
c22c62db | 397 | return poll_transfer(dws); |
e24c7452 | 398 | |
c22c62db | 399 | return 1; |
e24c7452 FT |
400 | } |
401 | ||
c22c62db | 402 | static void dw_spi_handle_err(struct spi_master *master, |
ec37e8e1 | 403 | struct spi_message *msg) |
e24c7452 | 404 | { |
ec37e8e1 | 405 | struct dw_spi *dws = spi_master_get_devdata(master); |
e24c7452 | 406 | |
4d5ac1ed AS |
407 | if (dws->dma_mapped) |
408 | dws->dma_ops->dma_stop(dws); | |
409 | ||
c22c62db | 410 | spi_reset_chip(dws); |
e24c7452 FT |
411 | } |
412 | ||
413 | /* This may be called twice for each spi dev */ | |
414 | static int dw_spi_setup(struct spi_device *spi) | |
415 | { | |
416 | struct dw_spi_chip *chip_info = NULL; | |
417 | struct chip_data *chip; | |
d9c73bb8 | 418 | int ret; |
e24c7452 | 419 | |
e24c7452 FT |
420 | /* Only alloc on first setup */ |
421 | chip = spi_get_ctldata(spi); | |
422 | if (!chip) { | |
a97c883a | 423 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
e24c7452 FT |
424 | if (!chip) |
425 | return -ENOMEM; | |
43f627ac | 426 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
427 | } |
428 | ||
429 | /* | |
430 | * Protocol drivers may change the chip settings, so... | |
431 | * if chip_info exists, use it | |
432 | */ | |
433 | chip_info = spi->controller_data; | |
434 | ||
435 | /* chip_info doesn't always exist */ | |
436 | if (chip_info) { | |
437 | if (chip_info->cs_control) | |
438 | chip->cs_control = chip_info->cs_control; | |
439 | ||
440 | chip->poll_mode = chip_info->poll_mode; | |
441 | chip->type = chip_info->type; | |
442 | ||
443 | chip->rx_threshold = 0; | |
444 | chip->tx_threshold = 0; | |
e24c7452 FT |
445 | } |
446 | ||
24778be2 | 447 | if (spi->bits_per_word == 8) { |
e24c7452 FT |
448 | chip->n_bytes = 1; |
449 | chip->dma_width = 1; | |
24778be2 | 450 | } else if (spi->bits_per_word == 16) { |
e24c7452 FT |
451 | chip->n_bytes = 2; |
452 | chip->dma_width = 2; | |
e24c7452 FT |
453 | } |
454 | chip->bits_per_word = spi->bits_per_word; | |
455 | ||
552e4509 FT |
456 | if (!spi->max_speed_hz) { |
457 | dev_err(&spi->dev, "No max speed HZ parameter\n"); | |
458 | return -EINVAL; | |
459 | } | |
e24c7452 FT |
460 | |
461 | chip->tmode = 0; /* Tx & Rx */ | |
462 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ | |
463 | chip->cr0 = (chip->bits_per_word - 1) | |
464 | | (chip->type << SPI_FRF_OFFSET) | |
465 | | (spi->mode << SPI_MODE_OFFSET) | |
466 | | (chip->tmode << SPI_TMOD_OFFSET); | |
467 | ||
c3ce15bf AS |
468 | if (spi->mode & SPI_LOOP) |
469 | chip->cr0 |= 1 << SPI_SRL_OFFSET; | |
470 | ||
d9c73bb8 BS |
471 | if (gpio_is_valid(spi->cs_gpio)) { |
472 | ret = gpio_direction_output(spi->cs_gpio, | |
473 | !(spi->mode & SPI_CS_HIGH)); | |
474 | if (ret) | |
475 | return ret; | |
476 | } | |
477 | ||
e24c7452 FT |
478 | return 0; |
479 | } | |
480 | ||
a97c883a AL |
481 | static void dw_spi_cleanup(struct spi_device *spi) |
482 | { | |
483 | struct chip_data *chip = spi_get_ctldata(spi); | |
484 | ||
485 | kfree(chip); | |
486 | spi_set_ctldata(spi, NULL); | |
487 | } | |
488 | ||
e24c7452 | 489 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
30b4b703 | 490 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
e24c7452 | 491 | { |
45746e82 | 492 | spi_reset_chip(dws); |
c587b6fa FT |
493 | |
494 | /* | |
495 | * Try to detect the FIFO depth if not set by interface driver, | |
496 | * the depth could be from 2 to 256 from HW spec | |
497 | */ | |
498 | if (!dws->fifo_len) { | |
499 | u32 fifo; | |
fadcace7 | 500 | |
9d239d35 | 501 | for (fifo = 1; fifo < 256; fifo++) { |
dd114443 TT |
502 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
503 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
504 | break; |
505 | } | |
dd114443 | 506 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 507 | |
9d239d35 | 508 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
30b4b703 | 509 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
c587b6fa | 510 | } |
e24c7452 FT |
511 | } |
512 | ||
04f421e7 | 513 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 FT |
514 | { |
515 | struct spi_master *master; | |
516 | int ret; | |
517 | ||
518 | BUG_ON(dws == NULL); | |
519 | ||
04f421e7 BS |
520 | master = spi_alloc_master(dev, 0); |
521 | if (!master) | |
522 | return -ENOMEM; | |
e24c7452 FT |
523 | |
524 | dws->master = master; | |
525 | dws->type = SSI_MOTO_SPI; | |
e24c7452 FT |
526 | dws->dma_inited = 0; |
527 | dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); | |
c3c6e231 | 528 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); |
e24c7452 | 529 | |
04f421e7 | 530 | ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, |
c22c62db | 531 | dws->name, master); |
e24c7452 FT |
532 | if (ret < 0) { |
533 | dev_err(&master->dev, "can not get IRQ\n"); | |
534 | goto err_free_master; | |
535 | } | |
536 | ||
c3ce15bf | 537 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
24778be2 | 538 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
e24c7452 FT |
539 | master->bus_num = dws->bus_num; |
540 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 541 | master->setup = dw_spi_setup; |
a97c883a | 542 | master->cleanup = dw_spi_cleanup; |
c22c62db AS |
543 | master->set_cs = dw_spi_set_cs; |
544 | master->transfer_one = dw_spi_transfer_one; | |
545 | master->handle_err = dw_spi_handle_err; | |
765ee709 | 546 | master->max_speed_hz = dws->max_freq; |
9c6de47d | 547 | master->dev.of_node = dev->of_node; |
e24c7452 | 548 | |
e24c7452 | 549 | /* Basic HW init */ |
30b4b703 | 550 | spi_hw_init(dev, dws); |
e24c7452 | 551 | |
7063c0d9 FT |
552 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
553 | ret = dws->dma_ops->dma_init(dws); | |
554 | if (ret) { | |
3dbb3b98 | 555 | dev_warn(dev, "DMA init failed\n"); |
7063c0d9 | 556 | dws->dma_inited = 0; |
f89a6d8f AS |
557 | } else { |
558 | master->can_dma = dws->dma_ops->can_dma; | |
7063c0d9 FT |
559 | } |
560 | } | |
561 | ||
e24c7452 | 562 | spi_master_set_devdata(master, dws); |
04f421e7 | 563 | ret = devm_spi_register_master(dev, master); |
e24c7452 FT |
564 | if (ret) { |
565 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 566 | goto err_dma_exit; |
e24c7452 FT |
567 | } |
568 | ||
53288fe9 | 569 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
570 | return 0; |
571 | ||
ec37e8e1 | 572 | err_dma_exit: |
7063c0d9 FT |
573 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
574 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 575 | spi_enable_chip(dws, 0); |
e24c7452 FT |
576 | err_free_master: |
577 | spi_master_put(master); | |
e24c7452 FT |
578 | return ret; |
579 | } | |
79290a2a | 580 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 581 | |
fd4a319b | 582 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 583 | { |
e24c7452 FT |
584 | if (!dws) |
585 | return; | |
53288fe9 | 586 | dw_spi_debugfs_remove(dws); |
e24c7452 | 587 | |
7063c0d9 FT |
588 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
589 | dws->dma_ops->dma_exit(dws); | |
e24c7452 FT |
590 | spi_enable_chip(dws, 0); |
591 | /* Disable clk */ | |
592 | spi_set_clk(dws, 0); | |
e24c7452 | 593 | } |
79290a2a | 594 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
595 | |
596 | int dw_spi_suspend_host(struct dw_spi *dws) | |
597 | { | |
598 | int ret = 0; | |
599 | ||
ec37e8e1 | 600 | ret = spi_master_suspend(dws->master); |
e24c7452 FT |
601 | if (ret) |
602 | return ret; | |
603 | spi_enable_chip(dws, 0); | |
604 | spi_set_clk(dws, 0); | |
605 | return ret; | |
606 | } | |
79290a2a | 607 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
608 | |
609 | int dw_spi_resume_host(struct dw_spi *dws) | |
610 | { | |
611 | int ret; | |
612 | ||
30b4b703 | 613 | spi_hw_init(&dws->master->dev, dws); |
ec37e8e1 | 614 | ret = spi_master_resume(dws->master); |
e24c7452 FT |
615 | if (ret) |
616 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); | |
617 | return ret; | |
618 | } | |
79290a2a | 619 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
620 | |
621 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
622 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
623 | MODULE_LICENSE("GPL v2"); |