Commit | Line | Data |
---|---|---|
e24c7452 | 1 | /* |
ca632f55 | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
e24c7452 FT |
3 | * |
4 | * Copyright (c) 2009, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
e24c7452 FT |
14 | */ |
15 | ||
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/interrupt.h> | |
d7614de4 | 18 | #include <linux/module.h> |
e24c7452 FT |
19 | #include <linux/highmem.h> |
20 | #include <linux/delay.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
e24c7452 | 22 | #include <linux/spi/spi.h> |
d9c73bb8 | 23 | #include <linux/gpio.h> |
e24c7452 | 24 | |
ca632f55 | 25 | #include "spi-dw.h" |
568a60ed | 26 | |
e24c7452 FT |
27 | #ifdef CONFIG_DEBUG_FS |
28 | #include <linux/debugfs.h> | |
29 | #endif | |
30 | ||
31 | #define START_STATE ((void *)0) | |
32 | #define RUNNING_STATE ((void *)1) | |
33 | #define DONE_STATE ((void *)2) | |
34 | #define ERROR_STATE ((void *)-1) | |
35 | ||
e24c7452 FT |
36 | /* Slave spi_dev related */ |
37 | struct chip_data { | |
38 | u16 cr0; | |
39 | u8 cs; /* chip select pin */ | |
40 | u8 n_bytes; /* current is a 1/2/4 byte op */ | |
41 | u8 tmode; /* TR/TO/RO/EEPROM */ | |
42 | u8 type; /* SPI/SSP/MicroWire */ | |
43 | ||
44 | u8 poll_mode; /* 1 means use poll mode */ | |
45 | ||
46 | u32 dma_width; | |
47 | u32 rx_threshold; | |
48 | u32 tx_threshold; | |
49 | u8 enable_dma; | |
50 | u8 bits_per_word; | |
51 | u16 clk_div; /* baud rate divider */ | |
52 | u32 speed_hz; /* baud rate */ | |
e24c7452 FT |
53 | void (*cs_control)(u32 command); |
54 | }; | |
55 | ||
56 | #ifdef CONFIG_DEBUG_FS | |
e24c7452 | 57 | #define SPI_REGS_BUFSIZE 1024 |
53288fe9 AS |
58 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
59 | size_t count, loff_t *ppos) | |
e24c7452 | 60 | { |
53288fe9 | 61 | struct dw_spi *dws = file->private_data; |
e24c7452 FT |
62 | char *buf; |
63 | u32 len = 0; | |
64 | ssize_t ret; | |
65 | ||
e24c7452 FT |
66 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
67 | if (!buf) | |
68 | return 0; | |
69 | ||
70 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
53288fe9 | 71 | "%s registers:\n", dev_name(&dws->master->dev)); |
e24c7452 FT |
72 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
73 | "=================================\n"); | |
74 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, | |
7eb187b3 | 75 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
e24c7452 | 76 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 77 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
e24c7452 | 78 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 79 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
e24c7452 | 80 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 81 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
e24c7452 | 82 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 83 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
e24c7452 | 84 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 85 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
e24c7452 | 86 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 87 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
e24c7452 | 88 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 89 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
e24c7452 | 90 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 91 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
e24c7452 | 92 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 93 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
e24c7452 | 94 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 95 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
e24c7452 | 96 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 97 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
e24c7452 | 98 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 99 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
e24c7452 | 100 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 101 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
e24c7452 | 102 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
7eb187b3 | 103 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
e24c7452 FT |
104 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
105 | "=================================\n"); | |
106 | ||
53288fe9 | 107 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
e24c7452 FT |
108 | kfree(buf); |
109 | return ret; | |
110 | } | |
111 | ||
53288fe9 | 112 | static const struct file_operations dw_spi_regs_ops = { |
e24c7452 | 113 | .owner = THIS_MODULE, |
234e3405 | 114 | .open = simple_open, |
53288fe9 | 115 | .read = dw_spi_show_regs, |
6038f373 | 116 | .llseek = default_llseek, |
e24c7452 FT |
117 | }; |
118 | ||
53288fe9 | 119 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 120 | { |
53288fe9 | 121 | dws->debugfs = debugfs_create_dir("dw_spi", NULL); |
e24c7452 FT |
122 | if (!dws->debugfs) |
123 | return -ENOMEM; | |
124 | ||
125 | debugfs_create_file("registers", S_IFREG | S_IRUGO, | |
53288fe9 | 126 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
e24c7452 FT |
127 | return 0; |
128 | } | |
129 | ||
53288fe9 | 130 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 | 131 | { |
fadcace7 | 132 | debugfs_remove_recursive(dws->debugfs); |
e24c7452 FT |
133 | } |
134 | ||
135 | #else | |
53288fe9 | 136 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
e24c7452 | 137 | { |
20a588fc | 138 | return 0; |
e24c7452 FT |
139 | } |
140 | ||
53288fe9 | 141 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
e24c7452 FT |
142 | { |
143 | } | |
144 | #endif /* CONFIG_DEBUG_FS */ | |
145 | ||
2ff271bf AD |
146 | /* Return the max entries we can fill into tx fifo */ |
147 | static inline u32 tx_max(struct dw_spi *dws) | |
148 | { | |
149 | u32 tx_left, tx_room, rxtx_gap; | |
150 | ||
151 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; | |
7eb187b3 | 152 | tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR); |
2ff271bf AD |
153 | |
154 | /* | |
155 | * Another concern is about the tx/rx mismatch, we | |
156 | * though to use (dws->fifo_len - rxflr - txflr) as | |
157 | * one maximum value for tx, but it doesn't cover the | |
158 | * data which is out of tx/rx fifo and inside the | |
159 | * shift registers. So a control from sw point of | |
160 | * view is taken. | |
161 | */ | |
162 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) | |
163 | / dws->n_bytes; | |
164 | ||
165 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); | |
166 | } | |
167 | ||
168 | /* Return the max entries we should read out of rx fifo */ | |
169 | static inline u32 rx_max(struct dw_spi *dws) | |
170 | { | |
171 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; | |
172 | ||
fadcace7 | 173 | return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR)); |
2ff271bf AD |
174 | } |
175 | ||
3b8a4dd3 | 176 | static void dw_writer(struct dw_spi *dws) |
e24c7452 | 177 | { |
2ff271bf | 178 | u32 max = tx_max(dws); |
de6efe0a | 179 | u16 txw = 0; |
e24c7452 | 180 | |
2ff271bf AD |
181 | while (max--) { |
182 | /* Set the tx word if the transfer's original "tx" is not null */ | |
183 | if (dws->tx_end - dws->len) { | |
184 | if (dws->n_bytes == 1) | |
185 | txw = *(u8 *)(dws->tx); | |
186 | else | |
187 | txw = *(u16 *)(dws->tx); | |
188 | } | |
7eb187b3 | 189 | dw_writew(dws, DW_SPI_DR, txw); |
2ff271bf | 190 | dws->tx += dws->n_bytes; |
e24c7452 | 191 | } |
e24c7452 FT |
192 | } |
193 | ||
3b8a4dd3 | 194 | static void dw_reader(struct dw_spi *dws) |
e24c7452 | 195 | { |
2ff271bf | 196 | u32 max = rx_max(dws); |
de6efe0a | 197 | u16 rxw; |
e24c7452 | 198 | |
2ff271bf | 199 | while (max--) { |
7eb187b3 | 200 | rxw = dw_readw(dws, DW_SPI_DR); |
de6efe0a FT |
201 | /* Care rx only if the transfer's original "rx" is not null */ |
202 | if (dws->rx_end - dws->len) { | |
203 | if (dws->n_bytes == 1) | |
204 | *(u8 *)(dws->rx) = rxw; | |
205 | else | |
206 | *(u16 *)(dws->rx) = rxw; | |
207 | } | |
208 | dws->rx += dws->n_bytes; | |
e24c7452 | 209 | } |
e24c7452 FT |
210 | } |
211 | ||
212 | static void *next_transfer(struct dw_spi *dws) | |
213 | { | |
214 | struct spi_message *msg = dws->cur_msg; | |
215 | struct spi_transfer *trans = dws->cur_transfer; | |
216 | ||
217 | /* Move to next transfer */ | |
218 | if (trans->transfer_list.next != &msg->transfers) { | |
219 | dws->cur_transfer = | |
220 | list_entry(trans->transfer_list.next, | |
221 | struct spi_transfer, | |
222 | transfer_list); | |
223 | return RUNNING_STATE; | |
fadcace7 JH |
224 | } |
225 | ||
226 | return DONE_STATE; | |
e24c7452 FT |
227 | } |
228 | ||
229 | /* | |
230 | * Note: first step is the protocol driver prepares | |
231 | * a dma-capable memory, and this func just need translate | |
232 | * the virt addr to physical | |
233 | */ | |
234 | static int map_dma_buffers(struct dw_spi *dws) | |
235 | { | |
7063c0d9 FT |
236 | if (!dws->cur_msg->is_dma_mapped |
237 | || !dws->dma_inited | |
238 | || !dws->cur_chip->enable_dma | |
239 | || !dws->dma_ops) | |
e24c7452 FT |
240 | return 0; |
241 | ||
242 | if (dws->cur_transfer->tx_dma) | |
243 | dws->tx_dma = dws->cur_transfer->tx_dma; | |
244 | ||
245 | if (dws->cur_transfer->rx_dma) | |
246 | dws->rx_dma = dws->cur_transfer->rx_dma; | |
247 | ||
248 | return 1; | |
249 | } | |
250 | ||
251 | /* Caller already set message->status; dma and pio irqs are blocked */ | |
252 | static void giveback(struct dw_spi *dws) | |
253 | { | |
254 | struct spi_transfer *last_transfer; | |
e24c7452 FT |
255 | struct spi_message *msg; |
256 | ||
e24c7452 FT |
257 | msg = dws->cur_msg; |
258 | dws->cur_msg = NULL; | |
259 | dws->cur_transfer = NULL; | |
260 | dws->prev_chip = dws->cur_chip; | |
261 | dws->cur_chip = NULL; | |
262 | dws->dma_mapped = 0; | |
e24c7452 | 263 | |
23e2c2aa | 264 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e24c7452 FT |
265 | transfer_list); |
266 | ||
d9c73bb8 BS |
267 | if (!last_transfer->cs_change) |
268 | spi_chip_sel(dws, dws->cur_msg->spi, 0); | |
e24c7452 | 269 | |
ec37e8e1 | 270 | spi_finalize_current_message(dws->master); |
e24c7452 FT |
271 | } |
272 | ||
273 | static void int_error_stop(struct dw_spi *dws, const char *msg) | |
274 | { | |
8a33a373 | 275 | /* Stop the hw */ |
e24c7452 FT |
276 | spi_enable_chip(dws, 0); |
277 | ||
278 | dev_err(&dws->master->dev, "%s\n", msg); | |
279 | dws->cur_msg->state = ERROR_STATE; | |
280 | tasklet_schedule(&dws->pump_transfers); | |
281 | } | |
282 | ||
7063c0d9 | 283 | void dw_spi_xfer_done(struct dw_spi *dws) |
e24c7452 | 284 | { |
25985edc | 285 | /* Update total byte transferred return count actual bytes read */ |
e24c7452 FT |
286 | dws->cur_msg->actual_length += dws->len; |
287 | ||
288 | /* Move to next transfer */ | |
289 | dws->cur_msg->state = next_transfer(dws); | |
290 | ||
291 | /* Handle end of message */ | |
292 | if (dws->cur_msg->state == DONE_STATE) { | |
293 | dws->cur_msg->status = 0; | |
294 | giveback(dws); | |
295 | } else | |
296 | tasklet_schedule(&dws->pump_transfers); | |
297 | } | |
7063c0d9 | 298 | EXPORT_SYMBOL_GPL(dw_spi_xfer_done); |
e24c7452 FT |
299 | |
300 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) | |
301 | { | |
7eb187b3 | 302 | u16 irq_status = dw_readw(dws, DW_SPI_ISR); |
e24c7452 | 303 | |
e24c7452 FT |
304 | /* Error handling */ |
305 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { | |
7eb187b3 HS |
306 | dw_readw(dws, DW_SPI_TXOICR); |
307 | dw_readw(dws, DW_SPI_RXOICR); | |
308 | dw_readw(dws, DW_SPI_RXUICR); | |
3b8a4dd3 | 309 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
e24c7452 FT |
310 | return IRQ_HANDLED; |
311 | } | |
312 | ||
3b8a4dd3 AD |
313 | dw_reader(dws); |
314 | if (dws->rx_end == dws->rx) { | |
315 | spi_mask_intr(dws, SPI_INT_TXEI); | |
316 | dw_spi_xfer_done(dws); | |
317 | return IRQ_HANDLED; | |
318 | } | |
552e4509 FT |
319 | if (irq_status & SPI_INT_TXEI) { |
320 | spi_mask_intr(dws, SPI_INT_TXEI); | |
3b8a4dd3 AD |
321 | dw_writer(dws); |
322 | /* Enable TX irq always, it will be disabled when RX finished */ | |
323 | spi_umask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
324 | } |
325 | ||
e24c7452 FT |
326 | return IRQ_HANDLED; |
327 | } | |
328 | ||
329 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) | |
330 | { | |
331 | struct dw_spi *dws = dev_id; | |
7eb187b3 | 332 | u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f; |
cbcc062a | 333 | |
cbcc062a YW |
334 | if (!irq_status) |
335 | return IRQ_NONE; | |
e24c7452 FT |
336 | |
337 | if (!dws->cur_msg) { | |
338 | spi_mask_intr(dws, SPI_INT_TXEI); | |
e24c7452 FT |
339 | return IRQ_HANDLED; |
340 | } | |
341 | ||
342 | return dws->transfer_handler(dws); | |
343 | } | |
344 | ||
345 | /* Must be called inside pump_transfers() */ | |
346 | static void poll_transfer(struct dw_spi *dws) | |
347 | { | |
2ff271bf AD |
348 | do { |
349 | dw_writer(dws); | |
de6efe0a | 350 | dw_reader(dws); |
2ff271bf AD |
351 | cpu_relax(); |
352 | } while (dws->rx_end > dws->rx); | |
e24c7452 | 353 | |
7063c0d9 | 354 | dw_spi_xfer_done(dws); |
e24c7452 FT |
355 | } |
356 | ||
357 | static void pump_transfers(unsigned long data) | |
358 | { | |
359 | struct dw_spi *dws = (struct dw_spi *)data; | |
360 | struct spi_message *message = NULL; | |
361 | struct spi_transfer *transfer = NULL; | |
362 | struct spi_transfer *previous = NULL; | |
363 | struct spi_device *spi = NULL; | |
364 | struct chip_data *chip = NULL; | |
365 | u8 bits = 0; | |
366 | u8 imask = 0; | |
367 | u8 cs_change = 0; | |
552e4509 | 368 | u16 txint_level = 0; |
e24c7452 FT |
369 | u16 clk_div = 0; |
370 | u32 speed = 0; | |
371 | u32 cr0 = 0; | |
372 | ||
373 | /* Get current state information */ | |
374 | message = dws->cur_msg; | |
375 | transfer = dws->cur_transfer; | |
376 | chip = dws->cur_chip; | |
377 | spi = message->spi; | |
378 | ||
552e4509 FT |
379 | if (unlikely(!chip->clk_div)) |
380 | chip->clk_div = dws->max_freq / chip->speed_hz; | |
381 | ||
e24c7452 FT |
382 | if (message->state == ERROR_STATE) { |
383 | message->status = -EIO; | |
384 | goto early_exit; | |
385 | } | |
386 | ||
387 | /* Handle end of message */ | |
388 | if (message->state == DONE_STATE) { | |
389 | message->status = 0; | |
390 | goto early_exit; | |
391 | } | |
392 | ||
393 | /* Delay if requested at end of transfer*/ | |
394 | if (message->state == RUNNING_STATE) { | |
395 | previous = list_entry(transfer->transfer_list.prev, | |
396 | struct spi_transfer, | |
397 | transfer_list); | |
398 | if (previous->delay_usecs) | |
399 | udelay(previous->delay_usecs); | |
400 | } | |
401 | ||
402 | dws->n_bytes = chip->n_bytes; | |
403 | dws->dma_width = chip->dma_width; | |
404 | dws->cs_control = chip->cs_control; | |
405 | ||
406 | dws->rx_dma = transfer->rx_dma; | |
407 | dws->tx_dma = transfer->tx_dma; | |
408 | dws->tx = (void *)transfer->tx_buf; | |
409 | dws->tx_end = dws->tx + transfer->len; | |
410 | dws->rx = transfer->rx_buf; | |
411 | dws->rx_end = dws->rx + transfer->len; | |
e24c7452 FT |
412 | dws->len = dws->cur_transfer->len; |
413 | if (chip != dws->prev_chip) | |
414 | cs_change = 1; | |
415 | ||
416 | cr0 = chip->cr0; | |
417 | ||
418 | /* Handle per transfer options for bpw and speed */ | |
419 | if (transfer->speed_hz) { | |
420 | speed = chip->speed_hz; | |
421 | ||
422 | if (transfer->speed_hz != speed) { | |
423 | speed = transfer->speed_hz; | |
e24c7452 FT |
424 | |
425 | /* clk_div doesn't support odd number */ | |
426 | clk_div = dws->max_freq / speed; | |
552e4509 | 427 | clk_div = (clk_div + 1) & 0xfffe; |
e24c7452 FT |
428 | |
429 | chip->speed_hz = speed; | |
430 | chip->clk_div = clk_div; | |
431 | } | |
432 | } | |
433 | if (transfer->bits_per_word) { | |
434 | bits = transfer->bits_per_word; | |
24778be2 | 435 | dws->n_bytes = dws->dma_width = bits >> 3; |
e24c7452 FT |
436 | cr0 = (bits - 1) |
437 | | (chip->type << SPI_FRF_OFFSET) | |
438 | | (spi->mode << SPI_MODE_OFFSET) | |
439 | | (chip->tmode << SPI_TMOD_OFFSET); | |
440 | } | |
441 | message->state = RUNNING_STATE; | |
442 | ||
052dc7c4 GS |
443 | /* |
444 | * Adjust transfer mode if necessary. Requires platform dependent | |
445 | * chipselect mechanism. | |
446 | */ | |
447 | if (dws->cs_control) { | |
448 | if (dws->rx && dws->tx) | |
e3e55ff5 | 449 | chip->tmode = SPI_TMOD_TR; |
052dc7c4 | 450 | else if (dws->rx) |
e3e55ff5 | 451 | chip->tmode = SPI_TMOD_RO; |
052dc7c4 | 452 | else |
e3e55ff5 | 453 | chip->tmode = SPI_TMOD_TO; |
052dc7c4 | 454 | |
e3e55ff5 | 455 | cr0 &= ~SPI_TMOD_MASK; |
052dc7c4 GS |
456 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
457 | } | |
458 | ||
e24c7452 FT |
459 | /* Check if current transfer is a DMA transaction */ |
460 | dws->dma_mapped = map_dma_buffers(dws); | |
461 | ||
552e4509 FT |
462 | /* |
463 | * Interrupt mode | |
464 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely | |
465 | */ | |
e24c7452 | 466 | if (!dws->dma_mapped && !chip->poll_mode) { |
552e4509 | 467 | int templen = dws->len / dws->n_bytes; |
fadcace7 | 468 | |
552e4509 FT |
469 | txint_level = dws->fifo_len / 2; |
470 | txint_level = (templen > txint_level) ? txint_level : templen; | |
471 | ||
fadcace7 JH |
472 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
473 | SPI_INT_RXUI | SPI_INT_RXOI; | |
e24c7452 FT |
474 | dws->transfer_handler = interrupt_transfer; |
475 | } | |
476 | ||
477 | /* | |
478 | * Reprogram registers only if | |
479 | * 1. chip select changes | |
480 | * 2. clk_div is changed | |
481 | * 3. control value changes | |
482 | */ | |
7eb187b3 | 483 | if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) { |
e24c7452 FT |
484 | spi_enable_chip(dws, 0); |
485 | ||
7eb187b3 HS |
486 | if (dw_readw(dws, DW_SPI_CTRL0) != cr0) |
487 | dw_writew(dws, DW_SPI_CTRL0, cr0); | |
e24c7452 | 488 | |
552e4509 | 489 | spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); |
d9c73bb8 | 490 | spi_chip_sel(dws, spi, 1); |
552e4509 | 491 | |
2f263d9d | 492 | /* Set the interrupt mask, for poll mode just disable all int */ |
e24c7452 | 493 | spi_mask_intr(dws, 0xff); |
552e4509 | 494 | if (imask) |
e24c7452 | 495 | spi_umask_intr(dws, imask); |
552e4509 | 496 | if (txint_level) |
7eb187b3 | 497 | dw_writew(dws, DW_SPI_TXFLTR, txint_level); |
e24c7452 | 498 | |
e24c7452 | 499 | spi_enable_chip(dws, 1); |
e24c7452 FT |
500 | if (cs_change) |
501 | dws->prev_chip = chip; | |
502 | } | |
503 | ||
504 | if (dws->dma_mapped) | |
7063c0d9 | 505 | dws->dma_ops->dma_transfer(dws, cs_change); |
e24c7452 FT |
506 | |
507 | if (chip->poll_mode) | |
508 | poll_transfer(dws); | |
509 | ||
510 | return; | |
511 | ||
512 | early_exit: | |
513 | giveback(dws); | |
e24c7452 FT |
514 | } |
515 | ||
ec37e8e1 BS |
516 | static int dw_spi_transfer_one_message(struct spi_master *master, |
517 | struct spi_message *msg) | |
e24c7452 | 518 | { |
ec37e8e1 | 519 | struct dw_spi *dws = spi_master_get_devdata(master); |
e24c7452 | 520 | |
ec37e8e1 | 521 | dws->cur_msg = msg; |
e24c7452 FT |
522 | /* Initial message state*/ |
523 | dws->cur_msg->state = START_STATE; | |
524 | dws->cur_transfer = list_entry(dws->cur_msg->transfers.next, | |
525 | struct spi_transfer, | |
526 | transfer_list); | |
527 | dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi); | |
528 | ||
ec37e8e1 | 529 | /* Launch transfers */ |
e24c7452 FT |
530 | tasklet_schedule(&dws->pump_transfers); |
531 | ||
e24c7452 FT |
532 | return 0; |
533 | } | |
534 | ||
535 | /* This may be called twice for each spi dev */ | |
536 | static int dw_spi_setup(struct spi_device *spi) | |
537 | { | |
538 | struct dw_spi_chip *chip_info = NULL; | |
539 | struct chip_data *chip; | |
d9c73bb8 | 540 | int ret; |
e24c7452 | 541 | |
e24c7452 FT |
542 | /* Only alloc on first setup */ |
543 | chip = spi_get_ctldata(spi); | |
544 | if (!chip) { | |
43f627ac BS |
545 | chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data), |
546 | GFP_KERNEL); | |
e24c7452 FT |
547 | if (!chip) |
548 | return -ENOMEM; | |
43f627ac | 549 | spi_set_ctldata(spi, chip); |
e24c7452 FT |
550 | } |
551 | ||
552 | /* | |
553 | * Protocol drivers may change the chip settings, so... | |
554 | * if chip_info exists, use it | |
555 | */ | |
556 | chip_info = spi->controller_data; | |
557 | ||
558 | /* chip_info doesn't always exist */ | |
559 | if (chip_info) { | |
560 | if (chip_info->cs_control) | |
561 | chip->cs_control = chip_info->cs_control; | |
562 | ||
563 | chip->poll_mode = chip_info->poll_mode; | |
564 | chip->type = chip_info->type; | |
565 | ||
566 | chip->rx_threshold = 0; | |
567 | chip->tx_threshold = 0; | |
568 | ||
569 | chip->enable_dma = chip_info->enable_dma; | |
570 | } | |
571 | ||
24778be2 | 572 | if (spi->bits_per_word == 8) { |
e24c7452 FT |
573 | chip->n_bytes = 1; |
574 | chip->dma_width = 1; | |
24778be2 | 575 | } else if (spi->bits_per_word == 16) { |
e24c7452 FT |
576 | chip->n_bytes = 2; |
577 | chip->dma_width = 2; | |
e24c7452 FT |
578 | } |
579 | chip->bits_per_word = spi->bits_per_word; | |
580 | ||
552e4509 FT |
581 | if (!spi->max_speed_hz) { |
582 | dev_err(&spi->dev, "No max speed HZ parameter\n"); | |
583 | return -EINVAL; | |
584 | } | |
e24c7452 | 585 | chip->speed_hz = spi->max_speed_hz; |
e24c7452 FT |
586 | |
587 | chip->tmode = 0; /* Tx & Rx */ | |
588 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ | |
589 | chip->cr0 = (chip->bits_per_word - 1) | |
590 | | (chip->type << SPI_FRF_OFFSET) | |
591 | | (spi->mode << SPI_MODE_OFFSET) | |
592 | | (chip->tmode << SPI_TMOD_OFFSET); | |
593 | ||
d9c73bb8 BS |
594 | if (gpio_is_valid(spi->cs_gpio)) { |
595 | ret = gpio_direction_output(spi->cs_gpio, | |
596 | !(spi->mode & SPI_CS_HIGH)); | |
597 | if (ret) | |
598 | return ret; | |
599 | } | |
600 | ||
e24c7452 FT |
601 | return 0; |
602 | } | |
603 | ||
e24c7452 FT |
604 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
605 | static void spi_hw_init(struct dw_spi *dws) | |
606 | { | |
607 | spi_enable_chip(dws, 0); | |
608 | spi_mask_intr(dws, 0xff); | |
609 | spi_enable_chip(dws, 1); | |
c587b6fa FT |
610 | |
611 | /* | |
612 | * Try to detect the FIFO depth if not set by interface driver, | |
613 | * the depth could be from 2 to 256 from HW spec | |
614 | */ | |
615 | if (!dws->fifo_len) { | |
616 | u32 fifo; | |
fadcace7 | 617 | |
c587b6fa | 618 | for (fifo = 2; fifo <= 257; fifo++) { |
7eb187b3 HS |
619 | dw_writew(dws, DW_SPI_TXFLTR, fifo); |
620 | if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) | |
c587b6fa FT |
621 | break; |
622 | } | |
623 | ||
624 | dws->fifo_len = (fifo == 257) ? 0 : fifo; | |
7eb187b3 | 625 | dw_writew(dws, DW_SPI_TXFLTR, 0); |
c587b6fa | 626 | } |
e24c7452 FT |
627 | } |
628 | ||
04f421e7 | 629 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
e24c7452 FT |
630 | { |
631 | struct spi_master *master; | |
632 | int ret; | |
633 | ||
634 | BUG_ON(dws == NULL); | |
635 | ||
04f421e7 BS |
636 | master = spi_alloc_master(dev, 0); |
637 | if (!master) | |
638 | return -ENOMEM; | |
e24c7452 FT |
639 | |
640 | dws->master = master; | |
641 | dws->type = SSI_MOTO_SPI; | |
642 | dws->prev_chip = NULL; | |
643 | dws->dma_inited = 0; | |
644 | dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); | |
40bfff85 LS |
645 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", |
646 | dws->bus_num); | |
e24c7452 | 647 | |
04f421e7 | 648 | ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, |
40bfff85 | 649 | dws->name, dws); |
e24c7452 FT |
650 | if (ret < 0) { |
651 | dev_err(&master->dev, "can not get IRQ\n"); | |
652 | goto err_free_master; | |
653 | } | |
654 | ||
655 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
24778be2 | 656 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
e24c7452 FT |
657 | master->bus_num = dws->bus_num; |
658 | master->num_chipselect = dws->num_cs; | |
e24c7452 | 659 | master->setup = dw_spi_setup; |
ec37e8e1 | 660 | master->transfer_one_message = dw_spi_transfer_one_message; |
765ee709 | 661 | master->max_speed_hz = dws->max_freq; |
e24c7452 | 662 | |
e24c7452 FT |
663 | /* Basic HW init */ |
664 | spi_hw_init(dws); | |
665 | ||
7063c0d9 FT |
666 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
667 | ret = dws->dma_ops->dma_init(dws); | |
668 | if (ret) { | |
669 | dev_warn(&master->dev, "DMA init failed\n"); | |
670 | dws->dma_inited = 0; | |
671 | } | |
672 | } | |
673 | ||
ec37e8e1 | 674 | tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws); |
e24c7452 FT |
675 | |
676 | spi_master_set_devdata(master, dws); | |
04f421e7 | 677 | ret = devm_spi_register_master(dev, master); |
e24c7452 FT |
678 | if (ret) { |
679 | dev_err(&master->dev, "problem registering spi master\n"); | |
ec37e8e1 | 680 | goto err_dma_exit; |
e24c7452 FT |
681 | } |
682 | ||
53288fe9 | 683 | dw_spi_debugfs_init(dws); |
e24c7452 FT |
684 | return 0; |
685 | ||
ec37e8e1 | 686 | err_dma_exit: |
7063c0d9 FT |
687 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
688 | dws->dma_ops->dma_exit(dws); | |
e24c7452 | 689 | spi_enable_chip(dws, 0); |
e24c7452 FT |
690 | err_free_master: |
691 | spi_master_put(master); | |
e24c7452 FT |
692 | return ret; |
693 | } | |
79290a2a | 694 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
e24c7452 | 695 | |
fd4a319b | 696 | void dw_spi_remove_host(struct dw_spi *dws) |
e24c7452 | 697 | { |
e24c7452 FT |
698 | if (!dws) |
699 | return; | |
53288fe9 | 700 | dw_spi_debugfs_remove(dws); |
e24c7452 | 701 | |
7063c0d9 FT |
702 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
703 | dws->dma_ops->dma_exit(dws); | |
e24c7452 FT |
704 | spi_enable_chip(dws, 0); |
705 | /* Disable clk */ | |
706 | spi_set_clk(dws, 0); | |
e24c7452 | 707 | } |
79290a2a | 708 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
e24c7452 FT |
709 | |
710 | int dw_spi_suspend_host(struct dw_spi *dws) | |
711 | { | |
712 | int ret = 0; | |
713 | ||
ec37e8e1 | 714 | ret = spi_master_suspend(dws->master); |
e24c7452 FT |
715 | if (ret) |
716 | return ret; | |
717 | spi_enable_chip(dws, 0); | |
718 | spi_set_clk(dws, 0); | |
719 | return ret; | |
720 | } | |
79290a2a | 721 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
e24c7452 FT |
722 | |
723 | int dw_spi_resume_host(struct dw_spi *dws) | |
724 | { | |
725 | int ret; | |
726 | ||
727 | spi_hw_init(dws); | |
ec37e8e1 | 728 | ret = spi_master_resume(dws->master); |
e24c7452 FT |
729 | if (ret) |
730 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); | |
731 | return ret; | |
732 | } | |
79290a2a | 733 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
e24c7452 FT |
734 | |
735 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); | |
736 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); | |
737 | MODULE_LICENSE("GPL v2"); |