[deliverable/linux.git] / drivers / spi / spi-fsl-dspi.c

/*
 * drivers/spi/spi-fsl-dspi.c
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Freescale DSPI driver
 * This file contains a driver for the Freescale DSPI
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define DRIVER_NAME "fsl-dspi"

#define TRAN_STATE_RX_VOID		0x01
#define TRAN_STATE_TX_VOID		0x02
#define TRAN_STATE_WORD_ODD_NUM	0x04

#define DSPI_FIFO_SIZE			4

#define SPI_MCR		0x00
#define SPI_MCR_MASTER		(1 << 31)
#define SPI_MCR_PCSIS		(0x3F << 16)
#define SPI_MCR_CLR_TXF	(1 << 11)
#define SPI_MCR_CLR_RXF	(1 << 10)

#define SPI_TCR			0x08

#define SPI_CTAR(x)		(0x0c + (x * 4))
#define SPI_CTAR_FMSZ(x)	(((x) & 0x0000000f) << 27)
#define SPI_CTAR_CPOL(x)	((x) << 26)
#define SPI_CTAR_CPHA(x)	((x) << 25)
#define SPI_CTAR_LSBFE(x)	((x) << 24)
#define SPI_CTAR_PCSSCR(x)	(((x) & 0x00000003) << 22)
#define SPI_CTAR_PASC(x)	(((x) & 0x00000003) << 20)
#define SPI_CTAR_PDT(x)	(((x) & 0x00000003) << 18)
#define SPI_CTAR_PBR(x)	(((x) & 0x00000003) << 16)
#define SPI_CTAR_CSSCK(x)	(((x) & 0x0000000f) << 12)
#define SPI_CTAR_ASC(x)	(((x) & 0x0000000f) << 8)
#define SPI_CTAR_DT(x)		(((x) & 0x0000000f) << 4)
#define SPI_CTAR_BR(x)		((x) & 0x0000000f)

#define SPI_CTAR0_SLAVE	0x0c

#define SPI_SR			0x2c
#define SPI_SR_EOQF		0x10000000

#define SPI_RSER		0x30
#define SPI_RSER_EOQFE		0x10000000

#define SPI_PUSHR		0x34
#define SPI_PUSHR_CONT		(1 << 31)
#define SPI_PUSHR_CTAS(x)	(((x) & 0x00000007) << 28)
#define SPI_PUSHR_EOQ		(1 << 27)
#define SPI_PUSHR_CTCNT	(1 << 26)
#define SPI_PUSHR_PCS(x)	(((1 << x) & 0x0000003f) << 16)
#define SPI_PUSHR_TXDATA(x)	((x) & 0x0000ffff)

#define SPI_PUSHR_SLAVE	0x34

#define SPI_POPR		0x38
#define SPI_POPR_RXDATA(x)	((x) & 0x0000ffff)

#define SPI_TXFR0		0x3c
#define SPI_TXFR1		0x40
#define SPI_TXFR2		0x44
#define SPI_TXFR3		0x48
#define SPI_RXFR0		0x7c
#define SPI_RXFR1		0x80
#define SPI_RXFR2		0x84
#define SPI_RXFR3		0x88

#define SPI_FRAME_BITS(bits)	SPI_CTAR_FMSZ((bits) - 1)
#define SPI_FRAME_BITS_MASK	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_16	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_8	SPI_CTAR_FMSZ(0x7)

#define SPI_CS_INIT		0x01
#define SPI_CS_ASSERT		0x02
#define SPI_CS_DROP		0x04

struct chip_data {
	u32 mcr_val;
	u32 ctar_val;
	u16 void_write_data;
};

struct fsl_dspi {
	struct spi_bitbang	bitbang;
	struct platform_device	*pdev;

	struct regmap		*regmap;
	int			irq;
	struct clk		*clk;

	struct spi_transfer	*cur_transfer;
	struct chip_data	*cur_chip;
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	char			dataflags;
	u8			cs;
	u16			void_write_data;

	wait_queue_head_t	waitq;
	u32			waitflags;
};

static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
	unsigned int val;

	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);

	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
}

static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
		unsigned long clkrate)
{
	/* Valid baud rate pre-scaler values */
	int pbr_tbl[4] = {2, 3, 5, 7};
	int brs[16] = {	2,	4,	6,	8,
		16,	32,	64,	128,
		256,	512,	1024,	2048,
		4096,	8192,	16384,	32768 };
	int temp, i = 0, j = 0;

	temp = clkrate / 2 / speed_hz;

	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
		for (j = 0; j < ARRAY_SIZE(brs); j++) {
			if (pbr_tbl[i] * brs[j] >= temp) {
				*pbr = i;
				*br = j;
				return;
			}
		}

	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
		,we use the max prescaler value.\n", speed_hz, clkrate);
	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	*br =  ARRAY_SIZE(brs) - 1;
}

static int dspi_transfer_write(struct fsl_dspi *dspi)
{
	int tx_count = 0;
	int tx_word;
	u16 d16;
	u8  d8;
	u32 dspi_pushr = 0;
	int first = 1;

	tx_word = is_double_byte_mode(dspi);

	/* If we are in word mode, but only have a single byte to transfer
	 * then switch to byte mode temporarily.  Will switch back at the
	 * end of the transfer.
	 */
	if (tx_word && (dspi->len == 1)) {
		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
		regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
		tx_word = 0;
	}

	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
		if (tx_word) {
			if (dspi->len == 1)
				break;

			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
				d16 = *(u16 *)dspi->tx;
				dspi->tx += 2;
			} else {
				d16 = dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d16) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len -= 2;
		} else {
			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {

				d8 = *(u8 *)dspi->tx;
				dspi->tx++;
			} else {
				d8 = (u8)dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d8) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len--;
		}

		if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
			/* last transfer in the transfer */
			dspi_pushr |= SPI_PUSHR_EOQ;
		} else if (tx_word && (dspi->len == 1))
			dspi_pushr |= SPI_PUSHR_EOQ;

		if (first) {
			first = 0;
			dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
		}

		regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);

		tx_count++;
	}

	return tx_count * (tx_word + 1);
}

static int dspi_transfer_read(struct fsl_dspi *dspi)
{
	int rx_count = 0;
	int rx_word = is_double_byte_mode(dspi);
	u16 d;
	while ((dspi->rx < dspi->rx_end)
			&& (rx_count < DSPI_FIFO_SIZE)) {
		if (rx_word) {
			unsigned int val;

			if ((dspi->rx_end - dspi->rx) == 1)
				break;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);

			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u16 *)dspi->rx = d;
			dspi->rx += 2;

		} else {
			unsigned int val;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);
			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u8 *)dspi->rx = d;
			dspi->rx++;
		}
		rx_count++;
	}

	return rx_count;
}

static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	dspi->cur_transfer = t;
	dspi->cur_chip = spi_get_ctldata(spi);
	dspi->cs = spi->chip_select;
	dspi->void_write_data = dspi->cur_chip->void_write_data;

	dspi->dataflags = 0;
	dspi->tx = (void *)t->tx_buf;
	dspi->tx_end = dspi->tx + t->len;
	dspi->rx = t->rx_buf;
	dspi->rx_end = dspi->rx + t->len;
	dspi->len = t->len;

	if (!dspi->rx)
		dspi->dataflags |= TRAN_STATE_RX_VOID;

	if (!dspi->tx)
		dspi->dataflags |= TRAN_STATE_TX_VOID;

	regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
	regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);

	if (t->speed_hz)
		regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
				dspi->cur_chip->ctar_val);

	dspi_transfer_write(dspi);

	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
		dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
	dspi->waitflags = 0;

	return t->len - dspi->len;
}

static void dspi_chipselect(struct spi_device *spi, int value)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	unsigned int pushr;

	regmap_read(dspi->regmap, SPI_PUSHR, &pushr);

	switch (value) {
	case BITBANG_CS_ACTIVE:
		pushr |= SPI_PUSHR_CONT;
		break;
	case BITBANG_CS_INACTIVE:
		pushr &= ~SPI_PUSHR_CONT;
		break;
	}

	regmap_write(dspi->regmap, SPI_PUSHR, pushr);
}

static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct chip_data *chip;
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	unsigned char br = 0, pbr = 0, fmsz = 0;

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (chip == NULL) {
		chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
	}

	chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
		SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
		fmsz = spi->bits_per_word - 1;
	} else {
		pr_err("Invalid wordsize\n");
		kfree(chip);
		return -ENODEV;
	}

	chip->void_write_data = 0;

	hz_to_spi_baud(&pbr, &br,
			spi->max_speed_hz, clk_get_rate(dspi->clk));

	chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
		| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
		| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
		| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
		| SPI_CTAR_PBR(pbr)
		| SPI_CTAR_BR(br);

	spi_set_ctldata(spi, chip);

	return 0;
}

static int dspi_setup(struct spi_device *spi)
{
	if (!spi->max_speed_hz)
		return -EINVAL;

	return dspi_setup_transfer(spi, NULL);
}

static irqreturn_t dspi_interrupt(int irq, void *dev_id)
{
	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;

	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);

	dspi_transfer_read(dspi);

	if (!dspi->len) {
		if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
			regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));

		dspi->waitflags = 1;
		wake_up_interruptible(&dspi->waitq);
	} else {
		dspi_transfer_write(dspi);

		return IRQ_HANDLED;
	}

	return IRQ_HANDLED;
}

static struct of_device_id fsl_dspi_dt_ids[] = {
	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);

#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(dspi->clk);

	return 0;
}

static int dspi_resume(struct device *dev)
{

	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	clk_prepare_enable(dspi->clk);
	spi_master_resume(master);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops dspi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
};

static struct regmap_config dspi_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = 0x88,
};

static int dspi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct fsl_dspi *dspi;
	struct resource *res;
	void __iomem *base;
	int ret = 0, cs_num, bus_num;

	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	if (!master)
		return -ENOMEM;

	dspi = spi_master_get_devdata(master);
	dspi->pdev = pdev;
	dspi->bitbang.master = master;
	dspi->bitbang.chipselect = dspi_chipselect;
	dspi->bitbang.setup_transfer = dspi_setup_transfer;
	dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
	dspi->bitbang.master->setup = dspi_setup;
	dspi->bitbang.master->dev.of_node = pdev->dev.of_node;

	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
					SPI_BPW_MASK(16);

	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
		goto out_master_put;
	}
	master->num_chipselect = cs_num;

	ret = of_property_read_u32(np, "bus-num", &bus_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get bus-num\n");
		goto out_master_put;
	}
	master->bus_num = bus_num;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base)) {
		ret = PTR_ERR(base);
		goto out_master_put;
	}

	dspi_regmap_config.lock_arg = dspi;
	dspi_regmap_config.val_format_endian =
		of_property_read_bool(np, "big-endian")
			? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
						&dspi_regmap_config);
	if (IS_ERR(dspi->regmap)) {
		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
				PTR_ERR(dspi->regmap));
		return PTR_ERR(dspi->regmap);
	}

	dspi->irq = platform_get_irq(pdev, 0);
	if (dspi->irq < 0) {
		dev_err(&pdev->dev, "can't get platform irq\n");
		ret = dspi->irq;
		goto out_master_put;
	}

	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
			pdev->name, dspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
		goto out_master_put;
	}

	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	if (IS_ERR(dspi->clk)) {
		ret = PTR_ERR(dspi->clk);
		dev_err(&pdev->dev, "unable to get clock\n");
		goto out_master_put;
	}
	clk_prepare_enable(dspi->clk);

	init_waitqueue_head(&dspi->waitq);
	platform_set_drvdata(pdev, dspi);

	ret = spi_bitbang_start(&dspi->bitbang);
	if (ret != 0) {
		dev_err(&pdev->dev, "Problem registering DSPI master\n");
		goto out_clk_put;
	}

	pr_info(KERN_INFO "Freescale DSPI master initialized\n");
	return ret;

out_clk_put:
	clk_disable_unprepare(dspi->clk);
out_master_put:
	spi_master_put(master);

	return ret;
}

static int dspi_remove(struct platform_device *pdev)
{
	struct fsl_dspi *dspi = platform_get_drvdata(pdev);

	/* Disconnect from the SPI framework */
	spi_bitbang_stop(&dspi->bitbang);
	clk_disable_unprepare(dspi->clk);
	spi_master_put(dspi->bitbang.master);

	return 0;
}

static struct platform_driver fsl_dspi_driver = {
	.driver.name    = DRIVER_NAME,
	.driver.of_match_table = fsl_dspi_dt_ids,
	.driver.owner   = THIS_MODULE,
	.driver.pm = &dspi_pm,
	.probe          = dspi_probe,
	.remove		= dspi_remove,
};
module_platform_driver(fsl_dspi_driver);

MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
349ad66c CF	1	/*
	2	* drivers/spi/spi-fsl-dspi.c
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* Freescale DSPI driver
	7	* This file contains a driver for the Freescale DSPI
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/errno.h>
	20	#include <linux/platform_device.h>
1acbdeb9	21	#include <linux/regmap.h>
349ad66c CF	22	#include <linux/sched.h>
	23	#include <linux/delay.h>
	24	#include <linux/io.h>
	25	#include <linux/clk.h>
	26	#include <linux/err.h>
	27	#include <linux/spi/spi.h>
	28	#include <linux/spi/spi_bitbang.h>
	29	#include <linux/pm_runtime.h>
	30	#include <linux/of.h>
	31	#include <linux/of_device.h>
	32
	33	#define DRIVER_NAME "fsl-dspi"
	34
	35	#define TRAN_STATE_RX_VOID 0x01
	36	#define TRAN_STATE_TX_VOID 0x02
	37	#define TRAN_STATE_WORD_ODD_NUM 0x04
	38
	39	#define DSPI_FIFO_SIZE 4
	40
	41	#define SPI_MCR 0x00
	42	#define SPI_MCR_MASTER (1 << 31)
	43	#define SPI_MCR_PCSIS (0x3F << 16)
	44	#define SPI_MCR_CLR_TXF (1 << 11)
	45	#define SPI_MCR_CLR_RXF (1 << 10)
	46
	47	#define SPI_TCR 0x08
	48
	49	#define SPI_CTAR(x) (0x0c + (x * 4))
	50	#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
	51	#define SPI_CTAR_CPOL(x) ((x) << 26)
	52	#define SPI_CTAR_CPHA(x) ((x) << 25)
	53	#define SPI_CTAR_LSBFE(x) ((x) << 24)
	54	#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
	55	#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
	56	#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
	57	#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
	58	#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
	59	#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
	60	#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
	61	#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
	62
	63	#define SPI_CTAR0_SLAVE 0x0c
	64
	65	#define SPI_SR 0x2c
	66	#define SPI_SR_EOQF 0x10000000
	67
	68	#define SPI_RSER 0x30
	69	#define SPI_RSER_EOQFE 0x10000000
	70
	71	#define SPI_PUSHR 0x34
	72	#define SPI_PUSHR_CONT (1 << 31)
	73	#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
	74	#define SPI_PUSHR_EOQ (1 << 27)
	75	#define SPI_PUSHR_CTCNT (1 << 26)
	76	#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
	77	#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
	78
	79	#define SPI_PUSHR_SLAVE 0x34
	80
	81	#define SPI_POPR 0x38
	82	#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
	83
	84	#define SPI_TXFR0 0x3c
	85	#define SPI_TXFR1 0x40
86	#define SPI_TXFR2 0x44
87	#define SPI_TXFR3 0x48
88	#define SPI_RXFR0 0x7c
89	#define SPI_RXFR1 0x80
90	#define SPI_RXFR2 0x84
91	#define SPI_RXFR3 0x88
92
93	#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
94	#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
95	#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
96	#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
97
98	#define SPI_CS_INIT 0x01
99	#define SPI_CS_ASSERT 0x02
100	#define SPI_CS_DROP 0x04
101
102	struct chip_data {
103	u32 mcr_val;
104	u32 ctar_val;
105	u16 void_write_data;
106	};
107
108	struct fsl_dspi {
109	struct spi_bitbang bitbang;
110	struct platform_device *pdev;
111
1acbdeb9	112	struct regmap *regmap;
349ad66c	113	int irq;
88386e85	114	struct clk *clk;
349ad66c	115
88386e85	116	struct spi_transfer *cur_transfer;
349ad66c CF	117	struct chip_data *cur_chip;
	118	size_t len;
	119	void *tx;
	120	void *tx_end;
	121	void *rx;
	122	void *rx_end;
	123	char dataflags;
	124	u8 cs;
	125	u16 void_write_data;
	126
88386e85 CF	127	wait_queue_head_t waitq;
88386e85 CF	128	u32 waitflags;
349ad66c CF	129	};
	130
	131	static inline int is_double_byte_mode(struct fsl_dspi *dspi)
	132	{
1acbdeb9	133	unsigned int val;
349ad66c	134
1acbdeb9	135	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
349ad66c	136
1acbdeb9	137	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
349ad66c CF	138	}
	139
	140	static void hz_to_spi_baud(char pbr, char br, int speed_hz,
	141	unsigned long clkrate)
	142	{
	143	/* Valid baud rate pre-scaler values */
	144	int pbr_tbl[4] = {2, 3, 5, 7};
	145	int brs[16] = { 2, 4, 6, 8,
	146	16, 32, 64, 128,
	147	256, 512, 1024, 2048,
	148	4096, 8192, 16384, 32768 };
	149	int temp, i = 0, j = 0;
	150
	151	temp = clkrate / 2 / speed_hz;
	152
	153	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
	154	for (j = 0; j < ARRAY_SIZE(brs); j++) {
	155	if (pbr_tbl[i] * brs[j] >= temp) {
	156	*pbr = i;
	157	*br = j;
	158	return;
	159	}
	160	}
	161
b444d1df	162	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
349ad66c CF	163	,we use the max prescaler value.\n", speed_hz, clkrate);
	164	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	165	*br = ARRAY_SIZE(brs) - 1;
	166	}
	167
	168	static int dspi_transfer_write(struct fsl_dspi *dspi)
	169	{
	170	int tx_count = 0;
	171	int tx_word;
	172	u16 d16;
	173	u8 d8;
	174	u32 dspi_pushr = 0;
	175	int first = 1;
	176
	177	tx_word = is_double_byte_mode(dspi);
	178
	179	/* If we are in word mode, but only have a single byte to transfer
	180	* then switch to byte mode temporarily. Will switch back at the
	181	* end of the transfer.
	182	*/
	183	if (tx_word && (dspi->len == 1)) {
	184	dspi->dataflags \|= TRAN_STATE_WORD_ODD_NUM;
1acbdeb9 CF	185	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	186	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
349ad66c CF	187	tx_word = 0;
	188	}
	189
	190	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
	191	if (tx_word) {
	192	if (dspi->len == 1)
	193	break;
	194
	195	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	196	d16 = (u16 )dspi->tx;
	197	dspi->tx += 2;
	198	} else {
	199	d16 = dspi->void_write_data;
	200	}
	201
	202	dspi_pushr = SPI_PUSHR_TXDATA(d16) \|
	203	SPI_PUSHR_PCS(dspi->cs) \|
	204	SPI_PUSHR_CTAS(dspi->cs) \|
	205	SPI_PUSHR_CONT;
	206
	207	dspi->len -= 2;
	208	} else {
	209	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	210
	211	d8 = (u8 )dspi->tx;
	212	dspi->tx++;
	213	} else {
	214	d8 = (u8)dspi->void_write_data;
	215	}
	216
	217	dspi_pushr = SPI_PUSHR_TXDATA(d8) \|
	218	SPI_PUSHR_PCS(dspi->cs) \|
	219	SPI_PUSHR_CTAS(dspi->cs) \|
	220	SPI_PUSHR_CONT;
	221
	222	dspi->len--;
	223	}
	224
	225	if (dspi->len == 0 \|\| tx_count == DSPI_FIFO_SIZE - 1) {
	226	/* last transfer in the transfer */
	227	dspi_pushr \|= SPI_PUSHR_EOQ;
	228	} else if (tx_word && (dspi->len == 1))
	229	dspi_pushr \|= SPI_PUSHR_EOQ;
	230
	231	if (first) {
	232	first = 0;
	233	dspi_pushr \|= SPI_PUSHR_CTCNT; /* clear counter */
	234	}
	235
1acbdeb9 CF	236	regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
1acbdeb9 CF	237
349ad66c CF	238	tx_count++;
	239	}
	240
	241	return tx_count * (tx_word + 1);
	242	}
	243
	244	static int dspi_transfer_read(struct fsl_dspi *dspi)
	245	{
	246	int rx_count = 0;
	247	int rx_word = is_double_byte_mode(dspi);
	248	u16 d;
	249	while ((dspi->rx < dspi->rx_end)
	250	&& (rx_count < DSPI_FIFO_SIZE)) {
	251	if (rx_word) {
1acbdeb9 CF	252	unsigned int val;
1acbdeb9 CF	253
349ad66c CF	254	if ((dspi->rx_end - dspi->rx) == 1)
	255	break;
	256
1acbdeb9 CF	257	regmap_read(dspi->regmap, SPI_POPR, &val);
1acbdeb9 CF	258	d = SPI_POPR_RXDATA(val);
349ad66c CF	259
	260	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	261	(u16 )dspi->rx = d;
	262	dspi->rx += 2;
	263
	264	} else {
1acbdeb9 CF	265	unsigned int val;
	266
	267	regmap_read(dspi->regmap, SPI_POPR, &val);
	268	d = SPI_POPR_RXDATA(val);
349ad66c CF	269	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	270	(u8 )dspi->rx = d;
	271	dspi->rx++;
	272	}
	273	rx_count++;
	274	}
	275
	276	return rx_count;
	277	}
	278
	279	static int dspi_txrx_transfer(struct spi_device spi, struct spi_transfer t)
	280	{
	281	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	282	dspi->cur_transfer = t;
	283	dspi->cur_chip = spi_get_ctldata(spi);
	284	dspi->cs = spi->chip_select;
	285	dspi->void_write_data = dspi->cur_chip->void_write_data;
	286
	287	dspi->dataflags = 0;
	288	dspi->tx = (void *)t->tx_buf;
	289	dspi->tx_end = dspi->tx + t->len;
	290	dspi->rx = t->rx_buf;
	291	dspi->rx_end = dspi->rx + t->len;
	292	dspi->len = t->len;
	293
	294	if (!dspi->rx)
	295	dspi->dataflags \|= TRAN_STATE_RX_VOID;
	296
	297	if (!dspi->tx)
	298	dspi->dataflags \|= TRAN_STATE_TX_VOID;
	299
1acbdeb9 CF	300	regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
	301	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
	302	regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
349ad66c CF	303
349ad66c CF	304	if (t->speed_hz)
1acbdeb9 CF	305	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	306	dspi->cur_chip->ctar_val);
349ad66c CF	307
	308	dspi_transfer_write(dspi);
	309
	310	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
	311	dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
	312	dspi->waitflags = 0;
	313
	314	return t->len - dspi->len;
	315	}
	316
	317	static void dspi_chipselect(struct spi_device *spi, int value)
	318	{
	319	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
1acbdeb9 CF	320	unsigned int pushr;
	321
	322	regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
349ad66c CF	323
	324	switch (value) {
	325	case BITBANG_CS_ACTIVE:
	326	pushr \|= SPI_PUSHR_CONT;
e07725be	327	break;
349ad66c CF	328	case BITBANG_CS_INACTIVE:
349ad66c CF	329	pushr &= ~SPI_PUSHR_CONT;
e07725be	330	break;
349ad66c CF	331	}
349ad66c CF	332
1acbdeb9	333	regmap_write(dspi->regmap, SPI_PUSHR, pushr);
349ad66c CF	334	}
	335
	336	static int dspi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	337	{
	338	struct chip_data *chip;
	339	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	340	unsigned char br = 0, pbr = 0, fmsz = 0;
	341
	342	/* Only alloc on first setup */
	343	chip = spi_get_ctldata(spi);
	344	if (chip == NULL) {
	345	chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
	346	if (!chip)
	347	return -ENOMEM;
	348	}
	349
	350	chip->mcr_val = SPI_MCR_MASTER \| SPI_MCR_PCSIS \|
	351	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF;
	352	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
	353	fmsz = spi->bits_per_word - 1;
	354	} else {
	355	pr_err("Invalid wordsize\n");
	356	kfree(chip);
	357	return -ENODEV;
	358	}
	359
	360	chip->void_write_data = 0;
	361
	362	hz_to_spi_baud(&pbr, &br,
	363	spi->max_speed_hz, clk_get_rate(dspi->clk));
	364
	365	chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
	366	\| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
	367	\| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
	368	\| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
	369	\| SPI_CTAR_PBR(pbr)
	370	\| SPI_CTAR_BR(br);
	371
	372	spi_set_ctldata(spi, chip);
	373
	374	return 0;
	375	}
	376
	377	static int dspi_setup(struct spi_device *spi)
	378	{
	379	if (!spi->max_speed_hz)
	380	return -EINVAL;
	381
349ad66c CF	382	return dspi_setup_transfer(spi, NULL);
	383	}
	384
	385	static irqreturn_t dspi_interrupt(int irq, void *dev_id)
	386	{
	387	struct fsl_dspi dspi = (struct fsl_dspi )dev_id;
	388
1acbdeb9	389	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
349ad66c CF	390
	391	dspi_transfer_read(dspi);
	392
	393	if (!dspi->len) {
	394	if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
1acbdeb9 CF	395	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
	396	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
	397
349ad66c CF	398	dspi->waitflags = 1;
	399	wake_up_interruptible(&dspi->waitq);
	400	} else {
	401	dspi_transfer_write(dspi);
	402
	403	return IRQ_HANDLED;
	404	}
	405
	406	return IRQ_HANDLED;
	407	}
	408
	409	static struct of_device_id fsl_dspi_dt_ids[] = {
	410	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	411	{ /* sentinel */ }
	412	};
	413	MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
	414
	415	#ifdef CONFIG_PM_SLEEP
	416	static int dspi_suspend(struct device *dev)
	417	{
	418	struct spi_master *master = dev_get_drvdata(dev);
	419	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	420
	421	spi_master_suspend(master);
	422	clk_disable_unprepare(dspi->clk);
	423
	424	return 0;
	425	}
	426
	427	static int dspi_resume(struct device *dev)
	428	{
	429
	430	struct spi_master *master = dev_get_drvdata(dev);
	431	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	432
	433	clk_prepare_enable(dspi->clk);
	434	spi_master_resume(master);
	435
	436	return 0;
	437	}
	438	#endif /* CONFIG_PM_SLEEP */
	439
	440	static const struct dev_pm_ops dspi_pm = {
	441	SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume)
	442	};
	443
1acbdeb9 CF	444	static struct regmap_config dspi_regmap_config = {
	445	.reg_bits = 32,
	446	.val_bits = 32,
	447	.reg_stride = 4,
	448	.max_register = 0x88,
	449	};
	450
349ad66c CF	451	static int dspi_probe(struct platform_device *pdev)
	452	{
	453	struct device_node *np = pdev->dev.of_node;
	454	struct spi_master *master;
	455	struct fsl_dspi *dspi;
	456	struct resource *res;
1acbdeb9	457	void __iomem *base;
349ad66c CF	458	int ret = 0, cs_num, bus_num;
	459
	460	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	461	if (!master)
	462	return -ENOMEM;
	463
	464	dspi = spi_master_get_devdata(master);
	465	dspi->pdev = pdev;
94c69f76	466	dspi->bitbang.master = master;
349ad66c CF	467	dspi->bitbang.chipselect = dspi_chipselect;
	468	dspi->bitbang.setup_transfer = dspi_setup_transfer;
	469	dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
	470	dspi->bitbang.master->setup = dspi_setup;
	471	dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
	472
	473	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	474	master->bits_per_word_mask = SPI_BPW_MASK(4) \| SPI_BPW_MASK(8) \|
	475	SPI_BPW_MASK(16);
	476
	477	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	478	if (ret < 0) {
	479	dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
	480	goto out_master_put;
	481	}
	482	master->num_chipselect = cs_num;
	483
	484	ret = of_property_read_u32(np, "bus-num", &bus_num);
	485	if (ret < 0) {
	486	dev_err(&pdev->dev, "can't get bus-num\n");
	487	goto out_master_put;
	488	}
	489	master->bus_num = bus_num;
	490
	491	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1acbdeb9 CF	492	base = devm_ioremap_resource(&pdev->dev, res);
	493	if (IS_ERR(base)) {
	494	ret = PTR_ERR(base);
349ad66c CF	495	goto out_master_put;
	496	}
	497
1acbdeb9 CF	498	dspi_regmap_config.lock_arg = dspi;
	499	dspi_regmap_config.val_format_endian =
	500	of_property_read_bool(np, "big-endian")
	501	? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
	502	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
	503	&dspi_regmap_config);
	504	if (IS_ERR(dspi->regmap)) {
	505	dev_err(&pdev->dev, "failed to init regmap: %ld\n",
	506	PTR_ERR(dspi->regmap));
	507	return PTR_ERR(dspi->regmap);
	508	}
	509
349ad66c CF	510	dspi->irq = platform_get_irq(pdev, 0);
	511	if (dspi->irq < 0) {
	512	dev_err(&pdev->dev, "can't get platform irq\n");
	513	ret = dspi->irq;
	514	goto out_master_put;
	515	}
	516
	517	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
	518	pdev->name, dspi);
	519	if (ret < 0) {
	520	dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
	521	goto out_master_put;
	522	}
	523
	524	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	525	if (IS_ERR(dspi->clk)) {
	526	ret = PTR_ERR(dspi->clk);
	527	dev_err(&pdev->dev, "unable to get clock\n");
	528	goto out_master_put;
	529	}
	530	clk_prepare_enable(dspi->clk);
	531
	532	init_waitqueue_head(&dspi->waitq);
	533	platform_set_drvdata(pdev, dspi);
	534
	535	ret = spi_bitbang_start(&dspi->bitbang);
	536	if (ret != 0) {
	537	dev_err(&pdev->dev, "Problem registering DSPI master\n");
	538	goto out_clk_put;
	539	}
	540
	541	pr_info(KERN_INFO "Freescale DSPI master initialized\n");
	542	return ret;
	543
	544	out_clk_put:
	545	clk_disable_unprepare(dspi->clk);
	546	out_master_put:
	547	spi_master_put(master);
349ad66c CF	548
	549	return ret;
	550	}
	551
	552	static int dspi_remove(struct platform_device *pdev)
	553	{
	554	struct fsl_dspi *dspi = platform_get_drvdata(pdev);
	555
	556	/* Disconnect from the SPI framework */
	557	spi_bitbang_stop(&dspi->bitbang);
05209f45	558	clk_disable_unprepare(dspi->clk);
349ad66c CF	559	spi_master_put(dspi->bitbang.master);
	560
	561	return 0;
	562	}
	563
	564	static struct platform_driver fsl_dspi_driver = {
	565	.driver.name = DRIVER_NAME,
	566	.driver.of_match_table = fsl_dspi_dt_ids,
	567	.driver.owner = THIS_MODULE,
	568	.driver.pm = &dspi_pm,
	569	.probe = dspi_probe,
	570	.remove = dspi_remove,
	571	};
	572	module_platform_driver(fsl_dspi_driver);
	573
	574	MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
b444d1df	575	MODULE_LICENSE("GPL");
349ad66c	576	MODULE_ALIAS("platform:" DRIVER_NAME);