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intel_pstate: remove setting P state to MAX on init
[deliverable/linux.git] / drivers / spi / spi-fsl-espi.c
CommitLineData
8b60d6c2
MH		 1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
5af50730
RH		 19#include <linux/of_address.h>
20#include <linux/of_irq.h>
8b60d6c2 21#include <linux/of_platform.h>
8b60d6c2
MH		 22#include <linux/interrupt.h>
23#include <linux/err.h>
24#include <sysdev/fsl_soc.h>
25
ca632f55 26#include "spi-fsl-lib.h"
8b60d6c2
MH		 27
28/* eSPI Controller registers */
29struct fsl_espi_reg {
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38};
39
40struct fsl_espi_transfer {
41 const void *tx_buf;
42 void *rx_buf;
43 unsigned len;
44 unsigned n_tx;
45 unsigned n_rx;
46 unsigned actual_length;
47 int status;
48};
49
50/* eSPI Controller mode register definitions */
51#define SPMODE_ENABLE (1 << 31)
52#define SPMODE_LOOP (1 << 30)
53#define SPMODE_TXTHR(x) ((x) << 8)
54#define SPMODE_RXTHR(x) ((x) << 0)
55
56/* eSPI Controller CS mode register definitions */
57#define CSMODE_CI_INACTIVEHIGH (1 << 31)
58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59#define CSMODE_REV (1 << 29)
60#define CSMODE_DIV16 (1 << 28)
61#define CSMODE_PM(x) ((x) << 24)
62#define CSMODE_POL_1 (1 << 20)
63#define CSMODE_LEN(x) ((x) << 16)
64#define CSMODE_BEF(x) ((x) << 12)
65#define CSMODE_AFT(x) ((x) << 8)
66#define CSMODE_CG(x) ((x) << 3)
67
68/* Default mode/csmode for eSPI controller */
69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
72
73/* SPIE register values */
74#define SPIE_NE 0x00000200 /* Not empty */
75#define SPIE_NF 0x00000100 /* Not full */
76
77/* SPIM register values */
78#define SPIM_NE 0x00000200 /* Not empty */
79#define SPIM_NF 0x00000100 /* Not full */
80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
82
83/* SPCOM register values */
84#define SPCOM_CS(x) ((x) << 30)
85#define SPCOM_TRANLEN(x) ((x) << 0)
86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87
88static void fsl_espi_change_mode(struct spi_device *spi)
89{
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = &reg_base->mode;
95 u32 tmp;
96 unsigned long flags;
97
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
100
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
106
107 local_irq_restore(flags);
108}
109
110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
111{
112 u32 data;
113 u16 data_h;
114 u16 data_l;
115 const u32 *tx = mpc8xxx_spi->tx;
116
117 if (!tx)
118 return 0;
119
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
123 swab16s(&data_l);
124 swab16s(&data_h);
125 data = data_h | data_l;
126
127 mpc8xxx_spi->tx = tx;
128 return data;
129}
130
131static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
133{
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
136 u8 pm;
137 u32 hz = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139
140 if (t) {
141 bits_per_word = t->bits_per_word;
142 hz = t->speed_hz;
143 }
144
145 /* spi_transfer level calls that work per-word */
146 if (!bits_per_word)
147 bits_per_word = spi->bits_per_word;
148
8b60d6c2
MH		 149 if (!hz)
150 hz = spi->max_speed_hz;
151
152 cs->rx_shift = 0;
153 cs->tx_shift = 0;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
51faed69 158 } else {
8b60d6c2
MH		 159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
8b60d6c2
MH		 162 }
163
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
168
169 bits_per_word = bits_per_word - 1;
170
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
173
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
175
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
35faa55c 178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
8b60d6c2 179
87bf5ab8 180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
8b60d6c2 181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
87bf5ab8
SAS		 182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
183 if (pm > 33)
184 pm = 33;
8b60d6c2 185 } else {
35faa55c 186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
8b60d6c2
MH		 187 }
188 if (pm)
189 pm--;
87bf5ab8
SAS		 190 if (pm < 2)
191 pm = 2;
8b60d6c2
MH		 192
193 cs->hw_mode |= CSMODE_PM(pm);
194
195 fsl_espi_change_mode(spi);
196 return 0;
197}
198
199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
200 unsigned int len)
201{
202 u32 word;
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
204
205 mspi->count = len;
206
207 /* enable rx ints */
208 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
209
210 /* transmit word */
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
213
214 return 0;
215}
216
217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218{
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
8b60d6c2
MH		 222 int ret;
223
8b60d6c2
MH		 224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
226
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
229
16735d02 230 reinit_completion(&mpc8xxx_spi->done);
8b60d6c2
MH		 231
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
236 return -EINVAL;
237 }
238 mpc8xxx_spi_write_reg(&reg_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 if (ret)
243 return ret;
244
245 wait_for_completion(&mpc8xxx_spi->done);
246
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
249
250 return mpc8xxx_spi->count;
251}
252
0dd2c96f 253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
8b60d6c2 254{
0dd2c96f 255 if (cmd) {
8b60d6c2
MH		 256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
259 }
260}
261
0dd2c96f 262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
8b60d6c2 263{
0dd2c96f 264 if (cmd)
8b60d6c2
MH		 265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
266
267 return 0;
268}
269
270static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
272{
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
278 int status = 0;
279
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
282
283 first = list_first_entry(&m->transfers, struct spi_transfer,
284 transfer_list);
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
f6bd03a7
JN		 289 dev_err(mspi->dev,
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
8b60d6c2
MH		 291 return;
292 }
293
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
297 }
298
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
303
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
306 status = -EINVAL;
307
308 status = fsl_espi_setup_transfer(spi, t);
309 if (status < 0)
310 break;
311 }
312
313 if (t->len)
314 status = fsl_espi_bufs(spi, t);
315
316 if (status) {
317 status = -EMSGSIZE;
318 break;
319 }
320
321 if (t->delay_usecs)
322 udelay(t->delay_usecs);
323 }
324
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
327}
328
329static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
331{
332 struct spi_transfer *t;
333 u8 *local_buf;
334 int i = 0;
335 struct fsl_espi_transfer *espi_trans = trans;
336
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
338 if (!local_buf) {
339 espi_trans->status = -ENOMEM;
340 return;
341 }
342
343 list_for_each_entry(t, &m->transfers, transfer_list) {
344 if (t->tx_buf) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
346 i += t->len;
347 }
348 }
349
350 espi_trans->tx_buf = local_buf;
351 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
352 fsl_espi_do_trans(m, espi_trans);
353
354 espi_trans->actual_length = espi_trans->len;
355 kfree(local_buf);
356}
357
358static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
360{
361 struct fsl_espi_transfer *espi_trans = trans;
362 unsigned int n_tx = espi_trans->n_tx;
363 unsigned int n_rx = espi_trans->n_rx;
364 struct spi_transfer *t;
365 u8 *local_buf;
366 u8 *rx_buf = rx_buff;
367 unsigned int trans_len;
368 unsigned int addr;
369 int i, pos, loop;
370
371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
372 if (!local_buf) {
373 espi_trans->status = -ENOMEM;
374 return;
375 }
376
377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
378 trans_len = n_rx - pos;
379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
380 trans_len = SPCOM_TRANLEN_MAX - n_tx;
381
382 i = 0;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
384 if (t->tx_buf) {
385 memcpy(local_buf + i, t->tx_buf, t->len);
386 i += t->len;
387 }
388 }
389
0dd2c96f
MH		 390 if (pos > 0) {
391 addr = fsl_espi_cmd2addr(local_buf);
392 addr += pos;
393 fsl_espi_addr2cmd(addr, local_buf);
394 }
8b60d6c2
MH		 395
396 espi_trans->n_tx = n_tx;
397 espi_trans->n_rx = trans_len;
398 espi_trans->len = trans_len + n_tx;
399 espi_trans->tx_buf = local_buf;
400 espi_trans->rx_buf = local_buf + n_tx;
401 fsl_espi_do_trans(m, espi_trans);
402
403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
404
405 if (loop > 0)
406 espi_trans->actual_length += espi_trans->len - n_tx;
407 else
408 espi_trans->actual_length += espi_trans->len;
409 }
410
411 kfree(local_buf);
412}
413
414static void fsl_espi_do_one_msg(struct spi_message *m)
415{
416 struct spi_transfer *t;
417 u8 *rx_buf = NULL;
418 unsigned int n_tx = 0;
419 unsigned int n_rx = 0;
420 struct fsl_espi_transfer espi_trans;
421
422 list_for_each_entry(t, &m->transfers, transfer_list) {
423 if (t->tx_buf)
424 n_tx += t->len;
425 if (t->rx_buf) {
426 n_rx += t->len;
427 rx_buf = t->rx_buf;
428 }
429 }
430
431 espi_trans.n_tx = n_tx;
432 espi_trans.n_rx = n_rx;
433 espi_trans.len = n_tx + n_rx;
434 espi_trans.actual_length = 0;
435 espi_trans.status = 0;
436
437 if (!rx_buf)
438 fsl_espi_cmd_trans(m, &espi_trans, NULL);
439 else
440 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
441
442 m->actual_length = espi_trans.actual_length;
443 m->status = espi_trans.status;
0a6d3879
AL		 444 if (m->complete)
445 m->complete(m->context);
8b60d6c2
MH		 446}
447
448static int fsl_espi_setup(struct spi_device *spi)
449{
450 struct mpc8xxx_spi *mpc8xxx_spi;
451 struct fsl_espi_reg *reg_base;
452 int retval;
453 u32 hw_mode;
454 u32 loop_mode;
455 struct spi_mpc8xxx_cs *cs = spi->controller_state;
456
457 if (!spi->max_speed_hz)
458 return -EINVAL;
459
460 if (!cs) {
461 cs = kzalloc(sizeof *cs, GFP_KERNEL);
462 if (!cs)
463 return -ENOMEM;
464 spi->controller_state = cs;
465 }
466
467 mpc8xxx_spi = spi_master_get_devdata(spi->master);
468 reg_base = mpc8xxx_spi->reg_base;
469
25985edc 470 hw_mode = cs->hw_mode; /* Save original settings */
8b60d6c2
MH		 471 cs->hw_mode = mpc8xxx_spi_read_reg(
472 &reg_base->csmode[spi->chip_select]);
473 /* mask out bits we are going to set */
474 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
475 | CSMODE_REV);
476
477 if (spi->mode & SPI_CPHA)
478 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
479 if (spi->mode & SPI_CPOL)
480 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
481 if (!(spi->mode & SPI_LSB_FIRST))
482 cs->hw_mode |= CSMODE_REV;
483
484 /* Handle the loop mode */
485 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
486 loop_mode &= ~SPMODE_LOOP;
487 if (spi->mode & SPI_LOOP)
488 loop_mode |= SPMODE_LOOP;
489 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
490
491 retval = fsl_espi_setup_transfer(spi, NULL);
492 if (retval < 0) {
493 cs->hw_mode = hw_mode; /* Restore settings */
494 return retval;
495 }
496 return 0;
497}
498
499void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
500{
501 struct fsl_espi_reg *reg_base = mspi->reg_base;
502
503 /* We need handle RX first */
504 if (events & SPIE_NE) {
e6289d63
MH		 505 u32 rx_data, tmp;
506 u8 rx_data_8;
8b60d6c2
MH		 507
508 /* Spin until RX is done */
509 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
510 cpu_relax();
511 events = mpc8xxx_spi_read_reg(&reg_base->event);
512 }
8b60d6c2 513
e6289d63
MH		 514 if (mspi->len >= 4) {
515 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
516 } else {
517 tmp = mspi->len;
518 rx_data = 0;
519 while (tmp--) {
520 rx_data_8 = in_8((u8 *)&reg_base->receive);
521 rx_data |= (rx_data_8 << (tmp * 8));
522 }
523
524 rx_data <<= (4 - mspi->len) * 8;
525 }
526
527 mspi->len -= 4;
8b60d6c2
MH		 528
529 if (mspi->rx)
530 mspi->get_rx(rx_data, mspi);
531 }
532
533 if (!(events & SPIE_NF)) {
534 int ret;
535
536 /* spin until TX is done */
537 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
538 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
539 if (!ret) {
540 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
541 return;
542 }
543 }
544
545 /* Clear the events */
546 mpc8xxx_spi_write_reg(&reg_base->event, events);
547
548 mspi->count -= 1;
549 if (mspi->count) {
550 u32 word = mspi->get_tx(mspi);
551
552 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
553 } else {
554 complete(&mspi->done);
555 }
556}
557
558static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
559{
560 struct mpc8xxx_spi *mspi = context_data;
561 struct fsl_espi_reg *reg_base = mspi->reg_base;
562 irqreturn_t ret = IRQ_NONE;
563 u32 events;
564
565 /* Get interrupt events(tx/rx) */
566 events = mpc8xxx_spi_read_reg(&reg_base->event);
567 if (events)
568 ret = IRQ_HANDLED;
569
570 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
571
572 fsl_espi_cpu_irq(mspi, events);
573
574 return ret;
575}
576
577static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
578{
579 iounmap(mspi->reg_base);
580}
581
fd4a319b 582static struct spi_master * fsl_espi_probe(struct device *dev,
8b60d6c2
MH		 583 struct resource *mem, unsigned int irq)
584{
8074cf06 585 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 586 struct spi_master *master;
587 struct mpc8xxx_spi *mpc8xxx_spi;
588 struct fsl_espi_reg *reg_base;
589 u32 regval;
590 int i, ret = 0;
591
592 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
593 if (!master) {
594 ret = -ENOMEM;
595 goto err;
596 }
597
598 dev_set_drvdata(dev, master);
599
600 ret = mpc8xxx_spi_probe(dev, mem, irq);
601 if (ret)
602 goto err_probe;
603
24778be2 604 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
8b60d6c2
MH		 605 master->setup = fsl_espi_setup;
606
607 mpc8xxx_spi = spi_master_get_devdata(master);
608 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
609 mpc8xxx_spi->spi_remove = fsl_espi_remove;
610
611 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
612 if (!mpc8xxx_spi->reg_base) {
613 ret = -ENOMEM;
614 goto err_probe;
615 }
616
617 reg_base = mpc8xxx_spi->reg_base;
618
619 /* Register for SPI Interrupt */
620 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
621 0, "fsl_espi", mpc8xxx_spi);
622 if (ret)
623 goto free_irq;
624
625 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
626 mpc8xxx_spi->rx_shift = 16;
627 mpc8xxx_spi->tx_shift = 24;
628 }
629
630 /* SPI controller initializations */
631 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
632 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
633 mpc8xxx_spi_write_reg(&reg_base->command, 0);
634 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
635
636 /* Init eSPI CS mode register */
637 for (i = 0; i < pdata->max_chipselect; i++)
638 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
639
640 /* Enable SPI interface */
641 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
642
643 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
644
645 ret = spi_register_master(master);
646 if (ret < 0)
647 goto unreg_master;
648
649 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
650
651 return master;
652
653unreg_master:
654 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
655free_irq:
656 iounmap(mpc8xxx_spi->reg_base);
657err_probe:
658 spi_master_put(master);
659err:
660 return ERR_PTR(ret);
661}
662
663static int of_fsl_espi_get_chipselects(struct device *dev)
664{
665 struct device_node *np = dev->of_node;
8074cf06 666 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 667 const u32 *prop;
668 int len;
669
670 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
671 if (!prop || len < sizeof(*prop)) {
672 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
673 return -EINVAL;
674 }
675
676 pdata->max_chipselect = *prop;
677 pdata->cs_control = NULL;
678
679 return 0;
680}
681
fd4a319b 682static int of_fsl_espi_probe(struct platform_device *ofdev)
8b60d6c2
MH		 683{
684 struct device *dev = &ofdev->dev;
685 struct device_node *np = ofdev->dev.of_node;
686 struct spi_master *master;
687 struct resource mem;
f7578496 688 unsigned int irq;
8b60d6c2
MH		 689 int ret = -ENOMEM;
690
18d306d1 691 ret = of_mpc8xxx_spi_probe(ofdev);
8b60d6c2
MH		 692 if (ret)
693 return ret;
694
695 ret = of_fsl_espi_get_chipselects(dev);
696 if (ret)
697 goto err;
698
699 ret = of_address_to_resource(np, 0, &mem);
700 if (ret)
701 goto err;
702
f7578496 703 irq = irq_of_parse_and_map(np, 0);
7227cd18 704 if (!irq) {
8b60d6c2
MH		 705 ret = -EINVAL;
706 goto err;
707 }
708
f7578496 709 master = fsl_espi_probe(dev, &mem, irq);
8b60d6c2
MH		 710 if (IS_ERR(master)) {
711 ret = PTR_ERR(master);
712 goto err;
713 }
714
715 return 0;
716
717err:
718 return ret;
719}
720
fd4a319b 721static int of_fsl_espi_remove(struct platform_device *dev)
8b60d6c2
MH		 722{
723 return mpc8xxx_spi_remove(&dev->dev);
724}
725
714bb654
HZ		 726#ifdef CONFIG_PM_SLEEP
727static int of_fsl_espi_suspend(struct device *dev)
728{
729 struct spi_master *master = dev_get_drvdata(dev);
730 struct mpc8xxx_spi *mpc8xxx_spi;
731 struct fsl_espi_reg *reg_base;
732 u32 regval;
733 int ret;
734
735 mpc8xxx_spi = spi_master_get_devdata(master);
736 reg_base = mpc8xxx_spi->reg_base;
737
738 ret = spi_master_suspend(master);
739 if (ret) {
740 dev_warn(dev, "cannot suspend master\n");
741 return ret;
742 }
743
744 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
745 regval &= ~SPMODE_ENABLE;
746 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
747
748 return 0;
749}
750
751static int of_fsl_espi_resume(struct device *dev)
752{
753 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
754 struct spi_master *master = dev_get_drvdata(dev);
755 struct mpc8xxx_spi *mpc8xxx_spi;
756 struct fsl_espi_reg *reg_base;
757 u32 regval;
758 int i;
759
760 mpc8xxx_spi = spi_master_get_devdata(master);
761 reg_base = mpc8xxx_spi->reg_base;
762
763 /* SPI controller initializations */
764 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
765 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
766 mpc8xxx_spi_write_reg(&reg_base->command, 0);
767 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
768
769 /* Init eSPI CS mode register */
770 for (i = 0; i < pdata->max_chipselect; i++)
771 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
772
773 /* Enable SPI interface */
774 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
775
776 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
777
778 return spi_master_resume(master);
779}
780#endif /* CONFIG_PM_SLEEP */
781
782static const struct dev_pm_ops espi_pm = {
783 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
784};
785
8b60d6c2
MH		 786static const struct of_device_id of_fsl_espi_match[] = {
787 { .compatible = "fsl,mpc8536-espi" },
788 {}
789};
790MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
791
18d306d1 792static struct platform_driver fsl_espi_driver = {
8b60d6c2
MH		 793 .driver = {
794 .name = "fsl_espi",
795 .owner = THIS_MODULE,
796 .of_match_table = of_fsl_espi_match,
714bb654 797 .pm = &espi_pm,
8b60d6c2
MH		 798 },
799 .probe = of_fsl_espi_probe,
fd4a319b 800 .remove = of_fsl_espi_remove,
8b60d6c2 801};
940ab889 802module_platform_driver(fsl_espi_driver);
8b60d6c2
MH		 803
804MODULE_AUTHOR("Mingkai Hu");
805MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
806MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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