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spi: fsl-(e)spi: simplify cleanup code
[deliverable/linux.git] / drivers / spi / spi-fsl-espi.c
CommitLineData
8b60d6c2
MH		 1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
8b60d6c2 11#include <linux/delay.h>
a3108360 12#include <linux/err.h>
8b60d6c2 13#include <linux/fsl_devices.h>
a3108360
XL		 14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/module.h>
8b60d6c2
MH		 17#include <linux/mm.h>
18#include <linux/of.h>
5af50730
RH		 19#include <linux/of_address.h>
20#include <linux/of_irq.h>
8b60d6c2 21#include <linux/of_platform.h>
a3108360
XL		 22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
8b60d6c2
MH		 24#include <sysdev/fsl_soc.h>
25
ca632f55 26#include "spi-fsl-lib.h"
8b60d6c2
MH		 27
28/* eSPI Controller registers */
29struct fsl_espi_reg {
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38};
39
40struct fsl_espi_transfer {
41 const void *tx_buf;
42 void *rx_buf;
43 unsigned len;
44 unsigned n_tx;
45 unsigned n_rx;
46 unsigned actual_length;
47 int status;
48};
49
50/* eSPI Controller mode register definitions */
51#define SPMODE_ENABLE (1 << 31)
52#define SPMODE_LOOP (1 << 30)
53#define SPMODE_TXTHR(x) ((x) << 8)
54#define SPMODE_RXTHR(x) ((x) << 0)
55
56/* eSPI Controller CS mode register definitions */
57#define CSMODE_CI_INACTIVEHIGH (1 << 31)
58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59#define CSMODE_REV (1 << 29)
60#define CSMODE_DIV16 (1 << 28)
61#define CSMODE_PM(x) ((x) << 24)
62#define CSMODE_POL_1 (1 << 20)
63#define CSMODE_LEN(x) ((x) << 16)
64#define CSMODE_BEF(x) ((x) << 12)
65#define CSMODE_AFT(x) ((x) << 8)
66#define CSMODE_CG(x) ((x) << 3)
67
68/* Default mode/csmode for eSPI controller */
69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
72
73/* SPIE register values */
74#define SPIE_NE 0x00000200 /* Not empty */
75#define SPIE_NF 0x00000100 /* Not full */
76
77/* SPIM register values */
78#define SPIM_NE 0x00000200 /* Not empty */
79#define SPIM_NF 0x00000100 /* Not full */
80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
82
83/* SPCOM register values */
84#define SPCOM_CS(x) ((x) << 30)
85#define SPCOM_TRANLEN(x) ((x) << 0)
86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87
88static void fsl_espi_change_mode(struct spi_device *spi)
89{
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = &reg_base->mode;
95 u32 tmp;
96 unsigned long flags;
97
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
100
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
106
107 local_irq_restore(flags);
108}
109
110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
111{
112 u32 data;
113 u16 data_h;
114 u16 data_l;
115 const u32 *tx = mpc8xxx_spi->tx;
116
117 if (!tx)
118 return 0;
119
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
123 swab16s(&data_l);
124 swab16s(&data_h);
125 data = data_h | data_l;
126
127 mpc8xxx_spi->tx = tx;
128 return data;
129}
130
131static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
133{
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
136 u8 pm;
137 u32 hz = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139
140 if (t) {
141 bits_per_word = t->bits_per_word;
142 hz = t->speed_hz;
143 }
144
145 /* spi_transfer level calls that work per-word */
146 if (!bits_per_word)
147 bits_per_word = spi->bits_per_word;
148
8b60d6c2
MH		 149 if (!hz)
150 hz = spi->max_speed_hz;
151
152 cs->rx_shift = 0;
153 cs->tx_shift = 0;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
51faed69 158 } else {
8b60d6c2
MH		 159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
8b60d6c2
MH		 162 }
163
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
168
169 bits_per_word = bits_per_word - 1;
170
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
173
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
175
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
35faa55c 178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
8b60d6c2 179
87bf5ab8 180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
8b60d6c2 181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
87bf5ab8
SAS		 182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
183 if (pm > 33)
184 pm = 33;
8b60d6c2 185 } else {
35faa55c 186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
8b60d6c2
MH		 187 }
188 if (pm)
189 pm--;
87bf5ab8
SAS		 190 if (pm < 2)
191 pm = 2;
8b60d6c2
MH		 192
193 cs->hw_mode |= CSMODE_PM(pm);
194
195 fsl_espi_change_mode(spi);
196 return 0;
197}
198
199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
200 unsigned int len)
201{
202 u32 word;
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
204
205 mspi->count = len;
206
207 /* enable rx ints */
208 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
209
210 /* transmit word */
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
213
214 return 0;
215}
216
217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218{
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
8b60d6c2
MH		 222 int ret;
223
8b60d6c2
MH		 224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
226
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
229
16735d02 230 reinit_completion(&mpc8xxx_spi->done);
8b60d6c2
MH		 231
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
236 return -EINVAL;
237 }
238 mpc8xxx_spi_write_reg(&reg_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 if (ret)
243 return ret;
244
245 wait_for_completion(&mpc8xxx_spi->done);
246
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
249
250 return mpc8xxx_spi->count;
251}
252
0dd2c96f 253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
8b60d6c2 254{
0dd2c96f 255 if (cmd) {
8b60d6c2
MH		 256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
259 }
260}
261
0dd2c96f 262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
8b60d6c2 263{
0dd2c96f 264 if (cmd)
8b60d6c2
MH		 265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
266
267 return 0;
268}
269
270static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
272{
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
278 int status = 0;
279
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
282
283 first = list_first_entry(&m->transfers, struct spi_transfer,
284 transfer_list);
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
f6bd03a7
JN		 289 dev_err(mspi->dev,
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
8b60d6c2
MH		 291 return;
292 }
293
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
297 }
298
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
303
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
306 status = -EINVAL;
307
308 status = fsl_espi_setup_transfer(spi, t);
309 if (status < 0)
310 break;
311 }
312
313 if (t->len)
314 status = fsl_espi_bufs(spi, t);
315
316 if (status) {
317 status = -EMSGSIZE;
318 break;
319 }
320
321 if (t->delay_usecs)
322 udelay(t->delay_usecs);
323 }
324
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
327}
328
329static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
331{
332 struct spi_transfer *t;
333 u8 *local_buf;
334 int i = 0;
335 struct fsl_espi_transfer *espi_trans = trans;
336
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
338 if (!local_buf) {
339 espi_trans->status = -ENOMEM;
340 return;
341 }
342
343 list_for_each_entry(t, &m->transfers, transfer_list) {
344 if (t->tx_buf) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
346 i += t->len;
347 }
348 }
349
350 espi_trans->tx_buf = local_buf;
a2cb1be1 351 espi_trans->rx_buf = local_buf;
8b60d6c2
MH		 352 fsl_espi_do_trans(m, espi_trans);
353
354 espi_trans->actual_length = espi_trans->len;
355 kfree(local_buf);
356}
357
358static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
360{
361 struct fsl_espi_transfer *espi_trans = trans;
2000058e 362 unsigned int total_len = espi_trans->len;
8b60d6c2
MH		 363 struct spi_transfer *t;
364 u8 *local_buf;
365 u8 *rx_buf = rx_buff;
366 unsigned int trans_len;
367 unsigned int addr;
2000058e
JR		 368 unsigned int tx_only;
369 unsigned int rx_pos = 0;
370 unsigned int pos;
371 int i, loop;
8b60d6c2
MH		 372
373 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
374 if (!local_buf) {
375 espi_trans->status = -ENOMEM;
376 return;
377 }
378
2000058e
JR		 379 for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) {
380 trans_len = total_len - pos;
8b60d6c2
MH		 381
382 i = 0;
2000058e 383 tx_only = 0;
8b60d6c2
MH		 384 list_for_each_entry(t, &m->transfers, transfer_list) {
385 if (t->tx_buf) {
386 memcpy(local_buf + i, t->tx_buf, t->len);
387 i += t->len;
2000058e
JR		 388 if (!t->rx_buf)
389 tx_only += t->len;
8b60d6c2
MH		 390 }
391 }
392
2000058e
JR		 393 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */
394 if (loop > 0)
395 trans_len += tx_only;
396
397 if (trans_len > SPCOM_TRANLEN_MAX)
398 trans_len = SPCOM_TRANLEN_MAX;
399
400 /* Update device offset */
0dd2c96f
MH		 401 if (pos > 0) {
402 addr = fsl_espi_cmd2addr(local_buf);
2000058e 403 addr += rx_pos;
0dd2c96f
MH		 404 fsl_espi_addr2cmd(addr, local_buf);
405 }
8b60d6c2 406
2000058e 407 espi_trans->len = trans_len;
8b60d6c2 408 espi_trans->tx_buf = local_buf;
a2cb1be1 409 espi_trans->rx_buf = local_buf;
8b60d6c2
MH		 410 fsl_espi_do_trans(m, espi_trans);
411
2000058e
JR		 412 /* If there is at least one RX byte then copy it to rx_buf */
413 if (tx_only < SPCOM_TRANLEN_MAX)
414 memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only,
415 trans_len - tx_only);
416
417 rx_pos += trans_len - tx_only;
8b60d6c2
MH		 418
419 if (loop > 0)
2000058e 420 espi_trans->actual_length += espi_trans->len - tx_only;
8b60d6c2
MH		 421 else
422 espi_trans->actual_length += espi_trans->len;
423 }
424
425 kfree(local_buf);
426}
427
c592becb
HK		 428static int fsl_espi_do_one_msg(struct spi_master *master,
429 struct spi_message *m)
8b60d6c2
MH		 430{
431 struct spi_transfer *t;
432 u8 *rx_buf = NULL;
433 unsigned int n_tx = 0;
434 unsigned int n_rx = 0;
2000058e 435 unsigned int xfer_len = 0;
8b60d6c2
MH		 436 struct fsl_espi_transfer espi_trans;
437
438 list_for_each_entry(t, &m->transfers, transfer_list) {
439 if (t->tx_buf)
440 n_tx += t->len;
441 if (t->rx_buf) {
442 n_rx += t->len;
443 rx_buf = t->rx_buf;
444 }
2000058e
JR		 445 if ((t->tx_buf) || (t->rx_buf))
446 xfer_len += t->len;
8b60d6c2
MH		 447 }
448
449 espi_trans.n_tx = n_tx;
450 espi_trans.n_rx = n_rx;
2000058e 451 espi_trans.len = xfer_len;
8b60d6c2
MH		 452 espi_trans.actual_length = 0;
453 espi_trans.status = 0;
454
455 if (!rx_buf)
456 fsl_espi_cmd_trans(m, &espi_trans, NULL);
457 else
458 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
459
460 m->actual_length = espi_trans.actual_length;
461 m->status = espi_trans.status;
c592becb
HK		 462 spi_finalize_current_message(master);
463 return 0;
8b60d6c2
MH		 464}
465
466static int fsl_espi_setup(struct spi_device *spi)
467{
468 struct mpc8xxx_spi *mpc8xxx_spi;
469 struct fsl_espi_reg *reg_base;
470 int retval;
471 u32 hw_mode;
472 u32 loop_mode;
d9f26748 473 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
8b60d6c2
MH		 474
475 if (!spi->max_speed_hz)
476 return -EINVAL;
477
478 if (!cs) {
d9f26748 479 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
8b60d6c2
MH		 480 if (!cs)
481 return -ENOMEM;
d9f26748 482 spi_set_ctldata(spi, cs);
8b60d6c2
MH		 483 }
484
485 mpc8xxx_spi = spi_master_get_devdata(spi->master);
486 reg_base = mpc8xxx_spi->reg_base;
487
25985edc 488 hw_mode = cs->hw_mode; /* Save original settings */
8b60d6c2
MH		 489 cs->hw_mode = mpc8xxx_spi_read_reg(
490 &reg_base->csmode[spi->chip_select]);
491 /* mask out bits we are going to set */
492 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
493 | CSMODE_REV);
494
495 if (spi->mode & SPI_CPHA)
496 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
497 if (spi->mode & SPI_CPOL)
498 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
499 if (!(spi->mode & SPI_LSB_FIRST))
500 cs->hw_mode |= CSMODE_REV;
501
502 /* Handle the loop mode */
503 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
504 loop_mode &= ~SPMODE_LOOP;
505 if (spi->mode & SPI_LOOP)
506 loop_mode |= SPMODE_LOOP;
507 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
508
509 retval = fsl_espi_setup_transfer(spi, NULL);
510 if (retval < 0) {
511 cs->hw_mode = hw_mode; /* Restore settings */
512 return retval;
513 }
514 return 0;
515}
516
d9f26748
AL		 517static void fsl_espi_cleanup(struct spi_device *spi)
518{
519 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
520
521 kfree(cs);
522 spi_set_ctldata(spi, NULL);
523}
524
8b60d6c2
MH		 525void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
526{
527 struct fsl_espi_reg *reg_base = mspi->reg_base;
528
529 /* We need handle RX first */
530 if (events & SPIE_NE) {
e6289d63
MH		 531 u32 rx_data, tmp;
532 u8 rx_data_8;
8b60d6c2
MH		 533
534 /* Spin until RX is done */
535 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
536 cpu_relax();
537 events = mpc8xxx_spi_read_reg(&reg_base->event);
538 }
8b60d6c2 539
e6289d63
MH		 540 if (mspi->len >= 4) {
541 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
542 } else {
543 tmp = mspi->len;
544 rx_data = 0;
545 while (tmp--) {
546 rx_data_8 = in_8((u8 *)&reg_base->receive);
547 rx_data |= (rx_data_8 << (tmp * 8));
548 }
549
550 rx_data <<= (4 - mspi->len) * 8;
551 }
552
553 mspi->len -= 4;
8b60d6c2
MH		 554
555 if (mspi->rx)
556 mspi->get_rx(rx_data, mspi);
557 }
558
559 if (!(events & SPIE_NF)) {
560 int ret;
561
562 /* spin until TX is done */
563 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
7a0a1759 564 &reg_base->event)) & SPIE_NF), 1000, 0);
8b60d6c2
MH		 565 if (!ret) {
566 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
7a0a1759
JW		 567
568 /* Clear the SPIE bits */
569 mpc8xxx_spi_write_reg(&reg_base->event, events);
570 complete(&mspi->done);
8b60d6c2
MH		 571 return;
572 }
573 }
574
575 /* Clear the events */
576 mpc8xxx_spi_write_reg(&reg_base->event, events);
577
578 mspi->count -= 1;
579 if (mspi->count) {
580 u32 word = mspi->get_tx(mspi);
581
582 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
583 } else {
584 complete(&mspi->done);
585 }
586}
587
588static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
589{
590 struct mpc8xxx_spi *mspi = context_data;
591 struct fsl_espi_reg *reg_base = mspi->reg_base;
592 irqreturn_t ret = IRQ_NONE;
593 u32 events;
594
595 /* Get interrupt events(tx/rx) */
596 events = mpc8xxx_spi_read_reg(&reg_base->event);
597 if (events)
598 ret = IRQ_HANDLED;
599
600 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
601
602 fsl_espi_cpu_irq(mspi, events);
603
604 return ret;
605}
606
75506d0e
HK		 607static int fsl_espi_suspend(struct spi_master *master)
608{
609 struct mpc8xxx_spi *mpc8xxx_spi;
610 struct fsl_espi_reg *reg_base;
611 u32 regval;
612
613 mpc8xxx_spi = spi_master_get_devdata(master);
614 reg_base = mpc8xxx_spi->reg_base;
615
616 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
617 regval &= ~SPMODE_ENABLE;
618 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
619
620 return 0;
621}
622
623static int fsl_espi_resume(struct spi_master *master)
624{
625 struct mpc8xxx_spi *mpc8xxx_spi;
626 struct fsl_espi_reg *reg_base;
627 u32 regval;
628
629 mpc8xxx_spi = spi_master_get_devdata(master);
630 reg_base = mpc8xxx_spi->reg_base;
631
632 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
633 regval |= SPMODE_ENABLE;
634 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
635
636 return 0;
637}
638
fd4a319b 639static struct spi_master * fsl_espi_probe(struct device *dev,
8b60d6c2
MH		 640 struct resource *mem, unsigned int irq)
641{
8074cf06 642 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 643 struct spi_master *master;
644 struct mpc8xxx_spi *mpc8xxx_spi;
645 struct fsl_espi_reg *reg_base;
d0fb47a5
JW		 646 struct device_node *nc;
647 const __be32 *prop;
648 u32 regval, csmode;
649 int i, len, ret = 0;
8b60d6c2
MH		 650
651 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
652 if (!master) {
653 ret = -ENOMEM;
654 goto err;
655 }
656
657 dev_set_drvdata(dev, master);
658
c592becb 659 mpc8xxx_spi_probe(dev, mem, irq);
8b60d6c2 660
24778be2 661 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
8b60d6c2 662 master->setup = fsl_espi_setup;
d9f26748 663 master->cleanup = fsl_espi_cleanup;
c592becb 664 master->transfer_one_message = fsl_espi_do_one_msg;
75506d0e
HK		 665 master->prepare_transfer_hardware = fsl_espi_resume;
666 master->unprepare_transfer_hardware = fsl_espi_suspend;
8b60d6c2
MH		 667
668 mpc8xxx_spi = spi_master_get_devdata(master);
8b60d6c2 669
4178b6b1 670 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
8b60d6c2
MH		 671 if (!mpc8xxx_spi->reg_base) {
672 ret = -ENOMEM;
673 goto err_probe;
674 }
675
676 reg_base = mpc8xxx_spi->reg_base;
677
678 /* Register for SPI Interrupt */
4178b6b1 679 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
8b60d6c2
MH		 680 0, "fsl_espi", mpc8xxx_spi);
681 if (ret)
4178b6b1 682 goto err_probe;
8b60d6c2
MH		 683
684 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
685 mpc8xxx_spi->rx_shift = 16;
686 mpc8xxx_spi->tx_shift = 24;
687 }
688
689 /* SPI controller initializations */
690 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
691 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
692 mpc8xxx_spi_write_reg(&reg_base->command, 0);
693 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
694
695 /* Init eSPI CS mode register */
d0fb47a5
JW		 696 for_each_available_child_of_node(master->dev.of_node, nc) {
697 /* get chip select */
698 prop = of_get_property(nc, "reg", &len);
699 if (!prop || len < sizeof(*prop))
700 continue;
701 i = be32_to_cpup(prop);
702 if (i < 0 || i >= pdata->max_chipselect)
703 continue;
704
705 csmode = CSMODE_INIT_VAL;
706 /* check if CSBEF is set in device tree */
707 prop = of_get_property(nc, "fsl,csbef", &len);
708 if (prop && len >= sizeof(*prop)) {
709 csmode &= ~(CSMODE_BEF(0xf));
710 csmode |= CSMODE_BEF(be32_to_cpup(prop));
711 }
712 /* check if CSAFT is set in device tree */
713 prop = of_get_property(nc, "fsl,csaft", &len);
714 if (prop && len >= sizeof(*prop)) {
715 csmode &= ~(CSMODE_AFT(0xf));
716 csmode |= CSMODE_AFT(be32_to_cpup(prop));
717 }
718 mpc8xxx_spi_write_reg(&reg_base->csmode[i], csmode);
719
720 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
721 }
8b60d6c2
MH		 722
723 /* Enable SPI interface */
724 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
725
726 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
727
4178b6b1 728 ret = devm_spi_register_master(dev, master);
8b60d6c2 729 if (ret < 0)
4178b6b1 730 goto err_probe;
8b60d6c2
MH		 731
732 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
733
734 return master;
735
8b60d6c2
MH		 736err_probe:
737 spi_master_put(master);
738err:
739 return ERR_PTR(ret);
740}
741
742static int of_fsl_espi_get_chipselects(struct device *dev)
743{
744 struct device_node *np = dev->of_node;
8074cf06 745 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
8b60d6c2
MH		 746 const u32 *prop;
747 int len;
748
749 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
750 if (!prop || len < sizeof(*prop)) {
751 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
752 return -EINVAL;
753 }
754
755 pdata->max_chipselect = *prop;
756 pdata->cs_control = NULL;
757
758 return 0;
759}
760
fd4a319b 761static int of_fsl_espi_probe(struct platform_device *ofdev)
8b60d6c2
MH		 762{
763 struct device *dev = &ofdev->dev;
764 struct device_node *np = ofdev->dev.of_node;
765 struct spi_master *master;
766 struct resource mem;
f7578496 767 unsigned int irq;
8b60d6c2
MH		 768 int ret = -ENOMEM;
769
18d306d1 770 ret = of_mpc8xxx_spi_probe(ofdev);
8b60d6c2
MH		 771 if (ret)
772 return ret;
773
774 ret = of_fsl_espi_get_chipselects(dev);
775 if (ret)
776 goto err;
777
778 ret = of_address_to_resource(np, 0, &mem);
779 if (ret)
780 goto err;
781
f7578496 782 irq = irq_of_parse_and_map(np, 0);
7227cd18 783 if (!irq) {
8b60d6c2
MH		 784 ret = -EINVAL;
785 goto err;
786 }
787
f7578496 788 master = fsl_espi_probe(dev, &mem, irq);
8b60d6c2
MH		 789 if (IS_ERR(master)) {
790 ret = PTR_ERR(master);
791 goto err;
792 }
793
794 return 0;
795
796err:
797 return ret;
798}
799
714bb654
HZ		 800#ifdef CONFIG_PM_SLEEP
801static int of_fsl_espi_suspend(struct device *dev)
802{
803 struct spi_master *master = dev_get_drvdata(dev);
714bb654
HZ		 804 int ret;
805
714bb654
HZ		 806 ret = spi_master_suspend(master);
807 if (ret) {
808 dev_warn(dev, "cannot suspend master\n");
809 return ret;
810 }
811
75506d0e 812 return fsl_espi_suspend(master);
714bb654
HZ		 813}
814
815static int of_fsl_espi_resume(struct device *dev)
816{
817 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
818 struct spi_master *master = dev_get_drvdata(dev);
819 struct mpc8xxx_spi *mpc8xxx_spi;
820 struct fsl_espi_reg *reg_base;
821 u32 regval;
822 int i;
823
824 mpc8xxx_spi = spi_master_get_devdata(master);
825 reg_base = mpc8xxx_spi->reg_base;
826
827 /* SPI controller initializations */
828 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
829 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
830 mpc8xxx_spi_write_reg(&reg_base->command, 0);
831 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
832
833 /* Init eSPI CS mode register */
834 for (i = 0; i < pdata->max_chipselect; i++)
835 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
836
837 /* Enable SPI interface */
838 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
839
840 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
841
842 return spi_master_resume(master);
843}
844#endif /* CONFIG_PM_SLEEP */
845
846static const struct dev_pm_ops espi_pm = {
847 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
848};
849
8b60d6c2
MH		 850static const struct of_device_id of_fsl_espi_match[] = {
851 { .compatible = "fsl,mpc8536-espi" },
852 {}
853};
854MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
855
18d306d1 856static struct platform_driver fsl_espi_driver = {
8b60d6c2
MH		 857 .driver = {
858 .name = "fsl_espi",
8b60d6c2 859 .of_match_table = of_fsl_espi_match,
714bb654 860 .pm = &espi_pm,
8b60d6c2
MH		 861 },
862 .probe = of_fsl_espi_probe,
8b60d6c2 863};
940ab889 864module_platform_driver(fsl_espi_driver);
8b60d6c2
MH		 865
866MODULE_AUTHOR("Mingkai Hu");
867MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
868MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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