Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
b36ece83 | 2 | * Freescale SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 7 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 8 | * |
4c1fba44 AV |
9 | * CPM SPI and QE buffer descriptors mode support: |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
447b0c7b AL |
13 | * GRLIB support: |
14 | * Copyright (c) 2012 Aeroflex Gaisler AB. | |
15 | * Author: Andreas Larsson <andreas@gaisler.com> | |
16 | * | |
ccf06998 KG |
17 | * This program is free software; you can redistribute it and/or modify it |
18 | * under the terms of the GNU General Public License as published by the | |
19 | * Free Software Foundation; either version 2 of the License, or (at your | |
20 | * option) any later version. | |
21 | */ | |
22 | #include <linux/module.h> | |
ccf06998 KG |
23 | #include <linux/types.h> |
24 | #include <linux/kernel.h> | |
ccf06998 KG |
25 | #include <linux/interrupt.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/irq.h> | |
ccf06998 KG |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/spi/spi_bitbang.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/fsl_devices.h> | |
4c1fba44 AV |
32 | #include <linux/dma-mapping.h> |
33 | #include <linux/mm.h> | |
34 | #include <linux/mutex.h> | |
35b4b3c0 AV |
35 | #include <linux/of.h> |
36 | #include <linux/of_platform.h> | |
e8beacbb AL |
37 | #include <linux/of_address.h> |
38 | #include <linux/of_irq.h> | |
35b4b3c0 AV |
39 | #include <linux/gpio.h> |
40 | #include <linux/of_gpio.h> | |
ccf06998 | 41 | |
ca632f55 | 42 | #include "spi-fsl-lib.h" |
e8beacbb AL |
43 | #include "spi-fsl-cpm.h" |
44 | #include "spi-fsl-spi.h" | |
ccf06998 | 45 | |
c3f3e771 | 46 | #define TYPE_FSL 0 |
447b0c7b | 47 | #define TYPE_GRLIB 1 |
c3f3e771 AL |
48 | |
49 | struct fsl_spi_match_data { | |
50 | int type; | |
51 | }; | |
52 | ||
53 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { | |
54 | .type = TYPE_FSL, | |
55 | }; | |
56 | ||
447b0c7b AL |
57 | static struct fsl_spi_match_data of_fsl_spi_grlib_config = { |
58 | .type = TYPE_GRLIB, | |
59 | }; | |
60 | ||
c3f3e771 AL |
61 | static struct of_device_id of_fsl_spi_match[] = { |
62 | { | |
63 | .compatible = "fsl,spi", | |
64 | .data = &of_fsl_spi_fsl_config, | |
65 | }, | |
447b0c7b AL |
66 | { |
67 | .compatible = "aeroflexgaisler,spictrl", | |
68 | .data = &of_fsl_spi_grlib_config, | |
69 | }, | |
c3f3e771 AL |
70 | {} |
71 | }; | |
72 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); | |
73 | ||
74 | static int fsl_spi_get_type(struct device *dev) | |
75 | { | |
76 | const struct of_device_id *match; | |
77 | ||
78 | if (dev->of_node) { | |
79 | match = of_match_node(of_fsl_spi_match, dev->of_node); | |
80 | if (match && match->data) | |
81 | return ((struct fsl_spi_match_data *)match->data)->type; | |
82 | } | |
83 | return TYPE_FSL; | |
84 | } | |
85 | ||
b36ece83 | 86 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
87 | { |
88 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
89 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
90 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
91 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
92 | unsigned long flags; |
93 | ||
94 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
95 | return; | |
96 | ||
97 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
98 | local_irq_save(flags); | |
99 | ||
100 | /* Turn off SPI unit prior changing mode */ | |
101 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 102 | |
4c1fba44 AV |
103 | /* When in CPM mode, we need to reinit tx and rx. */ |
104 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 105 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 106 | } |
f9218c2a | 107 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
108 | local_irq_restore(flags); |
109 | } | |
110 | ||
b36ece83 | 111 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 112 | { |
575c5807 | 113 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 114 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 115 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 116 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 117 | |
5039a869 KE |
118 | pdata = spi->dev.parent->parent->platform_data; |
119 | ||
ccf06998 | 120 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
121 | if (pdata->cs_control) |
122 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
123 | } |
124 | ||
125 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
126 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
127 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
128 | mpc8xxx_spi->get_rx = cs->get_rx; | |
129 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 130 | |
b36ece83 | 131 | fsl_spi_change_mode(spi); |
a35c1710 | 132 | |
364fdbc0 AV |
133 | if (pdata->cs_control) |
134 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
135 | } |
136 | } | |
137 | ||
b48c4e3c AL |
138 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
139 | int bits_per_word, int msb_first) | |
140 | { | |
141 | *rx_shift = 0; | |
142 | *tx_shift = 0; | |
143 | if (msb_first) { | |
144 | if (bits_per_word <= 8) { | |
145 | *rx_shift = 16; | |
146 | *tx_shift = 24; | |
147 | } else if (bits_per_word <= 16) { | |
148 | *rx_shift = 16; | |
149 | *tx_shift = 16; | |
150 | } | |
151 | } else { | |
152 | if (bits_per_word <= 8) | |
153 | *rx_shift = 8; | |
154 | } | |
155 | } | |
156 | ||
447b0c7b AL |
157 | static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, |
158 | int bits_per_word, int msb_first) | |
159 | { | |
160 | *rx_shift = 0; | |
161 | *tx_shift = 0; | |
162 | if (bits_per_word <= 16) { | |
163 | if (msb_first) { | |
164 | *rx_shift = 16; /* LSB in bit 16 */ | |
165 | *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ | |
166 | } else { | |
167 | *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ | |
168 | } | |
169 | } | |
170 | } | |
171 | ||
b36ece83 MH |
172 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
173 | struct spi_device *spi, | |
174 | struct mpc8xxx_spi *mpc8xxx_spi, | |
175 | int bits_per_word) | |
ccf06998 | 176 | { |
c9bfcb31 JT |
177 | cs->rx_shift = 0; |
178 | cs->tx_shift = 0; | |
ccf06998 | 179 | if (bits_per_word <= 8) { |
575c5807 AV |
180 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
181 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 182 | } else if (bits_per_word <= 16) { |
575c5807 AV |
183 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
184 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 185 | } else if (bits_per_word <= 32) { |
575c5807 AV |
186 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
187 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
188 | } else |
189 | return -EINVAL; | |
190 | ||
b48c4e3c AL |
191 | if (mpc8xxx_spi->set_shifts) |
192 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
193 | bits_per_word, | |
194 | !(spi->mode & SPI_LSB_FIRST)); | |
195 | ||
575c5807 AV |
196 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
197 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
198 | mpc8xxx_spi->get_rx = cs->get_rx; | |
199 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 200 | |
0398fb70 JT |
201 | return bits_per_word; |
202 | } | |
203 | ||
b36ece83 MH |
204 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
205 | struct spi_device *spi, | |
206 | int bits_per_word) | |
0398fb70 JT |
207 | { |
208 | /* QE uses Little Endian for words > 8 | |
209 | * so transform all words > 8 into 8 bits | |
210 | * Unfortnatly that doesn't work for LSB so | |
211 | * reject these for now */ | |
212 | /* Note: 32 bits word, LSB works iff | |
213 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
214 | if (spi->mode & SPI_LSB_FIRST && | |
215 | bits_per_word > 8) | |
216 | return -EINVAL; | |
217 | if (bits_per_word > 8) | |
218 | return 8; /* pretend its 8 bits */ | |
219 | return bits_per_word; | |
220 | } | |
221 | ||
b36ece83 MH |
222 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
223 | struct spi_transfer *t) | |
0398fb70 JT |
224 | { |
225 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 226 | int bits_per_word = 0; |
0398fb70 | 227 | u8 pm; |
b36ece83 | 228 | u32 hz = 0; |
0398fb70 JT |
229 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
230 | ||
231 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
232 | ||
233 | if (t) { | |
234 | bits_per_word = t->bits_per_word; | |
235 | hz = t->speed_hz; | |
0398fb70 JT |
236 | } |
237 | ||
238 | /* spi_transfer level calls that work per-word */ | |
239 | if (!bits_per_word) | |
240 | bits_per_word = spi->bits_per_word; | |
241 | ||
0398fb70 JT |
242 | if (!hz) |
243 | hz = spi->max_speed_hz; | |
244 | ||
245 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
246 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
247 | mpc8xxx_spi, | |
248 | bits_per_word); | |
249 | else if (mpc8xxx_spi->flags & SPI_QE) | |
250 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
251 | bits_per_word); | |
252 | ||
253 | if (bits_per_word < 0) | |
254 | return bits_per_word; | |
255 | ||
ccf06998 KG |
256 | if (bits_per_word == 32) |
257 | bits_per_word = 0; | |
258 | else | |
259 | bits_per_word = bits_per_word - 1; | |
260 | ||
32421daa | 261 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
262 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
263 | | SPMODE_PM(0xF)); | |
264 | ||
265 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
266 | ||
575c5807 | 267 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 268 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 269 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
fd8a11e1 AV |
270 | |
271 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
272 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 273 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 274 | if (pm > 16) |
53604dbe | 275 | pm = 16; |
b36ece83 | 276 | } else { |
4f4517c4 | 277 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 278 | } |
a61f5345 CG |
279 | if (pm) |
280 | pm--; | |
281 | ||
282 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 283 | |
b36ece83 | 284 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
285 | return 0; |
286 | } | |
ccf06998 | 287 | |
b36ece83 | 288 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
289 | struct spi_transfer *t, unsigned int len) |
290 | { | |
291 | u32 word; | |
b36ece83 | 292 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
293 | |
294 | mspi->count = len; | |
295 | ||
296 | /* enable rx ints */ | |
b36ece83 | 297 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
298 | |
299 | /* transmit word */ | |
300 | word = mspi->get_tx(mspi); | |
b36ece83 | 301 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
b36ece83 | 306 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
307 | bool is_dma_mapped) |
308 | { | |
309 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 310 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
311 | unsigned int len = t->len; |
312 | u8 bits_per_word; | |
313 | int ret; | |
c9bfcb31 | 314 | |
b36ece83 | 315 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
316 | bits_per_word = spi->bits_per_word; |
317 | if (t->bits_per_word) | |
318 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 319 | |
aa77d96b PK |
320 | if (bits_per_word > 8) { |
321 | /* invalid length? */ | |
322 | if (len & 1) | |
323 | return -EINVAL; | |
c9bfcb31 | 324 | len /= 2; |
aa77d96b PK |
325 | } |
326 | if (bits_per_word > 16) { | |
327 | /* invalid length? */ | |
328 | if (len & 1) | |
329 | return -EINVAL; | |
c9bfcb31 | 330 | len /= 2; |
aa77d96b | 331 | } |
aa77d96b | 332 | |
4c1fba44 AV |
333 | mpc8xxx_spi->tx = t->tx_buf; |
334 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 335 | |
16735d02 | 336 | reinit_completion(&mpc8xxx_spi->done); |
c9bfcb31 | 337 | |
4c1fba44 | 338 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 339 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 340 | else |
b36ece83 | 341 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
342 | if (ret) |
343 | return ret; | |
c9bfcb31 | 344 | |
575c5807 | 345 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
346 | |
347 | /* disable rx ints */ | |
b36ece83 | 348 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 349 | |
4c1fba44 | 350 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 351 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 352 | |
575c5807 | 353 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
354 | } |
355 | ||
b36ece83 | 356 | static void fsl_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 357 | { |
b9b9af11 | 358 | struct spi_device *spi = m->spi; |
4302a596 | 359 | struct spi_transfer *t, *first; |
b9b9af11 AV |
360 | unsigned int cs_change; |
361 | const int nsecs = 50; | |
362 | int status; | |
363 | ||
4302a596 SR |
364 | /* Don't allow changes if CS is active */ |
365 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
366 | transfer_list); | |
b9b9af11 | 367 | list_for_each_entry(t, &m->transfers, transfer_list) { |
4302a596 SR |
368 | if ((first->bits_per_word != t->bits_per_word) || |
369 | (first->speed_hz != t->speed_hz)) { | |
b9b9af11 | 370 | status = -EINVAL; |
4302a596 SR |
371 | dev_err(&spi->dev, |
372 | "bits_per_word/speed_hz should be same for the same SPI transfer\n"); | |
373 | return; | |
374 | } | |
375 | } | |
b9b9af11 | 376 | |
4302a596 SR |
377 | cs_change = 1; |
378 | status = -EINVAL; | |
379 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
380 | if (t->bits_per_word || t->speed_hz) { | |
b9b9af11 | 381 | if (cs_change) |
b36ece83 | 382 | status = fsl_spi_setup_transfer(spi, t); |
b9b9af11 | 383 | if (status < 0) |
c9bfcb31 | 384 | break; |
b9b9af11 | 385 | } |
c9bfcb31 | 386 | |
b9b9af11 | 387 | if (cs_change) { |
b36ece83 | 388 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
389 | ndelay(nsecs); |
390 | } | |
391 | cs_change = t->cs_change; | |
392 | if (t->len) | |
b36ece83 | 393 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
394 | if (status) { |
395 | status = -EMSGSIZE; | |
396 | break; | |
c9bfcb31 | 397 | } |
b9b9af11 | 398 | m->actual_length += t->len; |
c9bfcb31 | 399 | |
b9b9af11 AV |
400 | if (t->delay_usecs) |
401 | udelay(t->delay_usecs); | |
c9bfcb31 | 402 | |
b9b9af11 | 403 | if (cs_change) { |
c9bfcb31 | 404 | ndelay(nsecs); |
b36ece83 | 405 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 406 | ndelay(nsecs); |
c9bfcb31 | 407 | } |
b9b9af11 AV |
408 | } |
409 | ||
410 | m->status = status; | |
0a6d3879 AL |
411 | if (m->complete) |
412 | m->complete(m->context); | |
b9b9af11 AV |
413 | |
414 | if (status || !cs_change) { | |
415 | ndelay(nsecs); | |
b36ece83 | 416 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
417 | } |
418 | ||
b36ece83 | 419 | fsl_spi_setup_transfer(spi, NULL); |
ccf06998 KG |
420 | } |
421 | ||
b36ece83 | 422 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 423 | { |
575c5807 | 424 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 425 | struct fsl_spi_reg *reg_base; |
ccf06998 | 426 | int retval; |
c9bfcb31 | 427 | u32 hw_mode; |
575c5807 | 428 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
429 | |
430 | if (!spi->max_speed_hz) | |
431 | return -EINVAL; | |
432 | ||
c9bfcb31 | 433 | if (!cs) { |
7a400543 | 434 | cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); |
c9bfcb31 JT |
435 | if (!cs) |
436 | return -ENOMEM; | |
437 | spi->controller_state = cs; | |
438 | } | |
575c5807 | 439 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 440 | |
b36ece83 MH |
441 | reg_base = mpc8xxx_spi->reg_base; |
442 | ||
88393161 | 443 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 444 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
445 | /* mask out bits we are going to set */ |
446 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
447 | | SPMODE_REV | SPMODE_LOOP); | |
448 | ||
449 | if (spi->mode & SPI_CPHA) | |
450 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
451 | if (spi->mode & SPI_CPOL) | |
452 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
453 | if (!(spi->mode & SPI_LSB_FIRST)) | |
454 | cs->hw_mode |= SPMODE_REV; | |
455 | if (spi->mode & SPI_LOOP) | |
456 | cs->hw_mode |= SPMODE_LOOP; | |
457 | ||
b36ece83 | 458 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
459 | if (retval < 0) { |
460 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 461 | return retval; |
c9bfcb31 | 462 | } |
f482cd0f | 463 | |
76a7498f AL |
464 | if (mpc8xxx_spi->type == TYPE_GRLIB) { |
465 | if (gpio_is_valid(spi->cs_gpio)) { | |
466 | int desel; | |
467 | ||
468 | retval = gpio_request(spi->cs_gpio, | |
469 | dev_name(&spi->dev)); | |
470 | if (retval) | |
471 | return retval; | |
472 | ||
473 | desel = !(spi->mode & SPI_CS_HIGH); | |
474 | retval = gpio_direction_output(spi->cs_gpio, desel); | |
475 | if (retval) { | |
476 | gpio_free(spi->cs_gpio); | |
477 | return retval; | |
478 | } | |
479 | } else if (spi->cs_gpio != -ENOENT) { | |
480 | if (spi->cs_gpio < 0) | |
481 | return spi->cs_gpio; | |
482 | return -EINVAL; | |
483 | } | |
484 | /* When spi->cs_gpio == -ENOENT, a hole in the phandle list | |
485 | * indicates to use native chipselect if present, or allow for | |
486 | * an always selected chip | |
487 | */ | |
488 | } | |
489 | ||
f482cd0f AL |
490 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ |
491 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
492 | ||
ccf06998 KG |
493 | return 0; |
494 | } | |
495 | ||
76a7498f AL |
496 | static void fsl_spi_cleanup(struct spi_device *spi) |
497 | { | |
498 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
499 | ||
500 | if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) | |
501 | gpio_free(spi->cs_gpio); | |
502 | } | |
503 | ||
b36ece83 | 504 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 505 | { |
b36ece83 MH |
506 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
507 | ||
4c1fba44 AV |
508 | /* We need handle RX first */ |
509 | if (events & SPIE_NE) { | |
b36ece83 | 510 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
511 | |
512 | if (mspi->rx) | |
513 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
514 | } |
515 | ||
4c1fba44 | 516 | if ((events & SPIE_NF) == 0) |
ccf06998 | 517 | /* spin until TX is done */ |
4c1fba44 | 518 | while (((events = |
b36ece83 | 519 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 520 | SPIE_NF) == 0) |
9effb959 | 521 | cpu_relax(); |
ccf06998 | 522 | |
4c1fba44 | 523 | /* Clear the events */ |
b36ece83 | 524 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
525 | |
526 | mspi->count -= 1; | |
527 | if (mspi->count) { | |
528 | u32 word = mspi->get_tx(mspi); | |
529 | ||
b36ece83 | 530 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 531 | } else { |
4c1fba44 | 532 | complete(&mspi->done); |
ccf06998 | 533 | } |
4c1fba44 | 534 | } |
ccf06998 | 535 | |
b36ece83 | 536 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
537 | { |
538 | struct mpc8xxx_spi *mspi = context_data; | |
539 | irqreturn_t ret = IRQ_NONE; | |
540 | u32 events; | |
b36ece83 | 541 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
542 | |
543 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 544 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
545 | if (events) |
546 | ret = IRQ_HANDLED; | |
547 | ||
548 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
549 | ||
550 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 551 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 552 | else |
b36ece83 | 553 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
554 | |
555 | return ret; | |
556 | } | |
4c1fba44 | 557 | |
b36ece83 | 558 | static void fsl_spi_remove(struct mpc8xxx_spi *mspi) |
87ec0e98 | 559 | { |
b36ece83 MH |
560 | iounmap(mspi->reg_base); |
561 | fsl_spi_cpm_free(mspi); | |
87ec0e98 AV |
562 | } |
563 | ||
447b0c7b AL |
564 | static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) |
565 | { | |
566 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
567 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; | |
568 | u32 slvsel; | |
569 | u16 cs = spi->chip_select; | |
570 | ||
76a7498f AL |
571 | if (gpio_is_valid(spi->cs_gpio)) { |
572 | gpio_set_value(spi->cs_gpio, on); | |
573 | } else if (cs < mpc8xxx_spi->native_chipselects) { | |
574 | slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); | |
575 | slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); | |
576 | mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); | |
577 | } | |
447b0c7b AL |
578 | } |
579 | ||
580 | static void fsl_spi_grlib_probe(struct device *dev) | |
581 | { | |
8074cf06 | 582 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
447b0c7b AL |
583 | struct spi_master *master = dev_get_drvdata(dev); |
584 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
585 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; | |
586 | int mbits; | |
587 | u32 capabilities; | |
588 | ||
589 | capabilities = mpc8xxx_spi_read_reg(®_base->cap); | |
590 | ||
591 | mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; | |
592 | mbits = SPCAP_MAXWLEN(capabilities); | |
593 | if (mbits) | |
594 | mpc8xxx_spi->max_bits_per_word = mbits + 1; | |
595 | ||
76a7498f | 596 | mpc8xxx_spi->native_chipselects = 0; |
447b0c7b | 597 | if (SPCAP_SSEN(capabilities)) { |
76a7498f | 598 | mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); |
447b0c7b AL |
599 | mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); |
600 | } | |
76a7498f | 601 | master->num_chipselect = mpc8xxx_spi->native_chipselects; |
447b0c7b AL |
602 | pdata->cs_control = fsl_spi_grlib_cs_control; |
603 | } | |
604 | ||
fd4a319b | 605 | static struct spi_master * fsl_spi_probe(struct device *dev, |
b36ece83 | 606 | struct resource *mem, unsigned int irq) |
ccf06998 | 607 | { |
8074cf06 | 608 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
ccf06998 | 609 | struct spi_master *master; |
575c5807 | 610 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 611 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
612 | u32 regval; |
613 | int ret = 0; | |
614 | ||
575c5807 | 615 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
616 | if (master == NULL) { |
617 | ret = -ENOMEM; | |
618 | goto err; | |
619 | } | |
620 | ||
35b4b3c0 | 621 | dev_set_drvdata(dev, master); |
ccf06998 | 622 | |
b36ece83 MH |
623 | ret = mpc8xxx_spi_probe(dev, mem, irq); |
624 | if (ret) | |
625 | goto err_probe; | |
e7db06b5 | 626 | |
b36ece83 | 627 | master->setup = fsl_spi_setup; |
76a7498f | 628 | master->cleanup = fsl_spi_cleanup; |
575c5807 AV |
629 | |
630 | mpc8xxx_spi = spi_master_get_devdata(master); | |
b36ece83 MH |
631 | mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; |
632 | mpc8xxx_spi->spi_remove = fsl_spi_remove; | |
8922a366 | 633 | mpc8xxx_spi->max_bits_per_word = 32; |
c3f3e771 | 634 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
575c5807 | 635 | |
b36ece83 | 636 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
637 | if (ret) |
638 | goto err_cpm_init; | |
639 | ||
447b0c7b AL |
640 | mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); |
641 | if (mpc8xxx_spi->reg_base == NULL) { | |
642 | ret = -ENOMEM; | |
643 | goto err_ioremap; | |
644 | } | |
645 | ||
646 | if (mpc8xxx_spi->type == TYPE_GRLIB) | |
647 | fsl_spi_grlib_probe(dev); | |
648 | ||
f734394d AL |
649 | master->bits_per_word_mask = |
650 | (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & | |
651 | SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); | |
652 | ||
b48c4e3c AL |
653 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
654 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
655 | ||
656 | if (mpc8xxx_spi->set_shifts) | |
657 | /* 8 bits per word and MSB first */ | |
658 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
659 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 660 | |
ccf06998 | 661 | /* Register for SPI Interrupt */ |
b36ece83 MH |
662 | ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, |
663 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
664 | |
665 | if (ret != 0) | |
b36ece83 | 666 | goto free_irq; |
ccf06998 | 667 | |
b36ece83 | 668 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
669 | |
670 | /* SPI controller initializations */ | |
b36ece83 MH |
671 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
672 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
673 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
674 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
675 | |
676 | /* Enable SPI interface */ | |
677 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
8922a366 AL |
678 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
679 | regval &= ~SPMODE_LEN(0xF); | |
680 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); | |
681 | } | |
87ec0e98 | 682 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
683 | regval |= SPMODE_OP; |
684 | ||
b36ece83 | 685 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 JT |
686 | |
687 | ret = spi_register_master(master); | |
688 | if (ret < 0) | |
689 | goto unreg_master; | |
ccf06998 | 690 | |
b36ece83 | 691 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 692 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 693 | |
35b4b3c0 | 694 | return master; |
ccf06998 | 695 | |
c9bfcb31 | 696 | unreg_master: |
575c5807 | 697 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
b36ece83 MH |
698 | free_irq: |
699 | iounmap(mpc8xxx_spi->reg_base); | |
4c1fba44 | 700 | err_ioremap: |
b36ece83 | 701 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 702 | err_cpm_init: |
b36ece83 | 703 | err_probe: |
ccf06998 | 704 | spi_master_put(master); |
ccf06998 | 705 | err: |
35b4b3c0 | 706 | return ERR_PTR(ret); |
ccf06998 KG |
707 | } |
708 | ||
b36ece83 | 709 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 710 | { |
067aa481 | 711 | struct device *dev = spi->dev.parent->parent; |
8074cf06 JH |
712 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
713 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
35b4b3c0 AV |
714 | u16 cs = spi->chip_select; |
715 | int gpio = pinfo->gpios[cs]; | |
716 | bool alow = pinfo->alow_flags[cs]; | |
717 | ||
718 | gpio_set_value(gpio, on ^ alow); | |
719 | } | |
720 | ||
b36ece83 | 721 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 722 | { |
61c7a080 | 723 | struct device_node *np = dev->of_node; |
8074cf06 | 724 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
575c5807 | 725 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
e80beb27 | 726 | int ngpios; |
35b4b3c0 AV |
727 | int i = 0; |
728 | int ret; | |
729 | ||
730 | ngpios = of_gpio_count(np); | |
e80beb27 | 731 | if (ngpios <= 0) { |
35b4b3c0 AV |
732 | /* |
733 | * SPI w/o chip-select line. One SPI device is still permitted | |
734 | * though. | |
735 | */ | |
736 | pdata->max_chipselect = 1; | |
737 | return 0; | |
738 | } | |
739 | ||
02141546 | 740 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
741 | if (!pinfo->gpios) |
742 | return -ENOMEM; | |
02141546 | 743 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 744 | |
02141546 | 745 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
746 | GFP_KERNEL); |
747 | if (!pinfo->alow_flags) { | |
748 | ret = -ENOMEM; | |
749 | goto err_alloc_flags; | |
750 | } | |
751 | ||
752 | for (; i < ngpios; i++) { | |
753 | int gpio; | |
754 | enum of_gpio_flags flags; | |
755 | ||
756 | gpio = of_get_gpio_flags(np, i, &flags); | |
757 | if (!gpio_is_valid(gpio)) { | |
758 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 759 | ret = gpio; |
35b4b3c0 AV |
760 | goto err_loop; |
761 | } | |
762 | ||
763 | ret = gpio_request(gpio, dev_name(dev)); | |
764 | if (ret) { | |
765 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
766 | goto err_loop; | |
767 | } | |
768 | ||
769 | pinfo->gpios[i] = gpio; | |
770 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
771 | ||
772 | ret = gpio_direction_output(pinfo->gpios[i], | |
773 | pinfo->alow_flags[i]); | |
774 | if (ret) { | |
775 | dev_err(dev, "can't set output direction for gpio " | |
776 | "#%d: %d\n", i, ret); | |
777 | goto err_loop; | |
778 | } | |
779 | } | |
780 | ||
781 | pdata->max_chipselect = ngpios; | |
b36ece83 | 782 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
783 | |
784 | return 0; | |
785 | ||
786 | err_loop: | |
787 | while (i >= 0) { | |
788 | if (gpio_is_valid(pinfo->gpios[i])) | |
789 | gpio_free(pinfo->gpios[i]); | |
790 | i--; | |
791 | } | |
792 | ||
793 | kfree(pinfo->alow_flags); | |
794 | pinfo->alow_flags = NULL; | |
795 | err_alloc_flags: | |
796 | kfree(pinfo->gpios); | |
797 | pinfo->gpios = NULL; | |
798 | return ret; | |
799 | } | |
800 | ||
b36ece83 | 801 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 | 802 | { |
8074cf06 | 803 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
575c5807 | 804 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
805 | int i; |
806 | ||
807 | if (!pinfo->gpios) | |
808 | return 0; | |
809 | ||
810 | for (i = 0; i < pdata->max_chipselect; i++) { | |
811 | if (gpio_is_valid(pinfo->gpios[i])) | |
812 | gpio_free(pinfo->gpios[i]); | |
813 | } | |
814 | ||
815 | kfree(pinfo->gpios); | |
816 | kfree(pinfo->alow_flags); | |
817 | return 0; | |
818 | } | |
819 | ||
fd4a319b | 820 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
821 | { |
822 | struct device *dev = &ofdev->dev; | |
61c7a080 | 823 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
824 | struct spi_master *master; |
825 | struct resource mem; | |
447b0c7b | 826 | int irq, type; |
35b4b3c0 AV |
827 | int ret = -ENOMEM; |
828 | ||
18d306d1 | 829 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
830 | if (ret) |
831 | return ret; | |
35b4b3c0 | 832 | |
447b0c7b AL |
833 | type = fsl_spi_get_type(&ofdev->dev); |
834 | if (type == TYPE_FSL) { | |
835 | ret = of_fsl_spi_get_chipselects(dev); | |
836 | if (ret) | |
837 | goto err; | |
838 | } | |
35b4b3c0 AV |
839 | |
840 | ret = of_address_to_resource(np, 0, &mem); | |
841 | if (ret) | |
842 | goto err; | |
843 | ||
e8beacbb AL |
844 | irq = irq_of_parse_and_map(np, 0); |
845 | if (!irq) { | |
35b4b3c0 AV |
846 | ret = -EINVAL; |
847 | goto err; | |
848 | } | |
849 | ||
e8beacbb | 850 | master = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 AV |
851 | if (IS_ERR(master)) { |
852 | ret = PTR_ERR(master); | |
853 | goto err; | |
854 | } | |
855 | ||
35b4b3c0 AV |
856 | return 0; |
857 | ||
858 | err: | |
447b0c7b AL |
859 | if (type == TYPE_FSL) |
860 | of_fsl_spi_free_chipselects(dev); | |
35b4b3c0 AV |
861 | return ret; |
862 | } | |
863 | ||
fd4a319b | 864 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 | 865 | { |
24b5a82c | 866 | struct spi_master *master = platform_get_drvdata(ofdev); |
447b0c7b | 867 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
35b4b3c0 AV |
868 | int ret; |
869 | ||
575c5807 | 870 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
871 | if (ret) |
872 | return ret; | |
447b0c7b AL |
873 | if (mpc8xxx_spi->type == TYPE_FSL) |
874 | of_fsl_spi_free_chipselects(&ofdev->dev); | |
35b4b3c0 AV |
875 | return 0; |
876 | } | |
877 | ||
18d306d1 | 878 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 879 | .driver = { |
b36ece83 | 880 | .name = "fsl_spi", |
4018294b | 881 | .owner = THIS_MODULE, |
b36ece83 | 882 | .of_match_table = of_fsl_spi_match, |
4018294b | 883 | }, |
b36ece83 | 884 | .probe = of_fsl_spi_probe, |
fd4a319b | 885 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
886 | }; |
887 | ||
888 | #ifdef CONFIG_MPC832x_RDB | |
889 | /* | |
b36ece83 | 890 | * XXX XXX XXX |
35b4b3c0 AV |
891 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
892 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
893 | * tree can work with OpenFirmware driver. But for now we support old trees | |
894 | * as well. | |
895 | */ | |
fd4a319b | 896 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
897 | { |
898 | struct resource *mem; | |
e9a172f0 | 899 | int irq; |
35b4b3c0 AV |
900 | struct spi_master *master; |
901 | ||
8074cf06 | 902 | if (!dev_get_platdata(&pdev->dev)) |
35b4b3c0 AV |
903 | return -EINVAL; |
904 | ||
905 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
906 | if (!mem) | |
907 | return -EINVAL; | |
908 | ||
909 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 910 | if (irq <= 0) |
35b4b3c0 AV |
911 | return -EINVAL; |
912 | ||
b36ece83 | 913 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
8c6ffba0 | 914 | return PTR_ERR_OR_ZERO(master); |
35b4b3c0 AV |
915 | } |
916 | ||
fd4a319b | 917 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 918 | { |
575c5807 | 919 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
920 | } |
921 | ||
575c5807 AV |
922 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
923 | static struct platform_driver mpc8xxx_spi_driver = { | |
924 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 925 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 926 | .driver = { |
575c5807 | 927 | .name = "mpc8xxx_spi", |
7e38c3c4 | 928 | .owner = THIS_MODULE, |
ccf06998 KG |
929 | }, |
930 | }; | |
931 | ||
35b4b3c0 AV |
932 | static bool legacy_driver_failed; |
933 | ||
934 | static void __init legacy_driver_register(void) | |
935 | { | |
575c5807 | 936 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
937 | } |
938 | ||
939 | static void __exit legacy_driver_unregister(void) | |
940 | { | |
941 | if (legacy_driver_failed) | |
942 | return; | |
575c5807 | 943 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
944 | } |
945 | #else | |
946 | static void __init legacy_driver_register(void) {} | |
947 | static void __exit legacy_driver_unregister(void) {} | |
948 | #endif /* CONFIG_MPC832x_RDB */ | |
949 | ||
b36ece83 | 950 | static int __init fsl_spi_init(void) |
ccf06998 | 951 | { |
35b4b3c0 | 952 | legacy_driver_register(); |
18d306d1 | 953 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 954 | } |
b36ece83 | 955 | module_init(fsl_spi_init); |
ccf06998 | 956 | |
b36ece83 | 957 | static void __exit fsl_spi_exit(void) |
ccf06998 | 958 | { |
18d306d1 | 959 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 960 | legacy_driver_unregister(); |
ccf06998 | 961 | } |
b36ece83 | 962 | module_exit(fsl_spi_exit); |
ccf06998 KG |
963 | |
964 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 965 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 966 | MODULE_LICENSE("GPL"); |