Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
b36ece83 | 2 | * Freescale SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 7 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 8 | * |
4c1fba44 AV |
9 | * CPM SPI and QE buffer descriptors mode support: |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
ccf06998 KG |
13 | * This program is free software; you can redistribute it and/or modify it |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #include <linux/module.h> | |
ccf06998 KG |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
ccf06998 KG |
21 | #include <linux/interrupt.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/irq.h> | |
ccf06998 KG |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/spi_bitbang.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/fsl_devices.h> | |
4c1fba44 AV |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/mm.h> | |
30 | #include <linux/mutex.h> | |
35b4b3c0 AV |
31 | #include <linux/of.h> |
32 | #include <linux/of_platform.h> | |
e8beacbb AL |
33 | #include <linux/of_address.h> |
34 | #include <linux/of_irq.h> | |
35b4b3c0 AV |
35 | #include <linux/gpio.h> |
36 | #include <linux/of_gpio.h> | |
ccf06998 | 37 | |
ca632f55 | 38 | #include "spi-fsl-lib.h" |
e8beacbb AL |
39 | #include "spi-fsl-cpm.h" |
40 | #include "spi-fsl-spi.h" | |
ccf06998 | 41 | |
c3f3e771 AL |
42 | #define TYPE_FSL 0 |
43 | ||
44 | struct fsl_spi_match_data { | |
45 | int type; | |
46 | }; | |
47 | ||
48 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { | |
49 | .type = TYPE_FSL, | |
50 | }; | |
51 | ||
52 | static struct of_device_id of_fsl_spi_match[] = { | |
53 | { | |
54 | .compatible = "fsl,spi", | |
55 | .data = &of_fsl_spi_fsl_config, | |
56 | }, | |
57 | {} | |
58 | }; | |
59 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); | |
60 | ||
61 | static int fsl_spi_get_type(struct device *dev) | |
62 | { | |
63 | const struct of_device_id *match; | |
64 | ||
65 | if (dev->of_node) { | |
66 | match = of_match_node(of_fsl_spi_match, dev->of_node); | |
67 | if (match && match->data) | |
68 | return ((struct fsl_spi_match_data *)match->data)->type; | |
69 | } | |
70 | return TYPE_FSL; | |
71 | } | |
72 | ||
b36ece83 | 73 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
74 | { |
75 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
76 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
77 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
78 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
79 | unsigned long flags; |
80 | ||
81 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
82 | return; | |
83 | ||
84 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
85 | local_irq_save(flags); | |
86 | ||
87 | /* Turn off SPI unit prior changing mode */ | |
88 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 89 | |
4c1fba44 AV |
90 | /* When in CPM mode, we need to reinit tx and rx. */ |
91 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 92 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 93 | } |
f9218c2a | 94 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
95 | local_irq_restore(flags); |
96 | } | |
97 | ||
b36ece83 | 98 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 99 | { |
575c5807 | 100 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 101 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 102 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 103 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 104 | |
5039a869 KE |
105 | pdata = spi->dev.parent->parent->platform_data; |
106 | ||
ccf06998 | 107 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
108 | if (pdata->cs_control) |
109 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
110 | } |
111 | ||
112 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
113 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
114 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
115 | mpc8xxx_spi->get_rx = cs->get_rx; | |
116 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 117 | |
b36ece83 | 118 | fsl_spi_change_mode(spi); |
a35c1710 | 119 | |
364fdbc0 AV |
120 | if (pdata->cs_control) |
121 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
122 | } |
123 | } | |
124 | ||
b48c4e3c AL |
125 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
126 | int bits_per_word, int msb_first) | |
127 | { | |
128 | *rx_shift = 0; | |
129 | *tx_shift = 0; | |
130 | if (msb_first) { | |
131 | if (bits_per_word <= 8) { | |
132 | *rx_shift = 16; | |
133 | *tx_shift = 24; | |
134 | } else if (bits_per_word <= 16) { | |
135 | *rx_shift = 16; | |
136 | *tx_shift = 16; | |
137 | } | |
138 | } else { | |
139 | if (bits_per_word <= 8) | |
140 | *rx_shift = 8; | |
141 | } | |
142 | } | |
143 | ||
b36ece83 MH |
144 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
145 | struct spi_device *spi, | |
146 | struct mpc8xxx_spi *mpc8xxx_spi, | |
147 | int bits_per_word) | |
ccf06998 | 148 | { |
c9bfcb31 JT |
149 | cs->rx_shift = 0; |
150 | cs->tx_shift = 0; | |
ccf06998 | 151 | if (bits_per_word <= 8) { |
575c5807 AV |
152 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
153 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 154 | } else if (bits_per_word <= 16) { |
575c5807 AV |
155 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
156 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 157 | } else if (bits_per_word <= 32) { |
575c5807 AV |
158 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
159 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
160 | } else |
161 | return -EINVAL; | |
162 | ||
b48c4e3c AL |
163 | if (mpc8xxx_spi->set_shifts) |
164 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
165 | bits_per_word, | |
166 | !(spi->mode & SPI_LSB_FIRST)); | |
167 | ||
575c5807 AV |
168 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
169 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
170 | mpc8xxx_spi->get_rx = cs->get_rx; | |
171 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 172 | |
0398fb70 JT |
173 | return bits_per_word; |
174 | } | |
175 | ||
b36ece83 MH |
176 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
177 | struct spi_device *spi, | |
178 | int bits_per_word) | |
0398fb70 JT |
179 | { |
180 | /* QE uses Little Endian for words > 8 | |
181 | * so transform all words > 8 into 8 bits | |
182 | * Unfortnatly that doesn't work for LSB so | |
183 | * reject these for now */ | |
184 | /* Note: 32 bits word, LSB works iff | |
185 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
186 | if (spi->mode & SPI_LSB_FIRST && | |
187 | bits_per_word > 8) | |
188 | return -EINVAL; | |
189 | if (bits_per_word > 8) | |
190 | return 8; /* pretend its 8 bits */ | |
191 | return bits_per_word; | |
192 | } | |
193 | ||
b36ece83 MH |
194 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
195 | struct spi_transfer *t) | |
0398fb70 JT |
196 | { |
197 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 198 | int bits_per_word = 0; |
0398fb70 | 199 | u8 pm; |
b36ece83 | 200 | u32 hz = 0; |
0398fb70 JT |
201 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
202 | ||
203 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
204 | ||
205 | if (t) { | |
206 | bits_per_word = t->bits_per_word; | |
207 | hz = t->speed_hz; | |
0398fb70 JT |
208 | } |
209 | ||
210 | /* spi_transfer level calls that work per-word */ | |
211 | if (!bits_per_word) | |
212 | bits_per_word = spi->bits_per_word; | |
213 | ||
214 | /* Make sure its a bit width we support [4..16, 32] */ | |
215 | if ((bits_per_word < 4) | |
8922a366 AL |
216 | || ((bits_per_word > 16) && (bits_per_word != 32)) |
217 | || (bits_per_word > mpc8xxx_spi->max_bits_per_word)) | |
0398fb70 JT |
218 | return -EINVAL; |
219 | ||
220 | if (!hz) | |
221 | hz = spi->max_speed_hz; | |
222 | ||
223 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
224 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
225 | mpc8xxx_spi, | |
226 | bits_per_word); | |
227 | else if (mpc8xxx_spi->flags & SPI_QE) | |
228 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
229 | bits_per_word); | |
230 | ||
231 | if (bits_per_word < 0) | |
232 | return bits_per_word; | |
233 | ||
ccf06998 KG |
234 | if (bits_per_word == 32) |
235 | bits_per_word = 0; | |
236 | else | |
237 | bits_per_word = bits_per_word - 1; | |
238 | ||
32421daa | 239 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
240 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
241 | | SPMODE_PM(0xF)); | |
242 | ||
243 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
244 | ||
575c5807 | 245 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 246 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 247 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
fd8a11e1 AV |
248 | |
249 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
250 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 251 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 252 | if (pm > 16) |
53604dbe | 253 | pm = 16; |
b36ece83 | 254 | } else { |
4f4517c4 | 255 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 256 | } |
a61f5345 CG |
257 | if (pm) |
258 | pm--; | |
259 | ||
260 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 261 | |
b36ece83 | 262 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
263 | return 0; |
264 | } | |
ccf06998 | 265 | |
b36ece83 | 266 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
267 | struct spi_transfer *t, unsigned int len) |
268 | { | |
269 | u32 word; | |
b36ece83 | 270 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
271 | |
272 | mspi->count = len; | |
273 | ||
274 | /* enable rx ints */ | |
b36ece83 | 275 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
276 | |
277 | /* transmit word */ | |
278 | word = mspi->get_tx(mspi); | |
b36ece83 | 279 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
b36ece83 | 284 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
285 | bool is_dma_mapped) |
286 | { | |
287 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 288 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
289 | unsigned int len = t->len; |
290 | u8 bits_per_word; | |
291 | int ret; | |
c9bfcb31 | 292 | |
b36ece83 | 293 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
294 | bits_per_word = spi->bits_per_word; |
295 | if (t->bits_per_word) | |
296 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 297 | |
aa77d96b PK |
298 | if (bits_per_word > 8) { |
299 | /* invalid length? */ | |
300 | if (len & 1) | |
301 | return -EINVAL; | |
c9bfcb31 | 302 | len /= 2; |
aa77d96b PK |
303 | } |
304 | if (bits_per_word > 16) { | |
305 | /* invalid length? */ | |
306 | if (len & 1) | |
307 | return -EINVAL; | |
c9bfcb31 | 308 | len /= 2; |
aa77d96b | 309 | } |
aa77d96b | 310 | |
4c1fba44 AV |
311 | mpc8xxx_spi->tx = t->tx_buf; |
312 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 313 | |
4c1fba44 | 314 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 | 315 | |
4c1fba44 | 316 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 317 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 318 | else |
b36ece83 | 319 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
320 | if (ret) |
321 | return ret; | |
c9bfcb31 | 322 | |
575c5807 | 323 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
324 | |
325 | /* disable rx ints */ | |
b36ece83 | 326 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 327 | |
4c1fba44 | 328 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 329 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 330 | |
575c5807 | 331 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
332 | } |
333 | ||
b36ece83 | 334 | static void fsl_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 335 | { |
b9b9af11 AV |
336 | struct spi_device *spi = m->spi; |
337 | struct spi_transfer *t; | |
338 | unsigned int cs_change; | |
339 | const int nsecs = 50; | |
340 | int status; | |
341 | ||
342 | cs_change = 1; | |
343 | status = 0; | |
344 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
345 | if (t->bits_per_word || t->speed_hz) { | |
346 | /* Don't allow changes if CS is active */ | |
347 | status = -EINVAL; | |
348 | ||
349 | if (cs_change) | |
b36ece83 | 350 | status = fsl_spi_setup_transfer(spi, t); |
b9b9af11 | 351 | if (status < 0) |
c9bfcb31 | 352 | break; |
b9b9af11 | 353 | } |
c9bfcb31 | 354 | |
b9b9af11 | 355 | if (cs_change) { |
b36ece83 | 356 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
357 | ndelay(nsecs); |
358 | } | |
359 | cs_change = t->cs_change; | |
360 | if (t->len) | |
b36ece83 | 361 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
362 | if (status) { |
363 | status = -EMSGSIZE; | |
364 | break; | |
c9bfcb31 | 365 | } |
b9b9af11 | 366 | m->actual_length += t->len; |
c9bfcb31 | 367 | |
b9b9af11 AV |
368 | if (t->delay_usecs) |
369 | udelay(t->delay_usecs); | |
c9bfcb31 | 370 | |
b9b9af11 | 371 | if (cs_change) { |
c9bfcb31 | 372 | ndelay(nsecs); |
b36ece83 | 373 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 374 | ndelay(nsecs); |
c9bfcb31 | 375 | } |
b9b9af11 AV |
376 | } |
377 | ||
378 | m->status = status; | |
379 | m->complete(m->context); | |
380 | ||
381 | if (status || !cs_change) { | |
382 | ndelay(nsecs); | |
b36ece83 | 383 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
384 | } |
385 | ||
b36ece83 | 386 | fsl_spi_setup_transfer(spi, NULL); |
ccf06998 KG |
387 | } |
388 | ||
b36ece83 | 389 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 390 | { |
575c5807 | 391 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 392 | struct fsl_spi_reg *reg_base; |
ccf06998 | 393 | int retval; |
c9bfcb31 | 394 | u32 hw_mode; |
575c5807 | 395 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
396 | |
397 | if (!spi->max_speed_hz) | |
398 | return -EINVAL; | |
399 | ||
c9bfcb31 JT |
400 | if (!cs) { |
401 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
402 | if (!cs) | |
403 | return -ENOMEM; | |
404 | spi->controller_state = cs; | |
405 | } | |
575c5807 | 406 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 407 | |
b36ece83 MH |
408 | reg_base = mpc8xxx_spi->reg_base; |
409 | ||
88393161 | 410 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 411 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
412 | /* mask out bits we are going to set */ |
413 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
414 | | SPMODE_REV | SPMODE_LOOP); | |
415 | ||
416 | if (spi->mode & SPI_CPHA) | |
417 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
418 | if (spi->mode & SPI_CPOL) | |
419 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
420 | if (!(spi->mode & SPI_LSB_FIRST)) | |
421 | cs->hw_mode |= SPMODE_REV; | |
422 | if (spi->mode & SPI_LOOP) | |
423 | cs->hw_mode |= SPMODE_LOOP; | |
424 | ||
b36ece83 | 425 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
426 | if (retval < 0) { |
427 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 428 | return retval; |
c9bfcb31 | 429 | } |
f482cd0f AL |
430 | |
431 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ | |
432 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
433 | ||
ccf06998 KG |
434 | return 0; |
435 | } | |
436 | ||
b36ece83 | 437 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 438 | { |
b36ece83 MH |
439 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
440 | ||
4c1fba44 AV |
441 | /* We need handle RX first */ |
442 | if (events & SPIE_NE) { | |
b36ece83 | 443 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
444 | |
445 | if (mspi->rx) | |
446 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
447 | } |
448 | ||
4c1fba44 | 449 | if ((events & SPIE_NF) == 0) |
ccf06998 | 450 | /* spin until TX is done */ |
4c1fba44 | 451 | while (((events = |
b36ece83 | 452 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 453 | SPIE_NF) == 0) |
9effb959 | 454 | cpu_relax(); |
ccf06998 | 455 | |
4c1fba44 | 456 | /* Clear the events */ |
b36ece83 | 457 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
458 | |
459 | mspi->count -= 1; | |
460 | if (mspi->count) { | |
461 | u32 word = mspi->get_tx(mspi); | |
462 | ||
b36ece83 | 463 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 464 | } else { |
4c1fba44 | 465 | complete(&mspi->done); |
ccf06998 | 466 | } |
4c1fba44 | 467 | } |
ccf06998 | 468 | |
b36ece83 | 469 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
470 | { |
471 | struct mpc8xxx_spi *mspi = context_data; | |
472 | irqreturn_t ret = IRQ_NONE; | |
473 | u32 events; | |
b36ece83 | 474 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
475 | |
476 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 477 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
478 | if (events) |
479 | ret = IRQ_HANDLED; | |
480 | ||
481 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
482 | ||
483 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 484 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 485 | else |
b36ece83 | 486 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
487 | |
488 | return ret; | |
489 | } | |
4c1fba44 | 490 | |
b36ece83 | 491 | static void fsl_spi_remove(struct mpc8xxx_spi *mspi) |
87ec0e98 | 492 | { |
b36ece83 MH |
493 | iounmap(mspi->reg_base); |
494 | fsl_spi_cpm_free(mspi); | |
87ec0e98 AV |
495 | } |
496 | ||
fd4a319b | 497 | static struct spi_master * fsl_spi_probe(struct device *dev, |
b36ece83 | 498 | struct resource *mem, unsigned int irq) |
ccf06998 | 499 | { |
35b4b3c0 | 500 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 501 | struct spi_master *master; |
575c5807 | 502 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 503 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
504 | u32 regval; |
505 | int ret = 0; | |
506 | ||
575c5807 | 507 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
508 | if (master == NULL) { |
509 | ret = -ENOMEM; | |
510 | goto err; | |
511 | } | |
512 | ||
35b4b3c0 | 513 | dev_set_drvdata(dev, master); |
ccf06998 | 514 | |
b36ece83 MH |
515 | ret = mpc8xxx_spi_probe(dev, mem, irq); |
516 | if (ret) | |
517 | goto err_probe; | |
e7db06b5 | 518 | |
b36ece83 | 519 | master->setup = fsl_spi_setup; |
575c5807 AV |
520 | |
521 | mpc8xxx_spi = spi_master_get_devdata(master); | |
b36ece83 MH |
522 | mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; |
523 | mpc8xxx_spi->spi_remove = fsl_spi_remove; | |
8922a366 | 524 | mpc8xxx_spi->max_bits_per_word = 32; |
c3f3e771 | 525 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
575c5807 | 526 | |
b36ece83 | 527 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
528 | if (ret) |
529 | goto err_cpm_init; | |
530 | ||
b48c4e3c AL |
531 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
532 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
533 | ||
534 | if (mpc8xxx_spi->set_shifts) | |
535 | /* 8 bits per word and MSB first */ | |
536 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
537 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 538 | |
b36ece83 MH |
539 | mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); |
540 | if (mpc8xxx_spi->reg_base == NULL) { | |
ccf06998 | 541 | ret = -ENOMEM; |
4c1fba44 | 542 | goto err_ioremap; |
ccf06998 KG |
543 | } |
544 | ||
ccf06998 | 545 | /* Register for SPI Interrupt */ |
b36ece83 MH |
546 | ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, |
547 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
548 | |
549 | if (ret != 0) | |
b36ece83 | 550 | goto free_irq; |
ccf06998 | 551 | |
b36ece83 | 552 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
553 | |
554 | /* SPI controller initializations */ | |
b36ece83 MH |
555 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
556 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
557 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
558 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
559 | |
560 | /* Enable SPI interface */ | |
561 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
8922a366 AL |
562 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
563 | regval &= ~SPMODE_LEN(0xF); | |
564 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); | |
565 | } | |
87ec0e98 | 566 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
567 | regval |= SPMODE_OP; |
568 | ||
b36ece83 | 569 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 JT |
570 | |
571 | ret = spi_register_master(master); | |
572 | if (ret < 0) | |
573 | goto unreg_master; | |
ccf06998 | 574 | |
b36ece83 | 575 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 576 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 577 | |
35b4b3c0 | 578 | return master; |
ccf06998 | 579 | |
c9bfcb31 | 580 | unreg_master: |
575c5807 | 581 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
b36ece83 MH |
582 | free_irq: |
583 | iounmap(mpc8xxx_spi->reg_base); | |
4c1fba44 | 584 | err_ioremap: |
b36ece83 | 585 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 586 | err_cpm_init: |
b36ece83 | 587 | err_probe: |
ccf06998 | 588 | spi_master_put(master); |
ccf06998 | 589 | err: |
35b4b3c0 | 590 | return ERR_PTR(ret); |
ccf06998 KG |
591 | } |
592 | ||
b36ece83 | 593 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 594 | { |
067aa481 | 595 | struct device *dev = spi->dev.parent->parent; |
575c5807 | 596 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
597 | u16 cs = spi->chip_select; |
598 | int gpio = pinfo->gpios[cs]; | |
599 | bool alow = pinfo->alow_flags[cs]; | |
600 | ||
601 | gpio_set_value(gpio, on ^ alow); | |
602 | } | |
603 | ||
b36ece83 | 604 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 605 | { |
61c7a080 | 606 | struct device_node *np = dev->of_node; |
35b4b3c0 | 607 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
575c5807 | 608 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
e80beb27 | 609 | int ngpios; |
35b4b3c0 AV |
610 | int i = 0; |
611 | int ret; | |
612 | ||
613 | ngpios = of_gpio_count(np); | |
e80beb27 | 614 | if (ngpios <= 0) { |
35b4b3c0 AV |
615 | /* |
616 | * SPI w/o chip-select line. One SPI device is still permitted | |
617 | * though. | |
618 | */ | |
619 | pdata->max_chipselect = 1; | |
620 | return 0; | |
621 | } | |
622 | ||
02141546 | 623 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
624 | if (!pinfo->gpios) |
625 | return -ENOMEM; | |
02141546 | 626 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 627 | |
02141546 | 628 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
629 | GFP_KERNEL); |
630 | if (!pinfo->alow_flags) { | |
631 | ret = -ENOMEM; | |
632 | goto err_alloc_flags; | |
633 | } | |
634 | ||
635 | for (; i < ngpios; i++) { | |
636 | int gpio; | |
637 | enum of_gpio_flags flags; | |
638 | ||
639 | gpio = of_get_gpio_flags(np, i, &flags); | |
640 | if (!gpio_is_valid(gpio)) { | |
641 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 642 | ret = gpio; |
35b4b3c0 AV |
643 | goto err_loop; |
644 | } | |
645 | ||
646 | ret = gpio_request(gpio, dev_name(dev)); | |
647 | if (ret) { | |
648 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
649 | goto err_loop; | |
650 | } | |
651 | ||
652 | pinfo->gpios[i] = gpio; | |
653 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
654 | ||
655 | ret = gpio_direction_output(pinfo->gpios[i], | |
656 | pinfo->alow_flags[i]); | |
657 | if (ret) { | |
658 | dev_err(dev, "can't set output direction for gpio " | |
659 | "#%d: %d\n", i, ret); | |
660 | goto err_loop; | |
661 | } | |
662 | } | |
663 | ||
664 | pdata->max_chipselect = ngpios; | |
b36ece83 | 665 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
666 | |
667 | return 0; | |
668 | ||
669 | err_loop: | |
670 | while (i >= 0) { | |
671 | if (gpio_is_valid(pinfo->gpios[i])) | |
672 | gpio_free(pinfo->gpios[i]); | |
673 | i--; | |
674 | } | |
675 | ||
676 | kfree(pinfo->alow_flags); | |
677 | pinfo->alow_flags = NULL; | |
678 | err_alloc_flags: | |
679 | kfree(pinfo->gpios); | |
680 | pinfo->gpios = NULL; | |
681 | return ret; | |
682 | } | |
683 | ||
b36ece83 | 684 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
685 | { |
686 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 687 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
688 | int i; |
689 | ||
690 | if (!pinfo->gpios) | |
691 | return 0; | |
692 | ||
693 | for (i = 0; i < pdata->max_chipselect; i++) { | |
694 | if (gpio_is_valid(pinfo->gpios[i])) | |
695 | gpio_free(pinfo->gpios[i]); | |
696 | } | |
697 | ||
698 | kfree(pinfo->gpios); | |
699 | kfree(pinfo->alow_flags); | |
700 | return 0; | |
701 | } | |
702 | ||
fd4a319b | 703 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
704 | { |
705 | struct device *dev = &ofdev->dev; | |
61c7a080 | 706 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
707 | struct spi_master *master; |
708 | struct resource mem; | |
e8beacbb | 709 | int irq; |
35b4b3c0 AV |
710 | int ret = -ENOMEM; |
711 | ||
18d306d1 | 712 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
713 | if (ret) |
714 | return ret; | |
35b4b3c0 | 715 | |
b36ece83 | 716 | ret = of_fsl_spi_get_chipselects(dev); |
35b4b3c0 AV |
717 | if (ret) |
718 | goto err; | |
719 | ||
720 | ret = of_address_to_resource(np, 0, &mem); | |
721 | if (ret) | |
722 | goto err; | |
723 | ||
e8beacbb AL |
724 | irq = irq_of_parse_and_map(np, 0); |
725 | if (!irq) { | |
35b4b3c0 AV |
726 | ret = -EINVAL; |
727 | goto err; | |
728 | } | |
729 | ||
e8beacbb | 730 | master = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 AV |
731 | if (IS_ERR(master)) { |
732 | ret = PTR_ERR(master); | |
733 | goto err; | |
734 | } | |
735 | ||
35b4b3c0 AV |
736 | return 0; |
737 | ||
738 | err: | |
b36ece83 | 739 | of_fsl_spi_free_chipselects(dev); |
35b4b3c0 AV |
740 | return ret; |
741 | } | |
742 | ||
fd4a319b | 743 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 AV |
744 | { |
745 | int ret; | |
746 | ||
575c5807 | 747 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
748 | if (ret) |
749 | return ret; | |
b36ece83 | 750 | of_fsl_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
751 | return 0; |
752 | } | |
753 | ||
18d306d1 | 754 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 755 | .driver = { |
b36ece83 | 756 | .name = "fsl_spi", |
4018294b | 757 | .owner = THIS_MODULE, |
b36ece83 | 758 | .of_match_table = of_fsl_spi_match, |
4018294b | 759 | }, |
b36ece83 | 760 | .probe = of_fsl_spi_probe, |
fd4a319b | 761 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
762 | }; |
763 | ||
764 | #ifdef CONFIG_MPC832x_RDB | |
765 | /* | |
b36ece83 | 766 | * XXX XXX XXX |
35b4b3c0 AV |
767 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
768 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
769 | * tree can work with OpenFirmware driver. But for now we support old trees | |
770 | * as well. | |
771 | */ | |
fd4a319b | 772 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
773 | { |
774 | struct resource *mem; | |
e9a172f0 | 775 | int irq; |
35b4b3c0 AV |
776 | struct spi_master *master; |
777 | ||
778 | if (!pdev->dev.platform_data) | |
779 | return -EINVAL; | |
780 | ||
781 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
782 | if (!mem) | |
783 | return -EINVAL; | |
784 | ||
785 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 786 | if (irq <= 0) |
35b4b3c0 AV |
787 | return -EINVAL; |
788 | ||
b36ece83 | 789 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
e4d43781 | 790 | return PTR_RET(master); |
35b4b3c0 AV |
791 | } |
792 | ||
fd4a319b | 793 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 794 | { |
575c5807 | 795 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
796 | } |
797 | ||
575c5807 AV |
798 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
799 | static struct platform_driver mpc8xxx_spi_driver = { | |
800 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 801 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 802 | .driver = { |
575c5807 | 803 | .name = "mpc8xxx_spi", |
7e38c3c4 | 804 | .owner = THIS_MODULE, |
ccf06998 KG |
805 | }, |
806 | }; | |
807 | ||
35b4b3c0 AV |
808 | static bool legacy_driver_failed; |
809 | ||
810 | static void __init legacy_driver_register(void) | |
811 | { | |
575c5807 | 812 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
813 | } |
814 | ||
815 | static void __exit legacy_driver_unregister(void) | |
816 | { | |
817 | if (legacy_driver_failed) | |
818 | return; | |
575c5807 | 819 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
820 | } |
821 | #else | |
822 | static void __init legacy_driver_register(void) {} | |
823 | static void __exit legacy_driver_unregister(void) {} | |
824 | #endif /* CONFIG_MPC832x_RDB */ | |
825 | ||
b36ece83 | 826 | static int __init fsl_spi_init(void) |
ccf06998 | 827 | { |
35b4b3c0 | 828 | legacy_driver_register(); |
18d306d1 | 829 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 830 | } |
b36ece83 | 831 | module_init(fsl_spi_init); |
ccf06998 | 832 | |
b36ece83 | 833 | static void __exit fsl_spi_exit(void) |
ccf06998 | 834 | { |
18d306d1 | 835 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 836 | legacy_driver_unregister(); |
ccf06998 | 837 | } |
b36ece83 | 838 | module_exit(fsl_spi_exit); |
ccf06998 KG |
839 | |
840 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 841 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 842 | MODULE_LICENSE("GPL"); |