Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
b36ece83 | 2 | * Freescale SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 7 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 8 | * |
4c1fba44 AV |
9 | * CPM SPI and QE buffer descriptors mode support: |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
ccf06998 KG |
13 | * This program is free software; you can redistribute it and/or modify it |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #include <linux/module.h> | |
ccf06998 KG |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
ccf06998 KG |
21 | #include <linux/interrupt.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/irq.h> | |
ccf06998 KG |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/spi_bitbang.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/fsl_devices.h> | |
4c1fba44 AV |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/mm.h> | |
30 | #include <linux/mutex.h> | |
35b4b3c0 AV |
31 | #include <linux/of.h> |
32 | #include <linux/of_platform.h> | |
33 | #include <linux/gpio.h> | |
34 | #include <linux/of_gpio.h> | |
ccf06998 | 35 | |
35b4b3c0 | 36 | #include <sysdev/fsl_soc.h> |
4c1fba44 AV |
37 | #include <asm/cpm.h> |
38 | #include <asm/qe.h> | |
b36ece83 | 39 | |
ca632f55 | 40 | #include "spi-fsl-lib.h" |
ccf06998 | 41 | |
4c1fba44 AV |
42 | /* CPM1 and CPM2 are mutually exclusive. */ |
43 | #ifdef CONFIG_CPM1 | |
44 | #include <asm/cpm1.h> | |
45 | #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0) | |
46 | #else | |
47 | #include <asm/cpm2.h> | |
48 | #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0) | |
49 | #endif | |
50 | ||
ccf06998 | 51 | /* SPI Controller registers */ |
b36ece83 | 52 | struct fsl_spi_reg { |
ccf06998 KG |
53 | u8 res1[0x20]; |
54 | __be32 mode; | |
55 | __be32 event; | |
56 | __be32 mask; | |
57 | __be32 command; | |
58 | __be32 transmit; | |
59 | __be32 receive; | |
60 | }; | |
61 | ||
62 | /* SPI Controller mode register definitions */ | |
2a485d7a | 63 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
64 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
65 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
66 | #define SPMODE_DIV16 (1 << 27) | |
67 | #define SPMODE_REV (1 << 26) | |
68 | #define SPMODE_MS (1 << 25) | |
69 | #define SPMODE_ENABLE (1 << 24) | |
70 | #define SPMODE_LEN(x) ((x) << 20) | |
71 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 72 | #define SPMODE_OP (1 << 14) |
c9bfcb31 | 73 | #define SPMODE_CG(x) ((x) << 7) |
ccf06998 KG |
74 | |
75 | /* | |
76 | * Default for SPI Mode: | |
b36ece83 | 77 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk |
ccf06998 KG |
78 | */ |
79 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
80 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
81 | ||
82 | /* SPIE register values */ | |
83 | #define SPIE_NE 0x00000200 /* Not empty */ | |
84 | #define SPIE_NF 0x00000100 /* Not full */ | |
85 | ||
86 | /* SPIM register values */ | |
87 | #define SPIM_NE 0x00000200 /* Not empty */ | |
88 | #define SPIM_NF 0x00000100 /* Not full */ | |
89 | ||
4c1fba44 AV |
90 | #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */ |
91 | #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */ | |
92 | ||
93 | /* SPCOM register values */ | |
94 | #define SPCOM_STR (1 << 23) /* Start transmit */ | |
95 | ||
96 | #define SPI_PRAM_SIZE 0x100 | |
97 | #define SPI_MRBLR ((unsigned int)PAGE_SIZE) | |
98 | ||
b36ece83 MH |
99 | static void *fsl_dummy_rx; |
100 | static DEFINE_MUTEX(fsl_dummy_rx_lock); | |
101 | static int fsl_dummy_rx_refcnt; | |
ccf06998 | 102 | |
b36ece83 | 103 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
104 | { |
105 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
106 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
107 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
108 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
109 | unsigned long flags; |
110 | ||
111 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
112 | return; | |
113 | ||
114 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
115 | local_irq_save(flags); | |
116 | ||
117 | /* Turn off SPI unit prior changing mode */ | |
118 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 119 | |
4c1fba44 AV |
120 | /* When in CPM mode, we need to reinit tx and rx. */ |
121 | if (mspi->flags & SPI_CPM_MODE) { | |
122 | if (mspi->flags & SPI_QE) { | |
123 | qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock, | |
124 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
125 | } else { | |
126 | cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX); | |
127 | if (mspi->flags & SPI_CPM1) { | |
128 | out_be16(&mspi->pram->rbptr, | |
129 | in_be16(&mspi->pram->rbase)); | |
130 | out_be16(&mspi->pram->tbptr, | |
131 | in_be16(&mspi->pram->tbase)); | |
132 | } | |
133 | } | |
134 | } | |
f9218c2a | 135 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
136 | local_irq_restore(flags); |
137 | } | |
138 | ||
b36ece83 | 139 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 140 | { |
575c5807 | 141 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 142 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 143 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 144 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 145 | |
5039a869 KE |
146 | pdata = spi->dev.parent->parent->platform_data; |
147 | ||
ccf06998 | 148 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
149 | if (pdata->cs_control) |
150 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
151 | } |
152 | ||
153 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
154 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
155 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
156 | mpc8xxx_spi->get_rx = cs->get_rx; | |
157 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 158 | |
b36ece83 | 159 | fsl_spi_change_mode(spi); |
a35c1710 | 160 | |
364fdbc0 AV |
161 | if (pdata->cs_control) |
162 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
163 | } |
164 | } | |
165 | ||
b36ece83 MH |
166 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
167 | struct spi_device *spi, | |
168 | struct mpc8xxx_spi *mpc8xxx_spi, | |
169 | int bits_per_word) | |
ccf06998 | 170 | { |
c9bfcb31 JT |
171 | cs->rx_shift = 0; |
172 | cs->tx_shift = 0; | |
ccf06998 | 173 | if (bits_per_word <= 8) { |
575c5807 AV |
174 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
175 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
87ec0e98 | 176 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
177 | cs->rx_shift = 16; |
178 | cs->tx_shift = 24; | |
f29ba280 | 179 | } |
ccf06998 | 180 | } else if (bits_per_word <= 16) { |
575c5807 AV |
181 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
182 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
87ec0e98 | 183 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
184 | cs->rx_shift = 16; |
185 | cs->tx_shift = 16; | |
f29ba280 | 186 | } |
ccf06998 | 187 | } else if (bits_per_word <= 32) { |
575c5807 AV |
188 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
189 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
190 | } else |
191 | return -EINVAL; | |
192 | ||
87ec0e98 | 193 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE && |
0398fb70 | 194 | spi->mode & SPI_LSB_FIRST) { |
c9bfcb31 | 195 | cs->tx_shift = 0; |
35cc0b97 | 196 | if (bits_per_word <= 8) |
c9bfcb31 | 197 | cs->rx_shift = 8; |
35cc0b97 | 198 | else |
c9bfcb31 | 199 | cs->rx_shift = 0; |
35cc0b97 | 200 | } |
575c5807 AV |
201 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
202 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
203 | mpc8xxx_spi->get_rx = cs->get_rx; | |
204 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 205 | |
0398fb70 JT |
206 | return bits_per_word; |
207 | } | |
208 | ||
b36ece83 MH |
209 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
210 | struct spi_device *spi, | |
211 | int bits_per_word) | |
0398fb70 JT |
212 | { |
213 | /* QE uses Little Endian for words > 8 | |
214 | * so transform all words > 8 into 8 bits | |
215 | * Unfortnatly that doesn't work for LSB so | |
216 | * reject these for now */ | |
217 | /* Note: 32 bits word, LSB works iff | |
218 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
219 | if (spi->mode & SPI_LSB_FIRST && | |
220 | bits_per_word > 8) | |
221 | return -EINVAL; | |
222 | if (bits_per_word > 8) | |
223 | return 8; /* pretend its 8 bits */ | |
224 | return bits_per_word; | |
225 | } | |
226 | ||
b36ece83 MH |
227 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
228 | struct spi_transfer *t) | |
0398fb70 JT |
229 | { |
230 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 231 | int bits_per_word = 0; |
0398fb70 | 232 | u8 pm; |
b36ece83 | 233 | u32 hz = 0; |
0398fb70 JT |
234 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
235 | ||
236 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
237 | ||
238 | if (t) { | |
239 | bits_per_word = t->bits_per_word; | |
240 | hz = t->speed_hz; | |
0398fb70 JT |
241 | } |
242 | ||
243 | /* spi_transfer level calls that work per-word */ | |
244 | if (!bits_per_word) | |
245 | bits_per_word = spi->bits_per_word; | |
246 | ||
247 | /* Make sure its a bit width we support [4..16, 32] */ | |
248 | if ((bits_per_word < 4) | |
249 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
250 | return -EINVAL; | |
251 | ||
252 | if (!hz) | |
253 | hz = spi->max_speed_hz; | |
254 | ||
255 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
256 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
257 | mpc8xxx_spi, | |
258 | bits_per_word); | |
259 | else if (mpc8xxx_spi->flags & SPI_QE) | |
260 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
261 | bits_per_word); | |
262 | ||
263 | if (bits_per_word < 0) | |
264 | return bits_per_word; | |
265 | ||
ccf06998 KG |
266 | if (bits_per_word == 32) |
267 | bits_per_word = 0; | |
268 | else | |
269 | bits_per_word = bits_per_word - 1; | |
270 | ||
32421daa | 271 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
272 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
273 | | SPMODE_PM(0xF)); | |
274 | ||
275 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
276 | ||
575c5807 | 277 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 278 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 279 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
fd8a11e1 AV |
280 | |
281 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
282 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 283 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 284 | if (pm > 16) |
53604dbe | 285 | pm = 16; |
b36ece83 | 286 | } else { |
4f4517c4 | 287 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 288 | } |
a61f5345 CG |
289 | if (pm) |
290 | pm--; | |
291 | ||
292 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 293 | |
b36ece83 | 294 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
295 | return 0; |
296 | } | |
ccf06998 | 297 | |
b36ece83 | 298 | static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi) |
c9bfcb31 | 299 | { |
4c1fba44 AV |
300 | struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd; |
301 | struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd; | |
302 | unsigned int xfer_len = min(mspi->count, SPI_MRBLR); | |
303 | unsigned int xfer_ofs; | |
b36ece83 | 304 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
ccf06998 | 305 | |
4c1fba44 AV |
306 | xfer_ofs = mspi->xfer_in_progress->len - mspi->count; |
307 | ||
37880c90 | 308 | if (mspi->rx_dma == mspi->dma_dummy_rx) |
309 | out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma); | |
310 | else | |
311 | out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs); | |
4c1fba44 AV |
312 | out_be16(&rx_bd->cbd_datlen, 0); |
313 | out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP); | |
314 | ||
37880c90 | 315 | if (mspi->tx_dma == mspi->dma_dummy_tx) |
316 | out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma); | |
317 | else | |
318 | out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs); | |
4c1fba44 AV |
319 | out_be16(&tx_bd->cbd_datlen, xfer_len); |
320 | out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP | | |
321 | BD_SC_LAST); | |
322 | ||
323 | /* start transfer */ | |
b36ece83 | 324 | mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR); |
4c1fba44 AV |
325 | } |
326 | ||
b36ece83 | 327 | static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
328 | struct spi_transfer *t, bool is_dma_mapped) |
329 | { | |
330 | struct device *dev = mspi->dev; | |
b36ece83 | 331 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
332 | |
333 | if (is_dma_mapped) { | |
334 | mspi->map_tx_dma = 0; | |
335 | mspi->map_rx_dma = 0; | |
336 | } else { | |
337 | mspi->map_tx_dma = 1; | |
338 | mspi->map_rx_dma = 1; | |
339 | } | |
340 | ||
341 | if (!t->tx_buf) { | |
342 | mspi->tx_dma = mspi->dma_dummy_tx; | |
343 | mspi->map_tx_dma = 0; | |
344 | } | |
345 | ||
346 | if (!t->rx_buf) { | |
347 | mspi->rx_dma = mspi->dma_dummy_rx; | |
348 | mspi->map_rx_dma = 0; | |
349 | } | |
350 | ||
351 | if (mspi->map_tx_dma) { | |
352 | void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ | |
353 | ||
354 | mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len, | |
355 | DMA_TO_DEVICE); | |
356 | if (dma_mapping_error(dev, mspi->tx_dma)) { | |
357 | dev_err(dev, "unable to map tx dma\n"); | |
358 | return -ENOMEM; | |
359 | } | |
f9218c2a | 360 | } else if (t->tx_buf) { |
4c1fba44 AV |
361 | mspi->tx_dma = t->tx_dma; |
362 | } | |
363 | ||
364 | if (mspi->map_rx_dma) { | |
365 | mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len, | |
366 | DMA_FROM_DEVICE); | |
367 | if (dma_mapping_error(dev, mspi->rx_dma)) { | |
368 | dev_err(dev, "unable to map rx dma\n"); | |
369 | goto err_rx_dma; | |
370 | } | |
f9218c2a | 371 | } else if (t->rx_buf) { |
4c1fba44 AV |
372 | mspi->rx_dma = t->rx_dma; |
373 | } | |
374 | ||
375 | /* enable rx ints */ | |
b36ece83 | 376 | mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB); |
4c1fba44 AV |
377 | |
378 | mspi->xfer_in_progress = t; | |
379 | mspi->count = t->len; | |
380 | ||
381 | /* start CPM transfers */ | |
b36ece83 | 382 | fsl_spi_cpm_bufs_start(mspi); |
4c1fba44 AV |
383 | |
384 | return 0; | |
385 | ||
386 | err_rx_dma: | |
387 | if (mspi->map_tx_dma) | |
388 | dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); | |
389 | return -ENOMEM; | |
390 | } | |
391 | ||
b36ece83 | 392 | static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
393 | { |
394 | struct device *dev = mspi->dev; | |
395 | struct spi_transfer *t = mspi->xfer_in_progress; | |
396 | ||
397 | if (mspi->map_tx_dma) | |
398 | dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); | |
338ff298 | 399 | if (mspi->map_rx_dma) |
4c1fba44 AV |
400 | dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); |
401 | mspi->xfer_in_progress = NULL; | |
402 | } | |
403 | ||
b36ece83 | 404 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
405 | struct spi_transfer *t, unsigned int len) |
406 | { | |
407 | u32 word; | |
b36ece83 | 408 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
409 | |
410 | mspi->count = len; | |
411 | ||
412 | /* enable rx ints */ | |
b36ece83 | 413 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
414 | |
415 | /* transmit word */ | |
416 | word = mspi->get_tx(mspi); | |
b36ece83 | 417 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
418 | |
419 | return 0; | |
420 | } | |
421 | ||
b36ece83 | 422 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
423 | bool is_dma_mapped) |
424 | { | |
425 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 426 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
427 | unsigned int len = t->len; |
428 | u8 bits_per_word; | |
429 | int ret; | |
c9bfcb31 | 430 | |
b36ece83 | 431 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
432 | bits_per_word = spi->bits_per_word; |
433 | if (t->bits_per_word) | |
434 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 435 | |
aa77d96b PK |
436 | if (bits_per_word > 8) { |
437 | /* invalid length? */ | |
438 | if (len & 1) | |
439 | return -EINVAL; | |
c9bfcb31 | 440 | len /= 2; |
aa77d96b PK |
441 | } |
442 | if (bits_per_word > 16) { | |
443 | /* invalid length? */ | |
444 | if (len & 1) | |
445 | return -EINVAL; | |
c9bfcb31 | 446 | len /= 2; |
aa77d96b | 447 | } |
aa77d96b | 448 | |
4c1fba44 AV |
449 | mpc8xxx_spi->tx = t->tx_buf; |
450 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 451 | |
4c1fba44 | 452 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 | 453 | |
4c1fba44 | 454 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 455 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 456 | else |
b36ece83 | 457 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
458 | if (ret) |
459 | return ret; | |
c9bfcb31 | 460 | |
575c5807 | 461 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
462 | |
463 | /* disable rx ints */ | |
b36ece83 | 464 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 465 | |
4c1fba44 | 466 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 467 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 468 | |
575c5807 | 469 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
470 | } |
471 | ||
b36ece83 | 472 | static void fsl_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 473 | { |
b9b9af11 AV |
474 | struct spi_device *spi = m->spi; |
475 | struct spi_transfer *t; | |
476 | unsigned int cs_change; | |
477 | const int nsecs = 50; | |
478 | int status; | |
479 | ||
480 | cs_change = 1; | |
481 | status = 0; | |
482 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
483 | if (t->bits_per_word || t->speed_hz) { | |
484 | /* Don't allow changes if CS is active */ | |
485 | status = -EINVAL; | |
486 | ||
487 | if (cs_change) | |
b36ece83 | 488 | status = fsl_spi_setup_transfer(spi, t); |
b9b9af11 | 489 | if (status < 0) |
c9bfcb31 | 490 | break; |
b9b9af11 | 491 | } |
c9bfcb31 | 492 | |
b9b9af11 | 493 | if (cs_change) { |
b36ece83 | 494 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
495 | ndelay(nsecs); |
496 | } | |
497 | cs_change = t->cs_change; | |
498 | if (t->len) | |
b36ece83 | 499 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
500 | if (status) { |
501 | status = -EMSGSIZE; | |
502 | break; | |
c9bfcb31 | 503 | } |
b9b9af11 | 504 | m->actual_length += t->len; |
c9bfcb31 | 505 | |
b9b9af11 AV |
506 | if (t->delay_usecs) |
507 | udelay(t->delay_usecs); | |
c9bfcb31 | 508 | |
b9b9af11 | 509 | if (cs_change) { |
c9bfcb31 | 510 | ndelay(nsecs); |
b36ece83 | 511 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 512 | ndelay(nsecs); |
c9bfcb31 | 513 | } |
b9b9af11 AV |
514 | } |
515 | ||
516 | m->status = status; | |
517 | m->complete(m->context); | |
518 | ||
519 | if (status || !cs_change) { | |
520 | ndelay(nsecs); | |
b36ece83 | 521 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
522 | } |
523 | ||
b36ece83 | 524 | fsl_spi_setup_transfer(spi, NULL); |
ccf06998 KG |
525 | } |
526 | ||
b36ece83 | 527 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 528 | { |
575c5807 | 529 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 530 | struct fsl_spi_reg *reg_base; |
ccf06998 | 531 | int retval; |
c9bfcb31 | 532 | u32 hw_mode; |
575c5807 | 533 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
534 | |
535 | if (!spi->max_speed_hz) | |
536 | return -EINVAL; | |
537 | ||
c9bfcb31 JT |
538 | if (!cs) { |
539 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
540 | if (!cs) | |
541 | return -ENOMEM; | |
542 | spi->controller_state = cs; | |
543 | } | |
575c5807 | 544 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 545 | |
b36ece83 MH |
546 | reg_base = mpc8xxx_spi->reg_base; |
547 | ||
88393161 | 548 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 549 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
550 | /* mask out bits we are going to set */ |
551 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
552 | | SPMODE_REV | SPMODE_LOOP); | |
553 | ||
554 | if (spi->mode & SPI_CPHA) | |
555 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
556 | if (spi->mode & SPI_CPOL) | |
557 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
558 | if (!(spi->mode & SPI_LSB_FIRST)) | |
559 | cs->hw_mode |= SPMODE_REV; | |
560 | if (spi->mode & SPI_LOOP) | |
561 | cs->hw_mode |= SPMODE_LOOP; | |
562 | ||
b36ece83 | 563 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
564 | if (retval < 0) { |
565 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 566 | return retval; |
c9bfcb31 | 567 | } |
ccf06998 KG |
568 | return 0; |
569 | } | |
570 | ||
b36ece83 | 571 | static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) |
ccf06998 | 572 | { |
4c1fba44 | 573 | u16 len; |
b36ece83 | 574 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
ccf06998 | 575 | |
4c1fba44 AV |
576 | dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__, |
577 | in_be16(&mspi->rx_bd->cbd_datlen), mspi->count); | |
ccf06998 | 578 | |
4c1fba44 AV |
579 | len = in_be16(&mspi->rx_bd->cbd_datlen); |
580 | if (len > mspi->count) { | |
581 | WARN_ON(1); | |
582 | len = mspi->count; | |
583 | } | |
ccf06998 | 584 | |
4c1fba44 | 585 | /* Clear the events */ |
b36ece83 | 586 | mpc8xxx_spi_write_reg(®_base->event, events); |
ccf06998 | 587 | |
4c1fba44 AV |
588 | mspi->count -= len; |
589 | if (mspi->count) | |
b36ece83 | 590 | fsl_spi_cpm_bufs_start(mspi); |
4c1fba44 AV |
591 | else |
592 | complete(&mspi->done); | |
593 | } | |
594 | ||
b36ece83 | 595 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 596 | { |
b36ece83 MH |
597 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
598 | ||
4c1fba44 AV |
599 | /* We need handle RX first */ |
600 | if (events & SPIE_NE) { | |
b36ece83 | 601 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
602 | |
603 | if (mspi->rx) | |
604 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
605 | } |
606 | ||
4c1fba44 | 607 | if ((events & SPIE_NF) == 0) |
ccf06998 | 608 | /* spin until TX is done */ |
4c1fba44 | 609 | while (((events = |
b36ece83 | 610 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 611 | SPIE_NF) == 0) |
9effb959 | 612 | cpu_relax(); |
ccf06998 | 613 | |
4c1fba44 | 614 | /* Clear the events */ |
b36ece83 | 615 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
616 | |
617 | mspi->count -= 1; | |
618 | if (mspi->count) { | |
619 | u32 word = mspi->get_tx(mspi); | |
620 | ||
b36ece83 | 621 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 622 | } else { |
4c1fba44 | 623 | complete(&mspi->done); |
ccf06998 | 624 | } |
4c1fba44 | 625 | } |
ccf06998 | 626 | |
b36ece83 | 627 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
628 | { |
629 | struct mpc8xxx_spi *mspi = context_data; | |
630 | irqreturn_t ret = IRQ_NONE; | |
631 | u32 events; | |
b36ece83 | 632 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
633 | |
634 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 635 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
636 | if (events) |
637 | ret = IRQ_HANDLED; | |
638 | ||
639 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
640 | ||
641 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 642 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 643 | else |
b36ece83 | 644 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
645 | |
646 | return ret; | |
647 | } | |
4c1fba44 | 648 | |
b36ece83 | 649 | static void *fsl_spi_alloc_dummy_rx(void) |
c9bfcb31 | 650 | { |
b36ece83 | 651 | mutex_lock(&fsl_dummy_rx_lock); |
c9bfcb31 | 652 | |
b36ece83 MH |
653 | if (!fsl_dummy_rx) |
654 | fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL); | |
655 | if (fsl_dummy_rx) | |
656 | fsl_dummy_rx_refcnt++; | |
c9bfcb31 | 657 | |
b36ece83 | 658 | mutex_unlock(&fsl_dummy_rx_lock); |
c9bfcb31 | 659 | |
b36ece83 | 660 | return fsl_dummy_rx; |
c9bfcb31 JT |
661 | } |
662 | ||
b36ece83 | 663 | static void fsl_spi_free_dummy_rx(void) |
c9bfcb31 | 664 | { |
b36ece83 | 665 | mutex_lock(&fsl_dummy_rx_lock); |
ccf06998 | 666 | |
b36ece83 | 667 | switch (fsl_dummy_rx_refcnt) { |
4c1fba44 AV |
668 | case 0: |
669 | WARN_ON(1); | |
670 | break; | |
671 | case 1: | |
b36ece83 MH |
672 | kfree(fsl_dummy_rx); |
673 | fsl_dummy_rx = NULL; | |
4c1fba44 AV |
674 | /* fall through */ |
675 | default: | |
b36ece83 | 676 | fsl_dummy_rx_refcnt--; |
4c1fba44 AV |
677 | break; |
678 | } | |
679 | ||
b36ece83 | 680 | mutex_unlock(&fsl_dummy_rx_lock); |
4c1fba44 AV |
681 | } |
682 | ||
b36ece83 | 683 | static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
684 | { |
685 | struct device *dev = mspi->dev; | |
61c7a080 | 686 | struct device_node *np = dev->of_node; |
4c1fba44 AV |
687 | const u32 *iprop; |
688 | int size; | |
fb644095 | 689 | void __iomem *spi_base; |
4c1fba44 AV |
690 | unsigned long pram_ofs = -ENOMEM; |
691 | ||
692 | /* Can't use of_address_to_resource(), QE muram isn't at 0. */ | |
693 | iprop = of_get_property(np, "reg", &size); | |
694 | ||
695 | /* QE with a fixed pram location? */ | |
696 | if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4) | |
697 | return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE); | |
698 | ||
699 | /* QE but with a dynamic pram location? */ | |
700 | if (mspi->flags & SPI_QE) { | |
701 | pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); | |
702 | qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock, | |
703 | QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs); | |
704 | return pram_ofs; | |
705 | } | |
706 | ||
fb644095 HB |
707 | spi_base = of_iomap(np, 1); |
708 | if (spi_base == NULL) | |
709 | return -EINVAL; | |
4c1fba44 AV |
710 | |
711 | if (mspi->flags & SPI_CPM2) { | |
712 | pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); | |
fb644095 | 713 | out_be16(spi_base, pram_ofs); |
4c1fba44 | 714 | } else { |
fb644095 | 715 | struct spi_pram __iomem *pram = spi_base; |
4c1fba44 AV |
716 | u16 rpbase = in_be16(&pram->rpbase); |
717 | ||
718 | /* Microcode relocation patch applied? */ | |
719 | if (rpbase) | |
720 | pram_ofs = rpbase; | |
fb644095 HB |
721 | else { |
722 | pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); | |
723 | out_be16(spi_base, pram_ofs); | |
724 | } | |
4c1fba44 AV |
725 | } |
726 | ||
fb644095 | 727 | iounmap(spi_base); |
4c1fba44 AV |
728 | return pram_ofs; |
729 | } | |
730 | ||
b36ece83 | 731 | static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
732 | { |
733 | struct device *dev = mspi->dev; | |
61c7a080 | 734 | struct device_node *np = dev->of_node; |
4c1fba44 AV |
735 | const u32 *iprop; |
736 | int size; | |
737 | unsigned long pram_ofs; | |
738 | unsigned long bds_ofs; | |
739 | ||
740 | if (!(mspi->flags & SPI_CPM_MODE)) | |
741 | return 0; | |
742 | ||
b36ece83 | 743 | if (!fsl_spi_alloc_dummy_rx()) |
4c1fba44 AV |
744 | return -ENOMEM; |
745 | ||
746 | if (mspi->flags & SPI_QE) { | |
747 | iprop = of_get_property(np, "cell-index", &size); | |
748 | if (iprop && size == sizeof(*iprop)) | |
749 | mspi->subblock = *iprop; | |
750 | ||
751 | switch (mspi->subblock) { | |
752 | default: | |
753 | dev_warn(dev, "cell-index unspecified, assuming SPI1"); | |
754 | /* fall through */ | |
755 | case 0: | |
756 | mspi->subblock = QE_CR_SUBBLOCK_SPI1; | |
757 | break; | |
758 | case 1: | |
759 | mspi->subblock = QE_CR_SUBBLOCK_SPI2; | |
760 | break; | |
761 | } | |
762 | } | |
763 | ||
b36ece83 | 764 | pram_ofs = fsl_spi_cpm_get_pram(mspi); |
4c1fba44 AV |
765 | if (IS_ERR_VALUE(pram_ofs)) { |
766 | dev_err(dev, "can't allocate spi parameter ram\n"); | |
767 | goto err_pram; | |
768 | } | |
769 | ||
770 | bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) + | |
771 | sizeof(*mspi->rx_bd), 8); | |
772 | if (IS_ERR_VALUE(bds_ofs)) { | |
773 | dev_err(dev, "can't allocate bds\n"); | |
774 | goto err_bds; | |
775 | } | |
776 | ||
777 | mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE, | |
778 | DMA_TO_DEVICE); | |
779 | if (dma_mapping_error(dev, mspi->dma_dummy_tx)) { | |
780 | dev_err(dev, "unable to map dummy tx buffer\n"); | |
781 | goto err_dummy_tx; | |
782 | } | |
783 | ||
b36ece83 | 784 | mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR, |
4c1fba44 AV |
785 | DMA_FROM_DEVICE); |
786 | if (dma_mapping_error(dev, mspi->dma_dummy_rx)) { | |
787 | dev_err(dev, "unable to map dummy rx buffer\n"); | |
788 | goto err_dummy_rx; | |
789 | } | |
790 | ||
791 | mspi->pram = cpm_muram_addr(pram_ofs); | |
792 | ||
793 | mspi->tx_bd = cpm_muram_addr(bds_ofs); | |
794 | mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd)); | |
795 | ||
796 | /* Initialize parameter ram. */ | |
797 | out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd)); | |
798 | out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd)); | |
799 | out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL); | |
800 | out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL); | |
801 | out_be16(&mspi->pram->mrblr, SPI_MRBLR); | |
802 | out_be32(&mspi->pram->rstate, 0); | |
803 | out_be32(&mspi->pram->rdp, 0); | |
804 | out_be16(&mspi->pram->rbptr, 0); | |
805 | out_be16(&mspi->pram->rbc, 0); | |
806 | out_be32(&mspi->pram->rxtmp, 0); | |
807 | out_be32(&mspi->pram->tstate, 0); | |
808 | out_be32(&mspi->pram->tdp, 0); | |
809 | out_be16(&mspi->pram->tbptr, 0); | |
810 | out_be16(&mspi->pram->tbc, 0); | |
811 | out_be32(&mspi->pram->txtmp, 0); | |
812 | ||
813 | return 0; | |
814 | ||
815 | err_dummy_rx: | |
816 | dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); | |
817 | err_dummy_tx: | |
818 | cpm_muram_free(bds_ofs); | |
819 | err_bds: | |
820 | cpm_muram_free(pram_ofs); | |
821 | err_pram: | |
b36ece83 | 822 | fsl_spi_free_dummy_rx(); |
4c1fba44 AV |
823 | return -ENOMEM; |
824 | } | |
825 | ||
b36ece83 | 826 | static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
827 | { |
828 | struct device *dev = mspi->dev; | |
829 | ||
387719c2 JH |
830 | if (!(mspi->flags & SPI_CPM_MODE)) |
831 | return; | |
832 | ||
4c1fba44 AV |
833 | dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE); |
834 | dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); | |
835 | cpm_muram_free(cpm_muram_offset(mspi->tx_bd)); | |
836 | cpm_muram_free(cpm_muram_offset(mspi->pram)); | |
b36ece83 | 837 | fsl_spi_free_dummy_rx(); |
4c1fba44 AV |
838 | } |
839 | ||
b36ece83 | 840 | static void fsl_spi_remove(struct mpc8xxx_spi *mspi) |
87ec0e98 | 841 | { |
b36ece83 MH |
842 | iounmap(mspi->reg_base); |
843 | fsl_spi_cpm_free(mspi); | |
87ec0e98 AV |
844 | } |
845 | ||
fd4a319b | 846 | static struct spi_master * fsl_spi_probe(struct device *dev, |
b36ece83 | 847 | struct resource *mem, unsigned int irq) |
ccf06998 | 848 | { |
35b4b3c0 | 849 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 850 | struct spi_master *master; |
575c5807 | 851 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 852 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
853 | u32 regval; |
854 | int ret = 0; | |
855 | ||
575c5807 | 856 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
857 | if (master == NULL) { |
858 | ret = -ENOMEM; | |
859 | goto err; | |
860 | } | |
861 | ||
35b4b3c0 | 862 | dev_set_drvdata(dev, master); |
ccf06998 | 863 | |
b36ece83 MH |
864 | ret = mpc8xxx_spi_probe(dev, mem, irq); |
865 | if (ret) | |
866 | goto err_probe; | |
e7db06b5 | 867 | |
b36ece83 | 868 | master->setup = fsl_spi_setup; |
575c5807 AV |
869 | |
870 | mpc8xxx_spi = spi_master_get_devdata(master); | |
b36ece83 MH |
871 | mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; |
872 | mpc8xxx_spi->spi_remove = fsl_spi_remove; | |
873 | ||
575c5807 | 874 | |
b36ece83 | 875 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
876 | if (ret) |
877 | goto err_cpm_init; | |
878 | ||
87ec0e98 | 879 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
575c5807 AV |
880 | mpc8xxx_spi->rx_shift = 16; |
881 | mpc8xxx_spi->tx_shift = 24; | |
f29ba280 JT |
882 | } |
883 | ||
b36ece83 MH |
884 | mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); |
885 | if (mpc8xxx_spi->reg_base == NULL) { | |
ccf06998 | 886 | ret = -ENOMEM; |
4c1fba44 | 887 | goto err_ioremap; |
ccf06998 KG |
888 | } |
889 | ||
ccf06998 | 890 | /* Register for SPI Interrupt */ |
b36ece83 MH |
891 | ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, |
892 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
893 | |
894 | if (ret != 0) | |
b36ece83 | 895 | goto free_irq; |
ccf06998 | 896 | |
b36ece83 | 897 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
898 | |
899 | /* SPI controller initializations */ | |
b36ece83 MH |
900 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
901 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
902 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
903 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
904 | |
905 | /* Enable SPI interface */ | |
906 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
87ec0e98 | 907 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
908 | regval |= SPMODE_OP; |
909 | ||
b36ece83 | 910 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 JT |
911 | |
912 | ret = spi_register_master(master); | |
913 | if (ret < 0) | |
914 | goto unreg_master; | |
ccf06998 | 915 | |
b36ece83 | 916 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 917 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 918 | |
35b4b3c0 | 919 | return master; |
ccf06998 | 920 | |
c9bfcb31 | 921 | unreg_master: |
575c5807 | 922 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
b36ece83 MH |
923 | free_irq: |
924 | iounmap(mpc8xxx_spi->reg_base); | |
4c1fba44 | 925 | err_ioremap: |
b36ece83 | 926 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 927 | err_cpm_init: |
b36ece83 | 928 | err_probe: |
ccf06998 | 929 | spi_master_put(master); |
ccf06998 | 930 | err: |
35b4b3c0 | 931 | return ERR_PTR(ret); |
ccf06998 KG |
932 | } |
933 | ||
b36ece83 | 934 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 935 | { |
067aa481 | 936 | struct device *dev = spi->dev.parent->parent; |
575c5807 | 937 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
938 | u16 cs = spi->chip_select; |
939 | int gpio = pinfo->gpios[cs]; | |
940 | bool alow = pinfo->alow_flags[cs]; | |
941 | ||
942 | gpio_set_value(gpio, on ^ alow); | |
943 | } | |
944 | ||
b36ece83 | 945 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 946 | { |
61c7a080 | 947 | struct device_node *np = dev->of_node; |
35b4b3c0 | 948 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
575c5807 | 949 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
950 | unsigned int ngpios; |
951 | int i = 0; | |
952 | int ret; | |
953 | ||
954 | ngpios = of_gpio_count(np); | |
955 | if (!ngpios) { | |
956 | /* | |
957 | * SPI w/o chip-select line. One SPI device is still permitted | |
958 | * though. | |
959 | */ | |
960 | pdata->max_chipselect = 1; | |
961 | return 0; | |
962 | } | |
963 | ||
02141546 | 964 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
965 | if (!pinfo->gpios) |
966 | return -ENOMEM; | |
02141546 | 967 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 968 | |
02141546 | 969 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
970 | GFP_KERNEL); |
971 | if (!pinfo->alow_flags) { | |
972 | ret = -ENOMEM; | |
973 | goto err_alloc_flags; | |
974 | } | |
975 | ||
976 | for (; i < ngpios; i++) { | |
977 | int gpio; | |
978 | enum of_gpio_flags flags; | |
979 | ||
980 | gpio = of_get_gpio_flags(np, i, &flags); | |
981 | if (!gpio_is_valid(gpio)) { | |
982 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 983 | ret = gpio; |
35b4b3c0 AV |
984 | goto err_loop; |
985 | } | |
986 | ||
987 | ret = gpio_request(gpio, dev_name(dev)); | |
988 | if (ret) { | |
989 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
990 | goto err_loop; | |
991 | } | |
992 | ||
993 | pinfo->gpios[i] = gpio; | |
994 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
995 | ||
996 | ret = gpio_direction_output(pinfo->gpios[i], | |
997 | pinfo->alow_flags[i]); | |
998 | if (ret) { | |
999 | dev_err(dev, "can't set output direction for gpio " | |
1000 | "#%d: %d\n", i, ret); | |
1001 | goto err_loop; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | pdata->max_chipselect = ngpios; | |
b36ece83 | 1006 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
1007 | |
1008 | return 0; | |
1009 | ||
1010 | err_loop: | |
1011 | while (i >= 0) { | |
1012 | if (gpio_is_valid(pinfo->gpios[i])) | |
1013 | gpio_free(pinfo->gpios[i]); | |
1014 | i--; | |
1015 | } | |
1016 | ||
1017 | kfree(pinfo->alow_flags); | |
1018 | pinfo->alow_flags = NULL; | |
1019 | err_alloc_flags: | |
1020 | kfree(pinfo->gpios); | |
1021 | pinfo->gpios = NULL; | |
1022 | return ret; | |
1023 | } | |
1024 | ||
b36ece83 | 1025 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
1026 | { |
1027 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 1028 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
1029 | int i; |
1030 | ||
1031 | if (!pinfo->gpios) | |
1032 | return 0; | |
1033 | ||
1034 | for (i = 0; i < pdata->max_chipselect; i++) { | |
1035 | if (gpio_is_valid(pinfo->gpios[i])) | |
1036 | gpio_free(pinfo->gpios[i]); | |
1037 | } | |
1038 | ||
1039 | kfree(pinfo->gpios); | |
1040 | kfree(pinfo->alow_flags); | |
1041 | return 0; | |
1042 | } | |
1043 | ||
fd4a319b | 1044 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
1045 | { |
1046 | struct device *dev = &ofdev->dev; | |
61c7a080 | 1047 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
1048 | struct spi_master *master; |
1049 | struct resource mem; | |
1050 | struct resource irq; | |
35b4b3c0 AV |
1051 | int ret = -ENOMEM; |
1052 | ||
18d306d1 | 1053 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
1054 | if (ret) |
1055 | return ret; | |
35b4b3c0 | 1056 | |
b36ece83 | 1057 | ret = of_fsl_spi_get_chipselects(dev); |
35b4b3c0 AV |
1058 | if (ret) |
1059 | goto err; | |
1060 | ||
1061 | ret = of_address_to_resource(np, 0, &mem); | |
1062 | if (ret) | |
1063 | goto err; | |
1064 | ||
1065 | ret = of_irq_to_resource(np, 0, &irq); | |
1066 | if (!ret) { | |
1067 | ret = -EINVAL; | |
1068 | goto err; | |
1069 | } | |
1070 | ||
b36ece83 | 1071 | master = fsl_spi_probe(dev, &mem, irq.start); |
35b4b3c0 AV |
1072 | if (IS_ERR(master)) { |
1073 | ret = PTR_ERR(master); | |
1074 | goto err; | |
1075 | } | |
1076 | ||
35b4b3c0 AV |
1077 | return 0; |
1078 | ||
1079 | err: | |
b36ece83 | 1080 | of_fsl_spi_free_chipselects(dev); |
35b4b3c0 AV |
1081 | return ret; |
1082 | } | |
1083 | ||
fd4a319b | 1084 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 AV |
1085 | { |
1086 | int ret; | |
1087 | ||
575c5807 | 1088 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
1089 | if (ret) |
1090 | return ret; | |
b36ece83 | 1091 | of_fsl_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
1092 | return 0; |
1093 | } | |
1094 | ||
b36ece83 | 1095 | static const struct of_device_id of_fsl_spi_match[] = { |
35b4b3c0 | 1096 | { .compatible = "fsl,spi" }, |
b36ece83 | 1097 | {} |
35b4b3c0 | 1098 | }; |
b36ece83 | 1099 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); |
35b4b3c0 | 1100 | |
18d306d1 | 1101 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 1102 | .driver = { |
b36ece83 | 1103 | .name = "fsl_spi", |
4018294b | 1104 | .owner = THIS_MODULE, |
b36ece83 | 1105 | .of_match_table = of_fsl_spi_match, |
4018294b | 1106 | }, |
b36ece83 | 1107 | .probe = of_fsl_spi_probe, |
fd4a319b | 1108 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
1109 | }; |
1110 | ||
1111 | #ifdef CONFIG_MPC832x_RDB | |
1112 | /* | |
b36ece83 | 1113 | * XXX XXX XXX |
35b4b3c0 AV |
1114 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
1115 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
1116 | * tree can work with OpenFirmware driver. But for now we support old trees | |
1117 | * as well. | |
1118 | */ | |
fd4a319b | 1119 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
1120 | { |
1121 | struct resource *mem; | |
e9a172f0 | 1122 | int irq; |
35b4b3c0 AV |
1123 | struct spi_master *master; |
1124 | ||
1125 | if (!pdev->dev.platform_data) | |
1126 | return -EINVAL; | |
1127 | ||
1128 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1129 | if (!mem) | |
1130 | return -EINVAL; | |
1131 | ||
1132 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 1133 | if (irq <= 0) |
35b4b3c0 AV |
1134 | return -EINVAL; |
1135 | ||
b36ece83 | 1136 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
35b4b3c0 AV |
1137 | if (IS_ERR(master)) |
1138 | return PTR_ERR(master); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
fd4a319b | 1142 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 1143 | { |
575c5807 | 1144 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
1145 | } |
1146 | ||
575c5807 AV |
1147 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
1148 | static struct platform_driver mpc8xxx_spi_driver = { | |
1149 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 1150 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 1151 | .driver = { |
575c5807 | 1152 | .name = "mpc8xxx_spi", |
7e38c3c4 | 1153 | .owner = THIS_MODULE, |
ccf06998 KG |
1154 | }, |
1155 | }; | |
1156 | ||
35b4b3c0 AV |
1157 | static bool legacy_driver_failed; |
1158 | ||
1159 | static void __init legacy_driver_register(void) | |
1160 | { | |
575c5807 | 1161 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
1162 | } |
1163 | ||
1164 | static void __exit legacy_driver_unregister(void) | |
1165 | { | |
1166 | if (legacy_driver_failed) | |
1167 | return; | |
575c5807 | 1168 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
1169 | } |
1170 | #else | |
1171 | static void __init legacy_driver_register(void) {} | |
1172 | static void __exit legacy_driver_unregister(void) {} | |
1173 | #endif /* CONFIG_MPC832x_RDB */ | |
1174 | ||
b36ece83 | 1175 | static int __init fsl_spi_init(void) |
ccf06998 | 1176 | { |
35b4b3c0 | 1177 | legacy_driver_register(); |
18d306d1 | 1178 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 1179 | } |
b36ece83 | 1180 | module_init(fsl_spi_init); |
ccf06998 | 1181 | |
b36ece83 | 1182 | static void __exit fsl_spi_exit(void) |
ccf06998 | 1183 | { |
18d306d1 | 1184 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 1185 | legacy_driver_unregister(); |
ccf06998 | 1186 | } |
b36ece83 | 1187 | module_exit(fsl_spi_exit); |
ccf06998 KG |
1188 | |
1189 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 1190 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 1191 | MODULE_LICENSE("GPL"); |