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dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
[deliverable/linux.git] / drivers / spi / spi-imx.c
CommitLineData
b5f3294f
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
f62caccd
RG		 24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
b5f3294f
SH		 26#include <linux/err.h>
27#include <linux/gpio.h>
b5f3294f
SH		 28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
5a0e3ad6 34#include <linux/slab.h>
b5f3294f
SH		 35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
22a85e4c
SG		 38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
b5f3294f 41
f62caccd 42#include <linux/platform_data/dma-imx.h>
82906b13 43#include <linux/platform_data/spi-imx.h>
b5f3294f
SH		 44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
f62caccd
RG		 57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
6cdeb002 60struct spi_imx_config {
b5f3294f
SH		 61 unsigned int speed_hz;
62 unsigned int bpw;
63 unsigned int mode;
3b2aa89e 64 u8 cs;
b5f3294f
SH		 65};
66
f4ba6315 67enum spi_imx_devtype {
04ee5854
SG		 68 IMX1_CSPI,
69 IMX21_CSPI,
70 IMX27_CSPI,
71 IMX31_CSPI,
72 IMX35_CSPI, /* CSPI on all i.mx except above */
73 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
f4ba6315
UKK		 74};
75
76struct spi_imx_data;
77
78struct spi_imx_devtype_data {
79 void (*intctrl)(struct spi_imx_data *, int);
80 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
81 void (*trigger)(struct spi_imx_data *);
82 int (*rx_available)(struct spi_imx_data *);
1723e66b 83 void (*reset)(struct spi_imx_data *);
04ee5854 84 enum spi_imx_devtype devtype;
f4ba6315
UKK		 85};
86
6cdeb002 87struct spi_imx_data {
b5f3294f
SH		 88 struct spi_bitbang bitbang;
89
90 struct completion xfer_done;
cc4d22ae 91 void __iomem *base;
b5f3294f 92 int irq;
aa29d840
SH		 93 struct clk *clk_per;
94 struct clk *clk_ipg;
b5f3294f 95 unsigned long spi_clk;
b5f3294f
SH		 96
97 unsigned int count;
6cdeb002
UKK		 98 void (*tx)(struct spi_imx_data *);
99 void (*rx)(struct spi_imx_data *);
b5f3294f
SH		 100 void *rx_buf;
101 const void *tx_buf;
102 unsigned int txfifo; /* number of words pushed in tx FIFO */
103
f62caccd
RG		 104 /* DMA */
105 unsigned int dma_is_inited;
106 unsigned int dma_finished;
107 bool usedma;
108 u32 rx_wml;
109 u32 tx_wml;
110 u32 rxt_wml;
111 struct completion dma_rx_completion;
112 struct completion dma_tx_completion;
113
80023cb3 114 const struct spi_imx_devtype_data *devtype_data;
c2387cb9 115 int chipselect[0];
b5f3294f
SH		 116};
117
04ee5854
SG		 118static inline int is_imx27_cspi(struct spi_imx_data *d)
119{
120 return d->devtype_data->devtype == IMX27_CSPI;
121}
122
123static inline int is_imx35_cspi(struct spi_imx_data *d)
124{
125 return d->devtype_data->devtype == IMX35_CSPI;
126}
127
128static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
129{
130 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
131}
132
b5f3294f 133#define MXC_SPI_BUF_RX(type) \
6cdeb002 134static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
b5f3294f 135{ \
6cdeb002 136 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
b5f3294f 137 \
6cdeb002
UKK		 138 if (spi_imx->rx_buf) { \
139 *(type *)spi_imx->rx_buf = val; \
140 spi_imx->rx_buf += sizeof(type); \
b5f3294f
SH		 141 } \
142}
143
144#define MXC_SPI_BUF_TX(type) \
6cdeb002 145static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
b5f3294f
SH		 146{ \
147 type val = 0; \
148 \
6cdeb002
UKK		 149 if (spi_imx->tx_buf) { \
150 val = *(type *)spi_imx->tx_buf; \
151 spi_imx->tx_buf += sizeof(type); \
b5f3294f
SH		 152 } \
153 \
6cdeb002 154 spi_imx->count -= sizeof(type); \
b5f3294f 155 \
6cdeb002 156 writel(val, spi_imx->base + MXC_CSPITXDATA); \
b5f3294f
SH		 157}
158
159MXC_SPI_BUF_RX(u8)
160MXC_SPI_BUF_TX(u8)
161MXC_SPI_BUF_RX(u16)
162MXC_SPI_BUF_TX(u16)
163MXC_SPI_BUF_RX(u32)
164MXC_SPI_BUF_TX(u32)
165
166/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
167 * (which is currently not the case in this driver)
168 */
169static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
170 256, 384, 512, 768, 1024};
171
172/* MX21, MX27 */
6cdeb002 173static unsigned int spi_imx_clkdiv_1(unsigned int fin,
04ee5854 174 unsigned int fspi, unsigned int max)
b5f3294f 175{
04ee5854 176 int i;
b5f3294f
SH		 177
178 for (i = 2; i < max; i++)
179 if (fspi * mxc_clkdivs[i] >= fin)
180 return i;
181
182 return max;
183}
184
0b599603 185/* MX1, MX31, MX35, MX51 CSPI */
6cdeb002 186static unsigned int spi_imx_clkdiv_2(unsigned int fin,
b5f3294f
SH		 187 unsigned int fspi)
188{
189 int i, div = 4;
190
191 for (i = 0; i < 7; i++) {
192 if (fspi * div >= fin)
193 return i;
194 div <<= 1;
195 }
196
197 return 7;
198}
199
f62caccd
RG		 200static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
201 struct spi_transfer *transfer)
202{
203 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
204
205 if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
206 && (transfer->len > spi_imx->tx_wml))
207 return true;
208 return false;
209}
210
66de757c
SG		 211#define MX51_ECSPI_CTRL 0x08
212#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
213#define MX51_ECSPI_CTRL_XCH (1 << 2)
f62caccd 214#define MX51_ECSPI_CTRL_SMC (1 << 3)
66de757c
SG		 215#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
216#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
217#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
218#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
219#define MX51_ECSPI_CTRL_BL_OFFSET 20
220
221#define MX51_ECSPI_CONFIG 0x0c
222#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
223#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
224#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
225#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
c09b890b 226#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
66de757c
SG		 227
228#define MX51_ECSPI_INT 0x10
229#define MX51_ECSPI_INT_TEEN (1 << 0)
230#define MX51_ECSPI_INT_RREN (1 << 3)
231
f62caccd
RG		 232#define MX51_ECSPI_DMA 0x14
233#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
234#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
235#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
236#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
237#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
238#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
239
240#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
241#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
242#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
243
66de757c
SG		 244#define MX51_ECSPI_STAT 0x18
245#define MX51_ECSPI_STAT_RR (1 << 3)
0b599603
UKK		 246
247/* MX51 eCSPI */
6fd8b850
MV		 248static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
249 unsigned int *fres)
0b599603
UKK		 250{
251 /*
252 * there are two 4-bit dividers, the pre-divider divides by
253 * $pre, the post-divider by 2^$post
254 */
255 unsigned int pre, post;
256
257 if (unlikely(fspi > fin))
258 return 0;
259
260 post = fls(fin) - fls(fspi);
261 if (fin > fspi << post)
262 post++;
263
264 /* now we have: (fin <= fspi << post) with post being minimal */
265
266 post = max(4U, post) - 4;
267 if (unlikely(post > 0xf)) {
268 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
269 __func__, fspi, fin);
270 return 0xff;
271 }
272
273 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
274
275 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
276 __func__, fin, fspi, post, pre);
6fd8b850
MV		 277
278 /* Resulting frequency for the SCLK line. */
279 *fres = (fin / (pre + 1)) >> post;
280
66de757c
SG		 281 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
282 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
0b599603
UKK		 283}
284
66de757c 285static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
0b599603
UKK		 286{
287 unsigned val = 0;
288
289 if (enable & MXC_INT_TE)
66de757c 290 val |= MX51_ECSPI_INT_TEEN;
0b599603
UKK		 291
292 if (enable & MXC_INT_RR)
66de757c 293 val |= MX51_ECSPI_INT_RREN;
0b599603 294
66de757c 295 writel(val, spi_imx->base + MX51_ECSPI_INT);
0b599603
UKK		 296}
297
66de757c 298static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
0b599603 299{
f62caccd
RG		 300 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
301
302 if (!spi_imx->usedma)
303 reg |= MX51_ECSPI_CTRL_XCH;
304 else if (!spi_imx->dma_finished)
305 reg |= MX51_ECSPI_CTRL_SMC;
306 else
307 reg &= ~MX51_ECSPI_CTRL_SMC;
66de757c 308 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
0b599603
UKK		 309}
310
66de757c 311static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
0b599603
UKK		 312 struct spi_imx_config *config)
313{
f62caccd
RG		 314 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
315 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
6fd8b850 316 u32 clk = config->speed_hz, delay;
0b599603 317
f020c39e
SH		 318 /*
319 * The hardware seems to have a race condition when changing modes. The
320 * current assumption is that the selection of the channel arrives
321 * earlier in the hardware than the mode bits when they are written at
322 * the same time.
323 * So set master mode for all channels as we do not support slave mode.
324 */
66de757c 325 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
0b599603
UKK		 326
327 /* set clock speed */
6fd8b850 328 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
0b599603
UKK		 329
330 /* set chip select to use */
66de757c 331 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
0b599603 332
66de757c 333 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
0b599603 334
66de757c 335 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
0b599603
UKK		 336
337 if (config->mode & SPI_CPHA)
66de757c 338 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
0b599603 339
c09b890b 340 if (config->mode & SPI_CPOL) {
66de757c 341 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
c09b890b
KW		 342 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
343 }
0b599603 344 if (config->mode & SPI_CS_HIGH)
66de757c 345 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
0b599603 346
66de757c
SG		 347 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
348 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
0b599603 349
6fd8b850
MV		 350 /*
351 * Wait until the changes in the configuration register CONFIGREG
352 * propagate into the hardware. It takes exactly one tick of the
353 * SCLK clock, but we will wait two SCLK clock just to be sure. The
354 * effect of the delay it takes for the hardware to apply changes
355 * is noticable if the SCLK clock run very slow. In such a case, if
356 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
357 * be asserted before the SCLK polarity changes, which would disrupt
358 * the SPI communication as the device on the other end would consider
359 * the change of SCLK polarity as a clock tick already.
360 */
361 delay = (2 * 1000000) / clk;
362 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
363 udelay(delay);
364 else /* SCLK is _very_ slow */
365 usleep_range(delay, delay + 10);
366
f62caccd
RG		 367 /*
368 * Configure the DMA register: setup the watermark
369 * and enable DMA request.
370 */
371 if (spi_imx->dma_is_inited) {
372 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
373
374 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
375 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
376 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
377 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
378 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
379 rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
380 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
381 & ~MX51_ECSPI_DMA_RX_WML_MASK
382 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
383 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
384 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
385 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
386 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
387
388 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
389 }
390
0b599603
UKK		 391 return 0;
392}
393
66de757c 394static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
0b599603 395{
66de757c 396 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
0b599603
UKK		 397}
398
66de757c 399static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
0b599603
UKK		 400{
401 /* drain receive buffer */
66de757c 402 while (mx51_ecspi_rx_available(spi_imx))
0b599603
UKK		 403 readl(spi_imx->base + MXC_CSPIRXDATA);
404}
405
b5f3294f
SH		 406#define MX31_INTREG_TEEN (1 << 0)
407#define MX31_INTREG_RREN (1 << 3)
408
409#define MX31_CSPICTRL_ENABLE (1 << 0)
410#define MX31_CSPICTRL_MASTER (1 << 1)
411#define MX31_CSPICTRL_XCH (1 << 2)
412#define MX31_CSPICTRL_POL (1 << 4)
413#define MX31_CSPICTRL_PHA (1 << 5)
414#define MX31_CSPICTRL_SSCTL (1 << 6)
415#define MX31_CSPICTRL_SSPOL (1 << 7)
416#define MX31_CSPICTRL_BC_SHIFT 8
417#define MX35_CSPICTRL_BL_SHIFT 20
418#define MX31_CSPICTRL_CS_SHIFT 24
419#define MX35_CSPICTRL_CS_SHIFT 12
420#define MX31_CSPICTRL_DR_SHIFT 16
421
422#define MX31_CSPISTATUS 0x14
423#define MX31_STATUS_RR (1 << 3)
424
425/* These functions also work for the i.MX35, but be aware that
426 * the i.MX35 has a slightly different register layout for bits
427 * we do not use here.
428 */
f4ba6315 429static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 430{
431 unsigned int val = 0;
432
433 if (enable & MXC_INT_TE)
434 val |= MX31_INTREG_TEEN;
435 if (enable & MXC_INT_RR)
436 val |= MX31_INTREG_RREN;
437
6cdeb002 438 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 439}
440
f4ba6315 441static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 442{
443 unsigned int reg;
444
6cdeb002 445 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 446 reg |= MX31_CSPICTRL_XCH;
6cdeb002 447 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 448}
449
2a64a90a 450static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
1723e66b
UKK		 451 struct spi_imx_config *config)
452{
453 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
3b2aa89e 454 int cs = spi_imx->chipselect[config->cs];
1723e66b
UKK		 455
456 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
457 MX31_CSPICTRL_DR_SHIFT;
458
04ee5854 459 if (is_imx35_cspi(spi_imx)) {
2a64a90a
SG		 460 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
461 reg |= MX31_CSPICTRL_SSCTL;
462 } else {
463 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
464 }
1723e66b
UKK		 465
466 if (config->mode & SPI_CPHA)
467 reg |= MX31_CSPICTRL_PHA;
468 if (config->mode & SPI_CPOL)
469 reg |= MX31_CSPICTRL_POL;
470 if (config->mode & SPI_CS_HIGH)
471 reg |= MX31_CSPICTRL_SSPOL;
3b2aa89e 472 if (cs < 0)
2a64a90a 473 reg |= (cs + 32) <<
04ee5854
SG		 474 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
475 MX31_CSPICTRL_CS_SHIFT);
1723e66b
UKK		 476
477 writel(reg, spi_imx->base + MXC_CSPICTRL);
478
479 return 0;
480}
481
f4ba6315 482static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 483{
6cdeb002 484 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
b5f3294f
SH		 485}
486
2a64a90a 487static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 488{
489 /* drain receive buffer */
2a64a90a 490 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
1723e66b
UKK		 491 readl(spi_imx->base + MXC_CSPIRXDATA);
492}
493
3451fb15
SG		 494#define MX21_INTREG_RR (1 << 4)
495#define MX21_INTREG_TEEN (1 << 9)
496#define MX21_INTREG_RREN (1 << 13)
497
498#define MX21_CSPICTRL_POL (1 << 5)
499#define MX21_CSPICTRL_PHA (1 << 6)
500#define MX21_CSPICTRL_SSPOL (1 << 8)
501#define MX21_CSPICTRL_XCH (1 << 9)
502#define MX21_CSPICTRL_ENABLE (1 << 10)
503#define MX21_CSPICTRL_MASTER (1 << 11)
504#define MX21_CSPICTRL_DR_SHIFT 14
505#define MX21_CSPICTRL_CS_SHIFT 19
506
507static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 508{
509 unsigned int val = 0;
510
511 if (enable & MXC_INT_TE)
3451fb15 512 val |= MX21_INTREG_TEEN;
b5f3294f 513 if (enable & MXC_INT_RR)
3451fb15 514 val |= MX21_INTREG_RREN;
b5f3294f 515
6cdeb002 516 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 517}
518
3451fb15 519static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 520{
521 unsigned int reg;
522
6cdeb002 523 reg = readl(spi_imx->base + MXC_CSPICTRL);
3451fb15 524 reg |= MX21_CSPICTRL_XCH;
6cdeb002 525 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 526}
527
3451fb15 528static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
6cdeb002 529 struct spi_imx_config *config)
b5f3294f 530{
3451fb15 531 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
3b2aa89e 532 int cs = spi_imx->chipselect[config->cs];
04ee5854 533 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
b5f3294f 534
04ee5854 535 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
3451fb15 536 MX21_CSPICTRL_DR_SHIFT;
b5f3294f
SH		 537 reg |= config->bpw - 1;
538
539 if (config->mode & SPI_CPHA)
3451fb15 540 reg |= MX21_CSPICTRL_PHA;
b5f3294f 541 if (config->mode & SPI_CPOL)
3451fb15 542 reg |= MX21_CSPICTRL_POL;
b5f3294f 543 if (config->mode & SPI_CS_HIGH)
3451fb15 544 reg |= MX21_CSPICTRL_SSPOL;
3b2aa89e 545 if (cs < 0)
3451fb15 546 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
b5f3294f 547
6cdeb002 548 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 549
550 return 0;
551}
552
3451fb15 553static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 554{
3451fb15 555 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
b5f3294f
SH		 556}
557
3451fb15 558static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 559{
560 writel(1, spi_imx->base + MXC_RESET);
561}
562
b5f3294f
SH		 563#define MX1_INTREG_RR (1 << 3)
564#define MX1_INTREG_TEEN (1 << 8)
565#define MX1_INTREG_RREN (1 << 11)
566
567#define MX1_CSPICTRL_POL (1 << 4)
568#define MX1_CSPICTRL_PHA (1 << 5)
569#define MX1_CSPICTRL_XCH (1 << 8)
570#define MX1_CSPICTRL_ENABLE (1 << 9)
571#define MX1_CSPICTRL_MASTER (1 << 10)
572#define MX1_CSPICTRL_DR_SHIFT 13
573
f4ba6315 574static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 575{
576 unsigned int val = 0;
577
578 if (enable & MXC_INT_TE)
579 val |= MX1_INTREG_TEEN;
580 if (enable & MXC_INT_RR)
581 val |= MX1_INTREG_RREN;
582
6cdeb002 583 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 584}
585
f4ba6315 586static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 587{
588 unsigned int reg;
589
6cdeb002 590 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 591 reg |= MX1_CSPICTRL_XCH;
6cdeb002 592 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 593}
594
f4ba6315 595static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
6cdeb002 596 struct spi_imx_config *config)
b5f3294f
SH		 597{
598 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
599
6cdeb002 600 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 601 MX1_CSPICTRL_DR_SHIFT;
602 reg |= config->bpw - 1;
603
604 if (config->mode & SPI_CPHA)
605 reg |= MX1_CSPICTRL_PHA;
606 if (config->mode & SPI_CPOL)
607 reg |= MX1_CSPICTRL_POL;
608
6cdeb002 609 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 610
611 return 0;
612}
613
f4ba6315 614static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 615{
6cdeb002 616 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
b5f3294f
SH		 617}
618
1723e66b
UKK		 619static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
620{
621 writel(1, spi_imx->base + MXC_RESET);
622}
623
04ee5854
SG		 624static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
625 .intctrl = mx1_intctrl,
626 .config = mx1_config,
627 .trigger = mx1_trigger,
628 .rx_available = mx1_rx_available,
629 .reset = mx1_reset,
630 .devtype = IMX1_CSPI,
631};
632
633static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
634 .intctrl = mx21_intctrl,
635 .config = mx21_config,
636 .trigger = mx21_trigger,
637 .rx_available = mx21_rx_available,
638 .reset = mx21_reset,
639 .devtype = IMX21_CSPI,
640};
641
642static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
643 /* i.mx27 cspi shares the functions with i.mx21 one */
644 .intctrl = mx21_intctrl,
645 .config = mx21_config,
646 .trigger = mx21_trigger,
647 .rx_available = mx21_rx_available,
648 .reset = mx21_reset,
649 .devtype = IMX27_CSPI,
650};
651
652static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
653 .intctrl = mx31_intctrl,
654 .config = mx31_config,
655 .trigger = mx31_trigger,
656 .rx_available = mx31_rx_available,
657 .reset = mx31_reset,
658 .devtype = IMX31_CSPI,
659};
660
661static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
662 /* i.mx35 and later cspi shares the functions with i.mx31 one */
663 .intctrl = mx31_intctrl,
664 .config = mx31_config,
665 .trigger = mx31_trigger,
666 .rx_available = mx31_rx_available,
667 .reset = mx31_reset,
668 .devtype = IMX35_CSPI,
669};
670
671static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
672 .intctrl = mx51_ecspi_intctrl,
673 .config = mx51_ecspi_config,
674 .trigger = mx51_ecspi_trigger,
675 .rx_available = mx51_ecspi_rx_available,
676 .reset = mx51_ecspi_reset,
677 .devtype = IMX51_ECSPI,
678};
679
680static struct platform_device_id spi_imx_devtype[] = {
681 {
682 .name = "imx1-cspi",
683 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
684 }, {
685 .name = "imx21-cspi",
686 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
687 }, {
688 .name = "imx27-cspi",
689 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
690 }, {
691 .name = "imx31-cspi",
692 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
693 }, {
694 .name = "imx35-cspi",
695 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
696 }, {
697 .name = "imx51-ecspi",
698 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
699 }, {
700 /* sentinel */
701 }
f4ba6315
UKK		 702};
703
22a85e4c
SG		 704static const struct of_device_id spi_imx_dt_ids[] = {
705 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
706 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
707 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
708 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
709 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
710 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
711 { /* sentinel */ }
712};
27743e0b 713MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
22a85e4c 714
6cdeb002 715static void spi_imx_chipselect(struct spi_device *spi, int is_active)
b5f3294f 716{
6cdeb002 717 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
6cdeb002 718 int gpio = spi_imx->chipselect[spi->chip_select];
e6a0a8bf
UKK		 719 int active = is_active != BITBANG_CS_INACTIVE;
720 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
b5f3294f 721
8b17e055 722 if (!gpio_is_valid(gpio))
b5f3294f 723 return;
b5f3294f 724
e6a0a8bf 725 gpio_set_value(gpio, dev_is_lowactive ^ active);
b5f3294f
SH		 726}
727
6cdeb002 728static void spi_imx_push(struct spi_imx_data *spi_imx)
b5f3294f 729{
04ee5854 730 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
6cdeb002 731 if (!spi_imx->count)
b5f3294f 732 break;
6cdeb002
UKK		 733 spi_imx->tx(spi_imx);
734 spi_imx->txfifo++;
b5f3294f
SH		 735 }
736
edd501bb 737 spi_imx->devtype_data->trigger(spi_imx);
b5f3294f
SH		 738}
739
6cdeb002 740static irqreturn_t spi_imx_isr(int irq, void *dev_id)
b5f3294f 741{
6cdeb002 742 struct spi_imx_data *spi_imx = dev_id;
b5f3294f 743
edd501bb 744 while (spi_imx->devtype_data->rx_available(spi_imx)) {
6cdeb002
UKK		 745 spi_imx->rx(spi_imx);
746 spi_imx->txfifo--;
b5f3294f
SH		 747 }
748
6cdeb002
UKK		 749 if (spi_imx->count) {
750 spi_imx_push(spi_imx);
b5f3294f
SH		 751 return IRQ_HANDLED;
752 }
753
6cdeb002 754 if (spi_imx->txfifo) {
b5f3294f
SH		 755 /* No data left to push, but still waiting for rx data,
756 * enable receive data available interrupt.
757 */
edd501bb 758 spi_imx->devtype_data->intctrl(
f4ba6315 759 spi_imx, MXC_INT_RR);
b5f3294f
SH		 760 return IRQ_HANDLED;
761 }
762
edd501bb 763 spi_imx->devtype_data->intctrl(spi_imx, 0);
6cdeb002 764 complete(&spi_imx->xfer_done);
b5f3294f
SH		 765
766 return IRQ_HANDLED;
767}
768
6cdeb002 769static int spi_imx_setupxfer(struct spi_device *spi,
b5f3294f
SH		 770 struct spi_transfer *t)
771{
6cdeb002
UKK		 772 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
773 struct spi_imx_config config;
b5f3294f
SH		 774
775 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
776 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
777 config.mode = spi->mode;
3b2aa89e 778 config.cs = spi->chip_select;
b5f3294f 779
462d26b5
SH		 780 if (!config.speed_hz)
781 config.speed_hz = spi->max_speed_hz;
782 if (!config.bpw)
783 config.bpw = spi->bits_per_word;
462d26b5 784
e6a0a8bf
UKK		 785 /* Initialize the functions for transfer */
786 if (config.bpw <= 8) {
787 spi_imx->rx = spi_imx_buf_rx_u8;
788 spi_imx->tx = spi_imx_buf_tx_u8;
789 } else if (config.bpw <= 16) {
790 spi_imx->rx = spi_imx_buf_rx_u16;
791 spi_imx->tx = spi_imx_buf_tx_u16;
6051426f 792 } else {
e6a0a8bf
UKK		 793 spi_imx->rx = spi_imx_buf_rx_u32;
794 spi_imx->tx = spi_imx_buf_tx_u32;
24778be2 795 }
e6a0a8bf 796
edd501bb 797 spi_imx->devtype_data->config(spi_imx, &config);
b5f3294f
SH		 798
799 return 0;
800}
801
f62caccd
RG		 802static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
803{
804 struct spi_master *master = spi_imx->bitbang.master;
805
806 if (master->dma_rx) {
807 dma_release_channel(master->dma_rx);
808 master->dma_rx = NULL;
809 }
810
811 if (master->dma_tx) {
812 dma_release_channel(master->dma_tx);
813 master->dma_tx = NULL;
814 }
815
816 spi_imx->dma_is_inited = 0;
817}
818
819static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
820 struct spi_master *master,
821 const struct resource *res)
822{
823 struct dma_slave_config slave_config = {};
824 int ret;
825
826 /* Prepare for TX DMA: */
827 master->dma_tx = dma_request_slave_channel(dev, "tx");
828 if (!master->dma_tx) {
829 dev_err(dev, "cannot get the TX DMA channel!\n");
830 ret = -EINVAL;
831 goto err;
832 }
833
834 slave_config.direction = DMA_MEM_TO_DEV;
835 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
836 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
837 slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
838 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
839 if (ret) {
840 dev_err(dev, "error in TX dma configuration.\n");
841 goto err;
842 }
843
844 /* Prepare for RX : */
845 master->dma_rx = dma_request_slave_channel(dev, "rx");
846 if (!master->dma_rx) {
847 dev_dbg(dev, "cannot get the DMA channel.\n");
848 ret = -EINVAL;
849 goto err;
850 }
851
852 slave_config.direction = DMA_DEV_TO_MEM;
853 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
854 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
855 slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
856 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
857 if (ret) {
858 dev_err(dev, "error in RX dma configuration.\n");
859 goto err;
860 }
861
862 init_completion(&spi_imx->dma_rx_completion);
863 init_completion(&spi_imx->dma_tx_completion);
864 master->can_dma = spi_imx_can_dma;
865 master->max_dma_len = MAX_SDMA_BD_BYTES;
866 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
867 SPI_MASTER_MUST_TX;
868 spi_imx->dma_is_inited = 1;
869
870 return 0;
871err:
872 spi_imx_sdma_exit(spi_imx);
873 return ret;
874}
875
876static void spi_imx_dma_rx_callback(void *cookie)
877{
878 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
879
880 complete(&spi_imx->dma_rx_completion);
881}
882
883static void spi_imx_dma_tx_callback(void *cookie)
884{
885 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
886
887 complete(&spi_imx->dma_tx_completion);
888}
889
890static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
891 struct spi_transfer *transfer)
892{
893 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
894 int ret;
895 u32 dma;
896 int left;
897 struct spi_master *master = spi_imx->bitbang.master;
898 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
899
900 if (tx) {
901 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
902 tx->sgl, tx->nents, DMA_TO_DEVICE,
903 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
904 if (!desc_tx)
905 goto no_dma;
906
907 desc_tx->callback = spi_imx_dma_tx_callback;
908 desc_tx->callback_param = (void *)spi_imx;
909 dmaengine_submit(desc_tx);
910 }
911
912 if (rx) {
913 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
914 rx->sgl, rx->nents, DMA_FROM_DEVICE,
915 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
916 if (!desc_rx)
917 goto no_dma;
918
919 desc_rx->callback = spi_imx_dma_rx_callback;
920 desc_rx->callback_param = (void *)spi_imx;
921 dmaengine_submit(desc_rx);
922 }
923
924 reinit_completion(&spi_imx->dma_rx_completion);
925 reinit_completion(&spi_imx->dma_tx_completion);
926
927 /* Trigger the cspi module. */
928 spi_imx->dma_finished = 0;
929
930 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
931 dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
932 /* Change RX_DMA_LENGTH trigger dma fetch tail data */
933 left = transfer->len % spi_imx->rxt_wml;
934 if (left)
935 writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
936 spi_imx->base + MX51_ECSPI_DMA);
937 spi_imx->devtype_data->trigger(spi_imx);
938
939 dma_async_issue_pending(master->dma_tx);
940 dma_async_issue_pending(master->dma_rx);
941 /* Wait SDMA to finish the data transfer.*/
942 ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
943 IMX_DMA_TIMEOUT);
944 if (!ret) {
945 pr_warn("%s %s: I/O Error in DMA TX\n",
946 dev_driver_string(&master->dev),
947 dev_name(&master->dev));
948 dmaengine_terminate_all(master->dma_tx);
949 } else {
950 ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
951 IMX_DMA_TIMEOUT);
952 if (!ret) {
953 pr_warn("%s %s: I/O Error in DMA RX\n",
954 dev_driver_string(&master->dev),
955 dev_name(&master->dev));
956 spi_imx->devtype_data->reset(spi_imx);
957 dmaengine_terminate_all(master->dma_rx);
958 }
959 writel(dma |
960 spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
961 spi_imx->base + MX51_ECSPI_DMA);
962 }
963
964 spi_imx->dma_finished = 1;
965 spi_imx->devtype_data->trigger(spi_imx);
966
967 if (!ret)
968 ret = -ETIMEDOUT;
969 else if (ret > 0)
970 ret = transfer->len;
971
972 return ret;
973
974no_dma:
975 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
976 dev_driver_string(&master->dev),
977 dev_name(&master->dev));
978 return -EAGAIN;
979}
980
981static int spi_imx_pio_transfer(struct spi_device *spi,
b5f3294f
SH		 982 struct spi_transfer *transfer)
983{
6cdeb002 984 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
b5f3294f 985
6cdeb002
UKK		 986 spi_imx->tx_buf = transfer->tx_buf;
987 spi_imx->rx_buf = transfer->rx_buf;
988 spi_imx->count = transfer->len;
989 spi_imx->txfifo = 0;
b5f3294f 990
aa0fe826 991 reinit_completion(&spi_imx->xfer_done);
b5f3294f 992
6cdeb002 993 spi_imx_push(spi_imx);
b5f3294f 994
edd501bb 995 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
b5f3294f 996
6cdeb002 997 wait_for_completion(&spi_imx->xfer_done);
b5f3294f
SH		 998
999 return transfer->len;
1000}
1001
f62caccd
RG		 1002static int spi_imx_transfer(struct spi_device *spi,
1003 struct spi_transfer *transfer)
1004{
1005 int ret;
1006 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1007
1008 if (spi_imx->bitbang.master->can_dma &&
1009 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1010 spi_imx->usedma = true;
1011 ret = spi_imx_dma_transfer(spi_imx, transfer);
1012 if (ret != -EAGAIN)
1013 return ret;
1014 }
1015 spi_imx->usedma = false;
1016
1017 return spi_imx_pio_transfer(spi, transfer);
1018}
1019
6cdeb002 1020static int spi_imx_setup(struct spi_device *spi)
b5f3294f 1021{
6c23e5d4
SH		 1022 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1023 int gpio = spi_imx->chipselect[spi->chip_select];
1024
f4d4ecfe 1025 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
b5f3294f
SH		 1026 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1027
8b17e055 1028 if (gpio_is_valid(gpio))
6c23e5d4
SH		 1029 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1030
6cdeb002 1031 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
b5f3294f
SH		 1032
1033 return 0;
1034}
1035
6cdeb002 1036static void spi_imx_cleanup(struct spi_device *spi)
b5f3294f
SH		 1037{
1038}
1039
9e556dcc
HS		 1040static int
1041spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1042{
1043 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1044 int ret;
1045
1046 ret = clk_enable(spi_imx->clk_per);
1047 if (ret)
1048 return ret;
1049
1050 ret = clk_enable(spi_imx->clk_ipg);
1051 if (ret) {
1052 clk_disable(spi_imx->clk_per);
1053 return ret;
1054 }
1055
1056 return 0;
1057}
1058
1059static int
1060spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1061{
1062 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1063
1064 clk_disable(spi_imx->clk_ipg);
1065 clk_disable(spi_imx->clk_per);
1066 return 0;
1067}
1068
fd4a319b 1069static int spi_imx_probe(struct platform_device *pdev)
b5f3294f 1070{
22a85e4c
SG		 1071 struct device_node *np = pdev->dev.of_node;
1072 const struct of_device_id *of_id =
1073 of_match_device(spi_imx_dt_ids, &pdev->dev);
1074 struct spi_imx_master *mxc_platform_info =
1075 dev_get_platdata(&pdev->dev);
b5f3294f 1076 struct spi_master *master;
6cdeb002 1077 struct spi_imx_data *spi_imx;
b5f3294f 1078 struct resource *res;
c2387cb9 1079 int i, ret, num_cs;
b5f3294f 1080
22a85e4c 1081 if (!np && !mxc_platform_info) {
b5f3294f
SH		 1082 dev_err(&pdev->dev, "can't get the platform data\n");
1083 return -EINVAL;
1084 }
1085
22a85e4c 1086 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
39ec0d38
LW		 1087 if (ret < 0) {
1088 if (mxc_platform_info)
1089 num_cs = mxc_platform_info->num_chipselect;
1090 else
1091 return ret;
1092 }
22a85e4c 1093
c2387cb9
SG		 1094 master = spi_alloc_master(&pdev->dev,
1095 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
b5f3294f
SH		 1096 if (!master)
1097 return -ENOMEM;
1098
1099 platform_set_drvdata(pdev, master);
1100
24778be2 1101 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
b5f3294f 1102 master->bus_num = pdev->id;
c2387cb9 1103 master->num_chipselect = num_cs;
b5f3294f 1104
6cdeb002 1105 spi_imx = spi_master_get_devdata(master);
94c69f76 1106 spi_imx->bitbang.master = master;
b5f3294f
SH		 1107
1108 for (i = 0; i < master->num_chipselect; i++) {
22a85e4c 1109 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
8b17e055 1110 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
22a85e4c 1111 cs_gpio = mxc_platform_info->chipselect[i];
4cc122ac
FE		 1112
1113 spi_imx->chipselect[i] = cs_gpio;
8b17e055 1114 if (!gpio_is_valid(cs_gpio))
b5f3294f 1115 continue;
4cc122ac 1116
130b82c0
FE		 1117 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1118 DRIVER_NAME);
b5f3294f 1119 if (ret) {
bbd050af 1120 dev_err(&pdev->dev, "can't get cs gpios\n");
130b82c0 1121 goto out_master_put;
b5f3294f 1122 }
b5f3294f
SH		 1123 }
1124
6cdeb002
UKK		 1125 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1126 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1127 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1128 spi_imx->bitbang.master->setup = spi_imx_setup;
1129 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
9e556dcc
HS		 1130 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1131 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
3910f2cf 1132 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
b5f3294f 1133
6cdeb002 1134 init_completion(&spi_imx->xfer_done);
b5f3294f 1135
22a85e4c 1136 spi_imx->devtype_data = of_id ? of_id->data :
04ee5854 1137 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
f4ba6315 1138
b5f3294f 1139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130b82c0
FE		 1140 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1141 if (IS_ERR(spi_imx->base)) {
1142 ret = PTR_ERR(spi_imx->base);
1143 goto out_master_put;
b5f3294f
SH		 1144 }
1145
6cdeb002 1146 spi_imx->irq = platform_get_irq(pdev, 0);
73575938 1147 if (spi_imx->irq < 0) {
82106e0e 1148 ret = spi_imx->irq;
130b82c0 1149 goto out_master_put;
b5f3294f
SH		 1150 }
1151
130b82c0 1152 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
8fc39b51 1153 dev_name(&pdev->dev), spi_imx);
b5f3294f 1154 if (ret) {
6cdeb002 1155 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
130b82c0 1156 goto out_master_put;
b5f3294f
SH		 1157 }
1158
aa29d840
SH		 1159 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1160 if (IS_ERR(spi_imx->clk_ipg)) {
1161 ret = PTR_ERR(spi_imx->clk_ipg);
130b82c0 1162 goto out_master_put;
b5f3294f
SH		 1163 }
1164
aa29d840
SH		 1165 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1166 if (IS_ERR(spi_imx->clk_per)) {
1167 ret = PTR_ERR(spi_imx->clk_per);
130b82c0 1168 goto out_master_put;
aa29d840
SH		 1169 }
1170
83174626
FE		 1171 ret = clk_prepare_enable(spi_imx->clk_per);
1172 if (ret)
1173 goto out_master_put;
1174
1175 ret = clk_prepare_enable(spi_imx->clk_ipg);
1176 if (ret)
1177 goto out_put_per;
aa29d840
SH		 1178
1179 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
f62caccd
RG		 1180 /*
1181 * Only validated on i.mx6 now, can remove the constrain if validated on
1182 * other chips.
1183 */
1184 if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
1185 && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
1186 dev_err(&pdev->dev, "dma setup error,use pio instead\n");
b5f3294f 1187
edd501bb 1188 spi_imx->devtype_data->reset(spi_imx);
ce1807b2 1189
edd501bb 1190 spi_imx->devtype_data->intctrl(spi_imx, 0);
b5f3294f 1191
22a85e4c 1192 master->dev.of_node = pdev->dev.of_node;
6cdeb002 1193 ret = spi_bitbang_start(&spi_imx->bitbang);
b5f3294f
SH		 1194 if (ret) {
1195 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1196 goto out_clk_put;
1197 }
1198
1199 dev_info(&pdev->dev, "probed\n");
1200
9e556dcc
HS		 1201 clk_disable(spi_imx->clk_ipg);
1202 clk_disable(spi_imx->clk_per);
b5f3294f
SH		 1203 return ret;
1204
1205out_clk_put:
aa29d840 1206 clk_disable_unprepare(spi_imx->clk_ipg);
83174626
FE		 1207out_put_per:
1208 clk_disable_unprepare(spi_imx->clk_per);
130b82c0 1209out_master_put:
b5f3294f 1210 spi_master_put(master);
130b82c0 1211
b5f3294f
SH		 1212 return ret;
1213}
1214
fd4a319b 1215static int spi_imx_remove(struct platform_device *pdev)
b5f3294f
SH		 1216{
1217 struct spi_master *master = platform_get_drvdata(pdev);
6cdeb002 1218 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
b5f3294f 1219
6cdeb002 1220 spi_bitbang_stop(&spi_imx->bitbang);
b5f3294f 1221
6cdeb002 1222 writel(0, spi_imx->base + MXC_CSPICTRL);
fd40dccb
PDM		 1223 clk_unprepare(spi_imx->clk_ipg);
1224 clk_unprepare(spi_imx->clk_per);
f62caccd 1225 spi_imx_sdma_exit(spi_imx);
b5f3294f
SH		 1226 spi_master_put(master);
1227
b5f3294f
SH		 1228 return 0;
1229}
1230
6cdeb002 1231static struct platform_driver spi_imx_driver = {
b5f3294f
SH		 1232 .driver = {
1233 .name = DRIVER_NAME,
1234 .owner = THIS_MODULE,
22a85e4c 1235 .of_match_table = spi_imx_dt_ids,
b5f3294f 1236 },
f4ba6315 1237 .id_table = spi_imx_devtype,
6cdeb002 1238 .probe = spi_imx_probe,
fd4a319b 1239 .remove = spi_imx_remove,
b5f3294f 1240};
940ab889 1241module_platform_driver(spi_imx_driver);
b5f3294f
SH		 1242
1243MODULE_DESCRIPTION("SPI Master Controller driver");
1244MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1245MODULE_LICENSE("GPL");
3133fba3 1246MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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