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b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/gpio.h> | |
b5f3294f SH |
26 | #include <linux/interrupt.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/platform_device.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b5f3294f SH |
33 | #include <linux/spi/spi.h> |
34 | #include <linux/spi/spi_bitbang.h> | |
35 | #include <linux/types.h> | |
22a85e4c SG |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
38 | #include <linux/of_gpio.h> | |
b5f3294f | 39 | |
82906b13 | 40 | #include <linux/platform_data/spi-imx.h> |
b5f3294f SH |
41 | |
42 | #define DRIVER_NAME "spi_imx" | |
43 | ||
44 | #define MXC_CSPIRXDATA 0x00 | |
45 | #define MXC_CSPITXDATA 0x04 | |
46 | #define MXC_CSPICTRL 0x08 | |
47 | #define MXC_CSPIINT 0x0c | |
48 | #define MXC_RESET 0x1c | |
49 | ||
50 | /* generic defines to abstract from the different register layouts */ | |
51 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
52 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
53 | ||
6cdeb002 | 54 | struct spi_imx_config { |
b5f3294f SH |
55 | unsigned int speed_hz; |
56 | unsigned int bpw; | |
57 | unsigned int mode; | |
3b2aa89e | 58 | u8 cs; |
b5f3294f SH |
59 | }; |
60 | ||
f4ba6315 | 61 | enum spi_imx_devtype { |
04ee5854 SG |
62 | IMX1_CSPI, |
63 | IMX21_CSPI, | |
64 | IMX27_CSPI, | |
65 | IMX31_CSPI, | |
66 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
67 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | |
f4ba6315 UKK |
68 | }; |
69 | ||
70 | struct spi_imx_data; | |
71 | ||
72 | struct spi_imx_devtype_data { | |
73 | void (*intctrl)(struct spi_imx_data *, int); | |
74 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
75 | void (*trigger)(struct spi_imx_data *); | |
76 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 77 | void (*reset)(struct spi_imx_data *); |
04ee5854 | 78 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
79 | }; |
80 | ||
6cdeb002 | 81 | struct spi_imx_data { |
b5f3294f SH |
82 | struct spi_bitbang bitbang; |
83 | ||
84 | struct completion xfer_done; | |
cc4d22ae | 85 | void __iomem *base; |
b5f3294f | 86 | int irq; |
aa29d840 SH |
87 | struct clk *clk_per; |
88 | struct clk *clk_ipg; | |
b5f3294f | 89 | unsigned long spi_clk; |
b5f3294f SH |
90 | |
91 | unsigned int count; | |
6cdeb002 UKK |
92 | void (*tx)(struct spi_imx_data *); |
93 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
94 | void *rx_buf; |
95 | const void *tx_buf; | |
96 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
97 | ||
80023cb3 | 98 | const struct spi_imx_devtype_data *devtype_data; |
c2387cb9 | 99 | int chipselect[0]; |
b5f3294f SH |
100 | }; |
101 | ||
04ee5854 SG |
102 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
103 | { | |
104 | return d->devtype_data->devtype == IMX27_CSPI; | |
105 | } | |
106 | ||
107 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
108 | { | |
109 | return d->devtype_data->devtype == IMX35_CSPI; | |
110 | } | |
111 | ||
112 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) | |
113 | { | |
114 | return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8; | |
115 | } | |
116 | ||
b5f3294f | 117 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 118 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 119 | { \ |
6cdeb002 | 120 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 121 | \ |
6cdeb002 UKK |
122 | if (spi_imx->rx_buf) { \ |
123 | *(type *)spi_imx->rx_buf = val; \ | |
124 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
125 | } \ |
126 | } | |
127 | ||
128 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 129 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
130 | { \ |
131 | type val = 0; \ | |
132 | \ | |
6cdeb002 UKK |
133 | if (spi_imx->tx_buf) { \ |
134 | val = *(type *)spi_imx->tx_buf; \ | |
135 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
136 | } \ |
137 | \ | |
6cdeb002 | 138 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 139 | \ |
6cdeb002 | 140 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
141 | } |
142 | ||
143 | MXC_SPI_BUF_RX(u8) | |
144 | MXC_SPI_BUF_TX(u8) | |
145 | MXC_SPI_BUF_RX(u16) | |
146 | MXC_SPI_BUF_TX(u16) | |
147 | MXC_SPI_BUF_RX(u32) | |
148 | MXC_SPI_BUF_TX(u32) | |
149 | ||
150 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
151 | * (which is currently not the case in this driver) | |
152 | */ | |
153 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
154 | 256, 384, 512, 768, 1024}; | |
155 | ||
156 | /* MX21, MX27 */ | |
6cdeb002 | 157 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
04ee5854 | 158 | unsigned int fspi, unsigned int max) |
b5f3294f | 159 | { |
04ee5854 | 160 | int i; |
b5f3294f SH |
161 | |
162 | for (i = 2; i < max; i++) | |
163 | if (fspi * mxc_clkdivs[i] >= fin) | |
164 | return i; | |
165 | ||
166 | return max; | |
167 | } | |
168 | ||
0b599603 | 169 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 170 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
171 | unsigned int fspi) |
172 | { | |
173 | int i, div = 4; | |
174 | ||
175 | for (i = 0; i < 7; i++) { | |
176 | if (fspi * div >= fin) | |
177 | return i; | |
178 | div <<= 1; | |
179 | } | |
180 | ||
181 | return 7; | |
182 | } | |
183 | ||
66de757c SG |
184 | #define MX51_ECSPI_CTRL 0x08 |
185 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
186 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
187 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) | |
188 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 | |
189 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
190 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
191 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
192 | ||
193 | #define MX51_ECSPI_CONFIG 0x0c | |
194 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
195 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
196 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
197 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
c09b890b | 198 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
66de757c SG |
199 | |
200 | #define MX51_ECSPI_INT 0x10 | |
201 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
202 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
203 | ||
204 | #define MX51_ECSPI_STAT 0x18 | |
205 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 UKK |
206 | |
207 | /* MX51 eCSPI */ | |
6fd8b850 MV |
208 | static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi, |
209 | unsigned int *fres) | |
0b599603 UKK |
210 | { |
211 | /* | |
212 | * there are two 4-bit dividers, the pre-divider divides by | |
213 | * $pre, the post-divider by 2^$post | |
214 | */ | |
215 | unsigned int pre, post; | |
216 | ||
217 | if (unlikely(fspi > fin)) | |
218 | return 0; | |
219 | ||
220 | post = fls(fin) - fls(fspi); | |
221 | if (fin > fspi << post) | |
222 | post++; | |
223 | ||
224 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
225 | ||
226 | post = max(4U, post) - 4; | |
227 | if (unlikely(post > 0xf)) { | |
228 | pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", | |
229 | __func__, fspi, fin); | |
230 | return 0xff; | |
231 | } | |
232 | ||
233 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
234 | ||
235 | pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", | |
236 | __func__, fin, fspi, post, pre); | |
6fd8b850 MV |
237 | |
238 | /* Resulting frequency for the SCLK line. */ | |
239 | *fres = (fin / (pre + 1)) >> post; | |
240 | ||
66de757c SG |
241 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
242 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
243 | } |
244 | ||
66de757c | 245 | static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
246 | { |
247 | unsigned val = 0; | |
248 | ||
249 | if (enable & MXC_INT_TE) | |
66de757c | 250 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
251 | |
252 | if (enable & MXC_INT_RR) | |
66de757c | 253 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 254 | |
66de757c | 255 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
256 | } |
257 | ||
66de757c | 258 | static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 UKK |
259 | { |
260 | u32 reg; | |
261 | ||
66de757c SG |
262 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
263 | reg |= MX51_ECSPI_CTRL_XCH; | |
264 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 UKK |
265 | } |
266 | ||
66de757c | 267 | static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, |
0b599603 UKK |
268 | struct spi_imx_config *config) |
269 | { | |
66de757c | 270 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; |
6fd8b850 | 271 | u32 clk = config->speed_hz, delay; |
0b599603 | 272 | |
f020c39e SH |
273 | /* |
274 | * The hardware seems to have a race condition when changing modes. The | |
275 | * current assumption is that the selection of the channel arrives | |
276 | * earlier in the hardware than the mode bits when they are written at | |
277 | * the same time. | |
278 | * So set master mode for all channels as we do not support slave mode. | |
279 | */ | |
66de757c | 280 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
0b599603 UKK |
281 | |
282 | /* set clock speed */ | |
6fd8b850 | 283 | ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk); |
0b599603 UKK |
284 | |
285 | /* set chip select to use */ | |
66de757c | 286 | ctrl |= MX51_ECSPI_CTRL_CS(config->cs); |
0b599603 | 287 | |
66de757c | 288 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
0b599603 | 289 | |
66de757c | 290 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); |
0b599603 UKK |
291 | |
292 | if (config->mode & SPI_CPHA) | |
66de757c | 293 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
0b599603 | 294 | |
c09b890b | 295 | if (config->mode & SPI_CPOL) { |
66de757c | 296 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
c09b890b KW |
297 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); |
298 | } | |
0b599603 | 299 | if (config->mode & SPI_CS_HIGH) |
66de757c | 300 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
0b599603 | 301 | |
66de757c SG |
302 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); |
303 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); | |
0b599603 | 304 | |
6fd8b850 MV |
305 | /* |
306 | * Wait until the changes in the configuration register CONFIGREG | |
307 | * propagate into the hardware. It takes exactly one tick of the | |
308 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
309 | * effect of the delay it takes for the hardware to apply changes | |
310 | * is noticable if the SCLK clock run very slow. In such a case, if | |
311 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
312 | * be asserted before the SCLK polarity changes, which would disrupt | |
313 | * the SPI communication as the device on the other end would consider | |
314 | * the change of SCLK polarity as a clock tick already. | |
315 | */ | |
316 | delay = (2 * 1000000) / clk; | |
317 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ | |
318 | udelay(delay); | |
319 | else /* SCLK is _very_ slow */ | |
320 | usleep_range(delay, delay + 10); | |
321 | ||
0b599603 UKK |
322 | return 0; |
323 | } | |
324 | ||
66de757c | 325 | static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 326 | { |
66de757c | 327 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
328 | } |
329 | ||
66de757c | 330 | static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
331 | { |
332 | /* drain receive buffer */ | |
66de757c | 333 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
334 | readl(spi_imx->base + MXC_CSPIRXDATA); |
335 | } | |
336 | ||
b5f3294f SH |
337 | #define MX31_INTREG_TEEN (1 << 0) |
338 | #define MX31_INTREG_RREN (1 << 3) | |
339 | ||
340 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
341 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
342 | #define MX31_CSPICTRL_XCH (1 << 2) | |
343 | #define MX31_CSPICTRL_POL (1 << 4) | |
344 | #define MX31_CSPICTRL_PHA (1 << 5) | |
345 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
346 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
347 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
348 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
349 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
350 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
351 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
352 | ||
353 | #define MX31_CSPISTATUS 0x14 | |
354 | #define MX31_STATUS_RR (1 << 3) | |
355 | ||
356 | /* These functions also work for the i.MX35, but be aware that | |
357 | * the i.MX35 has a slightly different register layout for bits | |
358 | * we do not use here. | |
359 | */ | |
f4ba6315 | 360 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
361 | { |
362 | unsigned int val = 0; | |
363 | ||
364 | if (enable & MXC_INT_TE) | |
365 | val |= MX31_INTREG_TEEN; | |
366 | if (enable & MXC_INT_RR) | |
367 | val |= MX31_INTREG_RREN; | |
368 | ||
6cdeb002 | 369 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
370 | } |
371 | ||
f4ba6315 | 372 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
373 | { |
374 | unsigned int reg; | |
375 | ||
6cdeb002 | 376 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 377 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 378 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
379 | } |
380 | ||
2a64a90a | 381 | static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, |
1723e66b UKK |
382 | struct spi_imx_config *config) |
383 | { | |
384 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 385 | int cs = spi_imx->chipselect[config->cs]; |
1723e66b UKK |
386 | |
387 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << | |
388 | MX31_CSPICTRL_DR_SHIFT; | |
389 | ||
04ee5854 | 390 | if (is_imx35_cspi(spi_imx)) { |
2a64a90a SG |
391 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
392 | reg |= MX31_CSPICTRL_SSCTL; | |
393 | } else { | |
394 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
395 | } | |
1723e66b UKK |
396 | |
397 | if (config->mode & SPI_CPHA) | |
398 | reg |= MX31_CSPICTRL_PHA; | |
399 | if (config->mode & SPI_CPOL) | |
400 | reg |= MX31_CSPICTRL_POL; | |
401 | if (config->mode & SPI_CS_HIGH) | |
402 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e | 403 | if (cs < 0) |
2a64a90a | 404 | reg |= (cs + 32) << |
04ee5854 SG |
405 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
406 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b UKK |
407 | |
408 | writel(reg, spi_imx->base + MXC_CSPICTRL); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
f4ba6315 | 413 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 414 | { |
6cdeb002 | 415 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
416 | } |
417 | ||
2a64a90a | 418 | static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
419 | { |
420 | /* drain receive buffer */ | |
2a64a90a | 421 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
422 | readl(spi_imx->base + MXC_CSPIRXDATA); |
423 | } | |
424 | ||
3451fb15 SG |
425 | #define MX21_INTREG_RR (1 << 4) |
426 | #define MX21_INTREG_TEEN (1 << 9) | |
427 | #define MX21_INTREG_RREN (1 << 13) | |
428 | ||
429 | #define MX21_CSPICTRL_POL (1 << 5) | |
430 | #define MX21_CSPICTRL_PHA (1 << 6) | |
431 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
432 | #define MX21_CSPICTRL_XCH (1 << 9) | |
433 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
434 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
435 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
436 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
437 | ||
438 | static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) | |
b5f3294f SH |
439 | { |
440 | unsigned int val = 0; | |
441 | ||
442 | if (enable & MXC_INT_TE) | |
3451fb15 | 443 | val |= MX21_INTREG_TEEN; |
b5f3294f | 444 | if (enable & MXC_INT_RR) |
3451fb15 | 445 | val |= MX21_INTREG_RREN; |
b5f3294f | 446 | |
6cdeb002 | 447 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
448 | } |
449 | ||
3451fb15 | 450 | static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
451 | { |
452 | unsigned int reg; | |
453 | ||
6cdeb002 | 454 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 455 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 456 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
457 | } |
458 | ||
3451fb15 | 459 | static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 460 | struct spi_imx_config *config) |
b5f3294f | 461 | { |
3451fb15 | 462 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
3b2aa89e | 463 | int cs = spi_imx->chipselect[config->cs]; |
04ee5854 | 464 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
b5f3294f | 465 | |
04ee5854 | 466 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << |
3451fb15 | 467 | MX21_CSPICTRL_DR_SHIFT; |
b5f3294f SH |
468 | reg |= config->bpw - 1; |
469 | ||
470 | if (config->mode & SPI_CPHA) | |
3451fb15 | 471 | reg |= MX21_CSPICTRL_PHA; |
b5f3294f | 472 | if (config->mode & SPI_CPOL) |
3451fb15 | 473 | reg |= MX21_CSPICTRL_POL; |
b5f3294f | 474 | if (config->mode & SPI_CS_HIGH) |
3451fb15 | 475 | reg |= MX21_CSPICTRL_SSPOL; |
3b2aa89e | 476 | if (cs < 0) |
3451fb15 | 477 | reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; |
b5f3294f | 478 | |
6cdeb002 | 479 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
3451fb15 | 484 | static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 485 | { |
3451fb15 | 486 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
487 | } |
488 | ||
3451fb15 | 489 | static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
490 | { |
491 | writel(1, spi_imx->base + MXC_RESET); | |
492 | } | |
493 | ||
b5f3294f SH |
494 | #define MX1_INTREG_RR (1 << 3) |
495 | #define MX1_INTREG_TEEN (1 << 8) | |
496 | #define MX1_INTREG_RREN (1 << 11) | |
497 | ||
498 | #define MX1_CSPICTRL_POL (1 << 4) | |
499 | #define MX1_CSPICTRL_PHA (1 << 5) | |
500 | #define MX1_CSPICTRL_XCH (1 << 8) | |
501 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
502 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
503 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
504 | ||
f4ba6315 | 505 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
506 | { |
507 | unsigned int val = 0; | |
508 | ||
509 | if (enable & MXC_INT_TE) | |
510 | val |= MX1_INTREG_TEEN; | |
511 | if (enable & MXC_INT_RR) | |
512 | val |= MX1_INTREG_RREN; | |
513 | ||
6cdeb002 | 514 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
515 | } |
516 | ||
f4ba6315 | 517 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
518 | { |
519 | unsigned int reg; | |
520 | ||
6cdeb002 | 521 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 522 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 523 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
524 | } |
525 | ||
f4ba6315 | 526 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 527 | struct spi_imx_config *config) |
b5f3294f SH |
528 | { |
529 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
530 | ||
6cdeb002 | 531 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
532 | MX1_CSPICTRL_DR_SHIFT; |
533 | reg |= config->bpw - 1; | |
534 | ||
535 | if (config->mode & SPI_CPHA) | |
536 | reg |= MX1_CSPICTRL_PHA; | |
537 | if (config->mode & SPI_CPOL) | |
538 | reg |= MX1_CSPICTRL_POL; | |
539 | ||
6cdeb002 | 540 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
f4ba6315 | 545 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 546 | { |
6cdeb002 | 547 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
548 | } |
549 | ||
1723e66b UKK |
550 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
551 | { | |
552 | writel(1, spi_imx->base + MXC_RESET); | |
553 | } | |
554 | ||
04ee5854 SG |
555 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
556 | .intctrl = mx1_intctrl, | |
557 | .config = mx1_config, | |
558 | .trigger = mx1_trigger, | |
559 | .rx_available = mx1_rx_available, | |
560 | .reset = mx1_reset, | |
561 | .devtype = IMX1_CSPI, | |
562 | }; | |
563 | ||
564 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
565 | .intctrl = mx21_intctrl, | |
566 | .config = mx21_config, | |
567 | .trigger = mx21_trigger, | |
568 | .rx_available = mx21_rx_available, | |
569 | .reset = mx21_reset, | |
570 | .devtype = IMX21_CSPI, | |
571 | }; | |
572 | ||
573 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
574 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
575 | .intctrl = mx21_intctrl, | |
576 | .config = mx21_config, | |
577 | .trigger = mx21_trigger, | |
578 | .rx_available = mx21_rx_available, | |
579 | .reset = mx21_reset, | |
580 | .devtype = IMX27_CSPI, | |
581 | }; | |
582 | ||
583 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
584 | .intctrl = mx31_intctrl, | |
585 | .config = mx31_config, | |
586 | .trigger = mx31_trigger, | |
587 | .rx_available = mx31_rx_available, | |
588 | .reset = mx31_reset, | |
589 | .devtype = IMX31_CSPI, | |
590 | }; | |
591 | ||
592 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
593 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
594 | .intctrl = mx31_intctrl, | |
595 | .config = mx31_config, | |
596 | .trigger = mx31_trigger, | |
597 | .rx_available = mx31_rx_available, | |
598 | .reset = mx31_reset, | |
599 | .devtype = IMX35_CSPI, | |
600 | }; | |
601 | ||
602 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
603 | .intctrl = mx51_ecspi_intctrl, | |
604 | .config = mx51_ecspi_config, | |
605 | .trigger = mx51_ecspi_trigger, | |
606 | .rx_available = mx51_ecspi_rx_available, | |
607 | .reset = mx51_ecspi_reset, | |
608 | .devtype = IMX51_ECSPI, | |
609 | }; | |
610 | ||
611 | static struct platform_device_id spi_imx_devtype[] = { | |
612 | { | |
613 | .name = "imx1-cspi", | |
614 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
615 | }, { | |
616 | .name = "imx21-cspi", | |
617 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
618 | }, { | |
619 | .name = "imx27-cspi", | |
620 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
621 | }, { | |
622 | .name = "imx31-cspi", | |
623 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
624 | }, { | |
625 | .name = "imx35-cspi", | |
626 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
627 | }, { | |
628 | .name = "imx51-ecspi", | |
629 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
630 | }, { | |
631 | /* sentinel */ | |
632 | } | |
f4ba6315 UKK |
633 | }; |
634 | ||
22a85e4c SG |
635 | static const struct of_device_id spi_imx_dt_ids[] = { |
636 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
637 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
638 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
639 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
640 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
641 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
642 | { /* sentinel */ } | |
643 | }; | |
27743e0b | 644 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 645 | |
6cdeb002 | 646 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 647 | { |
6cdeb002 | 648 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
6cdeb002 | 649 | int gpio = spi_imx->chipselect[spi->chip_select]; |
e6a0a8bf UKK |
650 | int active = is_active != BITBANG_CS_INACTIVE; |
651 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 652 | |
8b17e055 | 653 | if (!gpio_is_valid(gpio)) |
b5f3294f | 654 | return; |
b5f3294f | 655 | |
e6a0a8bf | 656 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
657 | } |
658 | ||
6cdeb002 | 659 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 660 | { |
04ee5854 | 661 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
6cdeb002 | 662 | if (!spi_imx->count) |
b5f3294f | 663 | break; |
6cdeb002 UKK |
664 | spi_imx->tx(spi_imx); |
665 | spi_imx->txfifo++; | |
b5f3294f SH |
666 | } |
667 | ||
edd501bb | 668 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
669 | } |
670 | ||
6cdeb002 | 671 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 672 | { |
6cdeb002 | 673 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 674 | |
edd501bb | 675 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
6cdeb002 UKK |
676 | spi_imx->rx(spi_imx); |
677 | spi_imx->txfifo--; | |
b5f3294f SH |
678 | } |
679 | ||
6cdeb002 UKK |
680 | if (spi_imx->count) { |
681 | spi_imx_push(spi_imx); | |
b5f3294f SH |
682 | return IRQ_HANDLED; |
683 | } | |
684 | ||
6cdeb002 | 685 | if (spi_imx->txfifo) { |
b5f3294f SH |
686 | /* No data left to push, but still waiting for rx data, |
687 | * enable receive data available interrupt. | |
688 | */ | |
edd501bb | 689 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 690 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
691 | return IRQ_HANDLED; |
692 | } | |
693 | ||
edd501bb | 694 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 695 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
696 | |
697 | return IRQ_HANDLED; | |
698 | } | |
699 | ||
6cdeb002 | 700 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
701 | struct spi_transfer *t) |
702 | { | |
6cdeb002 UKK |
703 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
704 | struct spi_imx_config config; | |
b5f3294f SH |
705 | |
706 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
707 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
708 | config.mode = spi->mode; | |
3b2aa89e | 709 | config.cs = spi->chip_select; |
b5f3294f | 710 | |
462d26b5 SH |
711 | if (!config.speed_hz) |
712 | config.speed_hz = spi->max_speed_hz; | |
713 | if (!config.bpw) | |
714 | config.bpw = spi->bits_per_word; | |
462d26b5 | 715 | |
e6a0a8bf UKK |
716 | /* Initialize the functions for transfer */ |
717 | if (config.bpw <= 8) { | |
718 | spi_imx->rx = spi_imx_buf_rx_u8; | |
719 | spi_imx->tx = spi_imx_buf_tx_u8; | |
720 | } else if (config.bpw <= 16) { | |
721 | spi_imx->rx = spi_imx_buf_rx_u16; | |
722 | spi_imx->tx = spi_imx_buf_tx_u16; | |
6051426f | 723 | } else { |
e6a0a8bf UKK |
724 | spi_imx->rx = spi_imx_buf_rx_u32; |
725 | spi_imx->tx = spi_imx_buf_tx_u32; | |
24778be2 | 726 | } |
e6a0a8bf | 727 | |
edd501bb | 728 | spi_imx->devtype_data->config(spi_imx, &config); |
b5f3294f SH |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
6cdeb002 | 733 | static int spi_imx_transfer(struct spi_device *spi, |
b5f3294f SH |
734 | struct spi_transfer *transfer) |
735 | { | |
6cdeb002 | 736 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 737 | |
6cdeb002 UKK |
738 | spi_imx->tx_buf = transfer->tx_buf; |
739 | spi_imx->rx_buf = transfer->rx_buf; | |
740 | spi_imx->count = transfer->len; | |
741 | spi_imx->txfifo = 0; | |
b5f3294f | 742 | |
aa0fe826 | 743 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 744 | |
6cdeb002 | 745 | spi_imx_push(spi_imx); |
b5f3294f | 746 | |
edd501bb | 747 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 748 | |
6cdeb002 | 749 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
750 | |
751 | return transfer->len; | |
752 | } | |
753 | ||
6cdeb002 | 754 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 755 | { |
6c23e5d4 SH |
756 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
757 | int gpio = spi_imx->chipselect[spi->chip_select]; | |
758 | ||
f4d4ecfe | 759 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
760 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
761 | ||
8b17e055 | 762 | if (gpio_is_valid(gpio)) |
6c23e5d4 SH |
763 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
764 | ||
6cdeb002 | 765 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
766 | |
767 | return 0; | |
768 | } | |
769 | ||
6cdeb002 | 770 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
771 | { |
772 | } | |
773 | ||
9e556dcc HS |
774 | static int |
775 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) | |
776 | { | |
777 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
778 | int ret; | |
779 | ||
780 | ret = clk_enable(spi_imx->clk_per); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | ret = clk_enable(spi_imx->clk_ipg); | |
785 | if (ret) { | |
786 | clk_disable(spi_imx->clk_per); | |
787 | return ret; | |
788 | } | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static int | |
794 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) | |
795 | { | |
796 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
797 | ||
798 | clk_disable(spi_imx->clk_ipg); | |
799 | clk_disable(spi_imx->clk_per); | |
800 | return 0; | |
801 | } | |
802 | ||
fd4a319b | 803 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 804 | { |
22a85e4c SG |
805 | struct device_node *np = pdev->dev.of_node; |
806 | const struct of_device_id *of_id = | |
807 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
808 | struct spi_imx_master *mxc_platform_info = | |
809 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 810 | struct spi_master *master; |
6cdeb002 | 811 | struct spi_imx_data *spi_imx; |
b5f3294f | 812 | struct resource *res; |
c2387cb9 | 813 | int i, ret, num_cs; |
b5f3294f | 814 | |
22a85e4c | 815 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
816 | dev_err(&pdev->dev, "can't get the platform data\n"); |
817 | return -EINVAL; | |
818 | } | |
819 | ||
22a85e4c | 820 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); |
39ec0d38 LW |
821 | if (ret < 0) { |
822 | if (mxc_platform_info) | |
823 | num_cs = mxc_platform_info->num_chipselect; | |
824 | else | |
825 | return ret; | |
826 | } | |
22a85e4c | 827 | |
c2387cb9 SG |
828 | master = spi_alloc_master(&pdev->dev, |
829 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); | |
b5f3294f SH |
830 | if (!master) |
831 | return -ENOMEM; | |
832 | ||
833 | platform_set_drvdata(pdev, master); | |
834 | ||
24778be2 | 835 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
b5f3294f | 836 | master->bus_num = pdev->id; |
c2387cb9 | 837 | master->num_chipselect = num_cs; |
b5f3294f | 838 | |
6cdeb002 | 839 | spi_imx = spi_master_get_devdata(master); |
94c69f76 | 840 | spi_imx->bitbang.master = master; |
b5f3294f SH |
841 | |
842 | for (i = 0; i < master->num_chipselect; i++) { | |
22a85e4c | 843 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
8b17e055 | 844 | if (!gpio_is_valid(cs_gpio) && mxc_platform_info) |
22a85e4c | 845 | cs_gpio = mxc_platform_info->chipselect[i]; |
4cc122ac FE |
846 | |
847 | spi_imx->chipselect[i] = cs_gpio; | |
8b17e055 | 848 | if (!gpio_is_valid(cs_gpio)) |
b5f3294f | 849 | continue; |
4cc122ac | 850 | |
130b82c0 FE |
851 | ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], |
852 | DRIVER_NAME); | |
b5f3294f | 853 | if (ret) { |
bbd050af | 854 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
130b82c0 | 855 | goto out_master_put; |
b5f3294f | 856 | } |
b5f3294f SH |
857 | } |
858 | ||
6cdeb002 UKK |
859 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
860 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
861 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
862 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
863 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
9e556dcc HS |
864 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
865 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | |
3910f2cf | 866 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
b5f3294f | 867 | |
6cdeb002 | 868 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 869 | |
22a85e4c | 870 | spi_imx->devtype_data = of_id ? of_id->data : |
04ee5854 | 871 | (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; |
f4ba6315 | 872 | |
b5f3294f | 873 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
130b82c0 FE |
874 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
875 | if (IS_ERR(spi_imx->base)) { | |
876 | ret = PTR_ERR(spi_imx->base); | |
877 | goto out_master_put; | |
b5f3294f SH |
878 | } |
879 | ||
6cdeb002 | 880 | spi_imx->irq = platform_get_irq(pdev, 0); |
73575938 | 881 | if (spi_imx->irq < 0) { |
82106e0e | 882 | ret = spi_imx->irq; |
130b82c0 | 883 | goto out_master_put; |
b5f3294f SH |
884 | } |
885 | ||
130b82c0 | 886 | ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0, |
8fc39b51 | 887 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 888 | if (ret) { |
6cdeb002 | 889 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
130b82c0 | 890 | goto out_master_put; |
b5f3294f SH |
891 | } |
892 | ||
aa29d840 SH |
893 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
894 | if (IS_ERR(spi_imx->clk_ipg)) { | |
895 | ret = PTR_ERR(spi_imx->clk_ipg); | |
130b82c0 | 896 | goto out_master_put; |
b5f3294f SH |
897 | } |
898 | ||
aa29d840 SH |
899 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
900 | if (IS_ERR(spi_imx->clk_per)) { | |
901 | ret = PTR_ERR(spi_imx->clk_per); | |
130b82c0 | 902 | goto out_master_put; |
aa29d840 SH |
903 | } |
904 | ||
83174626 FE |
905 | ret = clk_prepare_enable(spi_imx->clk_per); |
906 | if (ret) | |
907 | goto out_master_put; | |
908 | ||
909 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
910 | if (ret) | |
911 | goto out_put_per; | |
aa29d840 SH |
912 | |
913 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
b5f3294f | 914 | |
edd501bb | 915 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 916 | |
edd501bb | 917 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 918 | |
22a85e4c | 919 | master->dev.of_node = pdev->dev.of_node; |
6cdeb002 | 920 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
921 | if (ret) { |
922 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
923 | goto out_clk_put; | |
924 | } | |
925 | ||
926 | dev_info(&pdev->dev, "probed\n"); | |
927 | ||
9e556dcc HS |
928 | clk_disable(spi_imx->clk_ipg); |
929 | clk_disable(spi_imx->clk_per); | |
b5f3294f SH |
930 | return ret; |
931 | ||
932 | out_clk_put: | |
aa29d840 | 933 | clk_disable_unprepare(spi_imx->clk_ipg); |
83174626 FE |
934 | out_put_per: |
935 | clk_disable_unprepare(spi_imx->clk_per); | |
130b82c0 | 936 | out_master_put: |
b5f3294f | 937 | spi_master_put(master); |
130b82c0 | 938 | |
b5f3294f SH |
939 | return ret; |
940 | } | |
941 | ||
fd4a319b | 942 | static int spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
943 | { |
944 | struct spi_master *master = platform_get_drvdata(pdev); | |
6cdeb002 | 945 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f | 946 | |
6cdeb002 | 947 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 948 | |
6cdeb002 | 949 | writel(0, spi_imx->base + MXC_CSPICTRL); |
fd40dccb PDM |
950 | clk_unprepare(spi_imx->clk_ipg); |
951 | clk_unprepare(spi_imx->clk_per); | |
b5f3294f SH |
952 | spi_master_put(master); |
953 | ||
b5f3294f SH |
954 | return 0; |
955 | } | |
956 | ||
6cdeb002 | 957 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
958 | .driver = { |
959 | .name = DRIVER_NAME, | |
960 | .owner = THIS_MODULE, | |
22a85e4c | 961 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 962 | }, |
f4ba6315 | 963 | .id_table = spi_imx_devtype, |
6cdeb002 | 964 | .probe = spi_imx_probe, |
fd4a319b | 965 | .remove = spi_imx_remove, |
b5f3294f | 966 | }; |
940ab889 | 967 | module_platform_driver(spi_imx_driver); |
b5f3294f SH |
968 | |
969 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
970 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
971 | MODULE_LICENSE("GPL"); | |
3133fba3 | 972 | MODULE_ALIAS("platform:" DRIVER_NAME); |