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spi: spi-imx: Do not store the irq number in the private structure
[deliverable/linux.git] / drivers / spi / spi-imx.c
CommitLineData
b5f3294f
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
f62caccd
RG		 24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
b5f3294f
SH		 26#include <linux/err.h>
27#include <linux/gpio.h>
b5f3294f
SH		 28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
5a0e3ad6 34#include <linux/slab.h>
b5f3294f
SH		 35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
22a85e4c
SG		 38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
b5f3294f 41
f62caccd 42#include <linux/platform_data/dma-imx.h>
82906b13 43#include <linux/platform_data/spi-imx.h>
b5f3294f
SH		 44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
f62caccd
RG		 57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
6cdeb002 60struct spi_imx_config {
b5f3294f
SH		 61 unsigned int speed_hz;
62 unsigned int bpw;
63 unsigned int mode;
3b2aa89e 64 u8 cs;
b5f3294f
SH		 65};
66
f4ba6315 67enum spi_imx_devtype {
04ee5854
SG		 68 IMX1_CSPI,
69 IMX21_CSPI,
70 IMX27_CSPI,
71 IMX31_CSPI,
72 IMX35_CSPI, /* CSPI on all i.mx except above */
73 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
f4ba6315
UKK		 74};
75
76struct spi_imx_data;
77
78struct spi_imx_devtype_data {
79 void (*intctrl)(struct spi_imx_data *, int);
80 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
81 void (*trigger)(struct spi_imx_data *);
82 int (*rx_available)(struct spi_imx_data *);
1723e66b 83 void (*reset)(struct spi_imx_data *);
04ee5854 84 enum spi_imx_devtype devtype;
f4ba6315
UKK		 85};
86
6cdeb002 87struct spi_imx_data {
b5f3294f
SH		 88 struct spi_bitbang bitbang;
89
90 struct completion xfer_done;
cc4d22ae 91 void __iomem *base;
aa29d840
SH		 92 struct clk *clk_per;
93 struct clk *clk_ipg;
b5f3294f 94 unsigned long spi_clk;
b5f3294f
SH		 95
96 unsigned int count;
6cdeb002
UKK		 97 void (*tx)(struct spi_imx_data *);
98 void (*rx)(struct spi_imx_data *);
b5f3294f
SH		 99 void *rx_buf;
100 const void *tx_buf;
101 unsigned int txfifo; /* number of words pushed in tx FIFO */
102
f62caccd
RG		 103 /* DMA */
104 unsigned int dma_is_inited;
105 unsigned int dma_finished;
106 bool usedma;
107 u32 rx_wml;
108 u32 tx_wml;
109 u32 rxt_wml;
110 struct completion dma_rx_completion;
111 struct completion dma_tx_completion;
112
80023cb3 113 const struct spi_imx_devtype_data *devtype_data;
c2387cb9 114 int chipselect[0];
b5f3294f
SH		 115};
116
04ee5854
SG		 117static inline int is_imx27_cspi(struct spi_imx_data *d)
118{
119 return d->devtype_data->devtype == IMX27_CSPI;
120}
121
122static inline int is_imx35_cspi(struct spi_imx_data *d)
123{
124 return d->devtype_data->devtype == IMX35_CSPI;
125}
126
127static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
128{
129 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
130}
131
b5f3294f 132#define MXC_SPI_BUF_RX(type) \
6cdeb002 133static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
b5f3294f 134{ \
6cdeb002 135 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
b5f3294f 136 \
6cdeb002
UKK		 137 if (spi_imx->rx_buf) { \
138 *(type *)spi_imx->rx_buf = val; \
139 spi_imx->rx_buf += sizeof(type); \
b5f3294f
SH		 140 } \
141}
142
143#define MXC_SPI_BUF_TX(type) \
6cdeb002 144static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
b5f3294f
SH		 145{ \
146 type val = 0; \
147 \
6cdeb002
UKK		 148 if (spi_imx->tx_buf) { \
149 val = *(type *)spi_imx->tx_buf; \
150 spi_imx->tx_buf += sizeof(type); \
b5f3294f
SH		 151 } \
152 \
6cdeb002 153 spi_imx->count -= sizeof(type); \
b5f3294f 154 \
6cdeb002 155 writel(val, spi_imx->base + MXC_CSPITXDATA); \
b5f3294f
SH		 156}
157
158MXC_SPI_BUF_RX(u8)
159MXC_SPI_BUF_TX(u8)
160MXC_SPI_BUF_RX(u16)
161MXC_SPI_BUF_TX(u16)
162MXC_SPI_BUF_RX(u32)
163MXC_SPI_BUF_TX(u32)
164
165/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
166 * (which is currently not the case in this driver)
167 */
168static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
169 256, 384, 512, 768, 1024};
170
171/* MX21, MX27 */
6cdeb002 172static unsigned int spi_imx_clkdiv_1(unsigned int fin,
04ee5854 173 unsigned int fspi, unsigned int max)
b5f3294f 174{
04ee5854 175 int i;
b5f3294f
SH		 176
177 for (i = 2; i < max; i++)
178 if (fspi * mxc_clkdivs[i] >= fin)
179 return i;
180
181 return max;
182}
183
0b599603 184/* MX1, MX31, MX35, MX51 CSPI */
6cdeb002 185static unsigned int spi_imx_clkdiv_2(unsigned int fin,
b5f3294f
SH		 186 unsigned int fspi)
187{
188 int i, div = 4;
189
190 for (i = 0; i < 7; i++) {
191 if (fspi * div >= fin)
192 return i;
193 div <<= 1;
194 }
195
196 return 7;
197}
198
f62caccd
RG		 199static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
200 struct spi_transfer *transfer)
201{
202 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
203
204 if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml)
205 && (transfer->len > spi_imx->tx_wml))
206 return true;
207 return false;
208}
209
66de757c
SG		 210#define MX51_ECSPI_CTRL 0x08
211#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
212#define MX51_ECSPI_CTRL_XCH (1 << 2)
f62caccd 213#define MX51_ECSPI_CTRL_SMC (1 << 3)
66de757c
SG		 214#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
215#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
216#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
217#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
218#define MX51_ECSPI_CTRL_BL_OFFSET 20
219
220#define MX51_ECSPI_CONFIG 0x0c
221#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
222#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
223#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
224#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
c09b890b 225#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
66de757c
SG		 226
227#define MX51_ECSPI_INT 0x10
228#define MX51_ECSPI_INT_TEEN (1 << 0)
229#define MX51_ECSPI_INT_RREN (1 << 3)
230
f62caccd
RG		 231#define MX51_ECSPI_DMA 0x14
232#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
233#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
234#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
235#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
236#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
237#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
238
239#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
240#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
241#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
242
66de757c
SG		 243#define MX51_ECSPI_STAT 0x18
244#define MX51_ECSPI_STAT_RR (1 << 3)
0b599603
UKK		 245
246/* MX51 eCSPI */
6fd8b850
MV		 247static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
248 unsigned int *fres)
0b599603
UKK		 249{
250 /*
251 * there are two 4-bit dividers, the pre-divider divides by
252 * $pre, the post-divider by 2^$post
253 */
254 unsigned int pre, post;
255
256 if (unlikely(fspi > fin))
257 return 0;
258
259 post = fls(fin) - fls(fspi);
260 if (fin > fspi << post)
261 post++;
262
263 /* now we have: (fin <= fspi << post) with post being minimal */
264
265 post = max(4U, post) - 4;
266 if (unlikely(post > 0xf)) {
267 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
268 __func__, fspi, fin);
269 return 0xff;
270 }
271
272 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
273
274 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
275 __func__, fin, fspi, post, pre);
6fd8b850
MV		 276
277 /* Resulting frequency for the SCLK line. */
278 *fres = (fin / (pre + 1)) >> post;
279
66de757c
SG		 280 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
281 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
0b599603
UKK		 282}
283
66de757c 284static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
0b599603
UKK		 285{
286 unsigned val = 0;
287
288 if (enable & MXC_INT_TE)
66de757c 289 val |= MX51_ECSPI_INT_TEEN;
0b599603
UKK		 290
291 if (enable & MXC_INT_RR)
66de757c 292 val |= MX51_ECSPI_INT_RREN;
0b599603 293
66de757c 294 writel(val, spi_imx->base + MX51_ECSPI_INT);
0b599603
UKK		 295}
296
66de757c 297static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
0b599603 298{
f62caccd
RG		 299 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
300
301 if (!spi_imx->usedma)
302 reg |= MX51_ECSPI_CTRL_XCH;
303 else if (!spi_imx->dma_finished)
304 reg |= MX51_ECSPI_CTRL_SMC;
305 else
306 reg &= ~MX51_ECSPI_CTRL_SMC;
66de757c 307 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
0b599603
UKK		 308}
309
66de757c 310static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
0b599603
UKK		 311 struct spi_imx_config *config)
312{
f62caccd
RG		 313 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
314 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
6fd8b850 315 u32 clk = config->speed_hz, delay;
0b599603 316
f020c39e
SH		 317 /*
318 * The hardware seems to have a race condition when changing modes. The
319 * current assumption is that the selection of the channel arrives
320 * earlier in the hardware than the mode bits when they are written at
321 * the same time.
322 * So set master mode for all channels as we do not support slave mode.
323 */
66de757c 324 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
0b599603
UKK		 325
326 /* set clock speed */
6fd8b850 327 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
0b599603
UKK		 328
329 /* set chip select to use */
66de757c 330 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
0b599603 331
66de757c 332 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
0b599603 333
66de757c 334 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
0b599603
UKK		 335
336 if (config->mode & SPI_CPHA)
66de757c 337 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
0b599603 338
c09b890b 339 if (config->mode & SPI_CPOL) {
66de757c 340 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
c09b890b
KW		 341 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
342 }
0b599603 343 if (config->mode & SPI_CS_HIGH)
66de757c 344 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
0b599603 345
66de757c
SG		 346 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
347 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
0b599603 348
6fd8b850
MV		 349 /*
350 * Wait until the changes in the configuration register CONFIGREG
351 * propagate into the hardware. It takes exactly one tick of the
352 * SCLK clock, but we will wait two SCLK clock just to be sure. The
353 * effect of the delay it takes for the hardware to apply changes
354 * is noticable if the SCLK clock run very slow. In such a case, if
355 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
356 * be asserted before the SCLK polarity changes, which would disrupt
357 * the SPI communication as the device on the other end would consider
358 * the change of SCLK polarity as a clock tick already.
359 */
360 delay = (2 * 1000000) / clk;
361 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
362 udelay(delay);
363 else /* SCLK is _very_ slow */
364 usleep_range(delay, delay + 10);
365
f62caccd
RG		 366 /*
367 * Configure the DMA register: setup the watermark
368 * and enable DMA request.
369 */
370 if (spi_imx->dma_is_inited) {
371 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
372
373 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
374 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
375 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
376 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
377 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
378 rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
379 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
380 & ~MX51_ECSPI_DMA_RX_WML_MASK
381 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
382 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
383 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
384 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
385 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
386
387 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
388 }
389
0b599603
UKK		 390 return 0;
391}
392
66de757c 393static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
0b599603 394{
66de757c 395 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
0b599603
UKK		 396}
397
66de757c 398static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
0b599603
UKK		 399{
400 /* drain receive buffer */
66de757c 401 while (mx51_ecspi_rx_available(spi_imx))
0b599603
UKK		 402 readl(spi_imx->base + MXC_CSPIRXDATA);
403}
404
b5f3294f
SH		 405#define MX31_INTREG_TEEN (1 << 0)
406#define MX31_INTREG_RREN (1 << 3)
407
408#define MX31_CSPICTRL_ENABLE (1 << 0)
409#define MX31_CSPICTRL_MASTER (1 << 1)
410#define MX31_CSPICTRL_XCH (1 << 2)
411#define MX31_CSPICTRL_POL (1 << 4)
412#define MX31_CSPICTRL_PHA (1 << 5)
413#define MX31_CSPICTRL_SSCTL (1 << 6)
414#define MX31_CSPICTRL_SSPOL (1 << 7)
415#define MX31_CSPICTRL_BC_SHIFT 8
416#define MX35_CSPICTRL_BL_SHIFT 20
417#define MX31_CSPICTRL_CS_SHIFT 24
418#define MX35_CSPICTRL_CS_SHIFT 12
419#define MX31_CSPICTRL_DR_SHIFT 16
420
421#define MX31_CSPISTATUS 0x14
422#define MX31_STATUS_RR (1 << 3)
423
424/* These functions also work for the i.MX35, but be aware that
425 * the i.MX35 has a slightly different register layout for bits
426 * we do not use here.
427 */
f4ba6315 428static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 429{
430 unsigned int val = 0;
431
432 if (enable & MXC_INT_TE)
433 val |= MX31_INTREG_TEEN;
434 if (enable & MXC_INT_RR)
435 val |= MX31_INTREG_RREN;
436
6cdeb002 437 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 438}
439
f4ba6315 440static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 441{
442 unsigned int reg;
443
6cdeb002 444 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 445 reg |= MX31_CSPICTRL_XCH;
6cdeb002 446 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 447}
448
2a64a90a 449static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
1723e66b
UKK		 450 struct spi_imx_config *config)
451{
452 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
3b2aa89e 453 int cs = spi_imx->chipselect[config->cs];
1723e66b
UKK		 454
455 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
456 MX31_CSPICTRL_DR_SHIFT;
457
04ee5854 458 if (is_imx35_cspi(spi_imx)) {
2a64a90a
SG		 459 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
460 reg |= MX31_CSPICTRL_SSCTL;
461 } else {
462 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
463 }
1723e66b
UKK		 464
465 if (config->mode & SPI_CPHA)
466 reg |= MX31_CSPICTRL_PHA;
467 if (config->mode & SPI_CPOL)
468 reg |= MX31_CSPICTRL_POL;
469 if (config->mode & SPI_CS_HIGH)
470 reg |= MX31_CSPICTRL_SSPOL;
3b2aa89e 471 if (cs < 0)
2a64a90a 472 reg |= (cs + 32) <<
04ee5854
SG		 473 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
474 MX31_CSPICTRL_CS_SHIFT);
1723e66b
UKK		 475
476 writel(reg, spi_imx->base + MXC_CSPICTRL);
477
478 return 0;
479}
480
f4ba6315 481static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 482{
6cdeb002 483 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
b5f3294f
SH		 484}
485
2a64a90a 486static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 487{
488 /* drain receive buffer */
2a64a90a 489 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
1723e66b
UKK		 490 readl(spi_imx->base + MXC_CSPIRXDATA);
491}
492
3451fb15
SG		 493#define MX21_INTREG_RR (1 << 4)
494#define MX21_INTREG_TEEN (1 << 9)
495#define MX21_INTREG_RREN (1 << 13)
496
497#define MX21_CSPICTRL_POL (1 << 5)
498#define MX21_CSPICTRL_PHA (1 << 6)
499#define MX21_CSPICTRL_SSPOL (1 << 8)
500#define MX21_CSPICTRL_XCH (1 << 9)
501#define MX21_CSPICTRL_ENABLE (1 << 10)
502#define MX21_CSPICTRL_MASTER (1 << 11)
503#define MX21_CSPICTRL_DR_SHIFT 14
504#define MX21_CSPICTRL_CS_SHIFT 19
505
506static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 507{
508 unsigned int val = 0;
509
510 if (enable & MXC_INT_TE)
3451fb15 511 val |= MX21_INTREG_TEEN;
b5f3294f 512 if (enable & MXC_INT_RR)
3451fb15 513 val |= MX21_INTREG_RREN;
b5f3294f 514
6cdeb002 515 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 516}
517
3451fb15 518static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 519{
520 unsigned int reg;
521
6cdeb002 522 reg = readl(spi_imx->base + MXC_CSPICTRL);
3451fb15 523 reg |= MX21_CSPICTRL_XCH;
6cdeb002 524 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 525}
526
3451fb15 527static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
6cdeb002 528 struct spi_imx_config *config)
b5f3294f 529{
3451fb15 530 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
3b2aa89e 531 int cs = spi_imx->chipselect[config->cs];
04ee5854 532 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
b5f3294f 533
04ee5854 534 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
3451fb15 535 MX21_CSPICTRL_DR_SHIFT;
b5f3294f
SH		 536 reg |= config->bpw - 1;
537
538 if (config->mode & SPI_CPHA)
3451fb15 539 reg |= MX21_CSPICTRL_PHA;
b5f3294f 540 if (config->mode & SPI_CPOL)
3451fb15 541 reg |= MX21_CSPICTRL_POL;
b5f3294f 542 if (config->mode & SPI_CS_HIGH)
3451fb15 543 reg |= MX21_CSPICTRL_SSPOL;
3b2aa89e 544 if (cs < 0)
3451fb15 545 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
b5f3294f 546
6cdeb002 547 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 548
549 return 0;
550}
551
3451fb15 552static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 553{
3451fb15 554 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
b5f3294f
SH		 555}
556
3451fb15 557static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 558{
559 writel(1, spi_imx->base + MXC_RESET);
560}
561
b5f3294f
SH		 562#define MX1_INTREG_RR (1 << 3)
563#define MX1_INTREG_TEEN (1 << 8)
564#define MX1_INTREG_RREN (1 << 11)
565
566#define MX1_CSPICTRL_POL (1 << 4)
567#define MX1_CSPICTRL_PHA (1 << 5)
568#define MX1_CSPICTRL_XCH (1 << 8)
569#define MX1_CSPICTRL_ENABLE (1 << 9)
570#define MX1_CSPICTRL_MASTER (1 << 10)
571#define MX1_CSPICTRL_DR_SHIFT 13
572
f4ba6315 573static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 574{
575 unsigned int val = 0;
576
577 if (enable & MXC_INT_TE)
578 val |= MX1_INTREG_TEEN;
579 if (enable & MXC_INT_RR)
580 val |= MX1_INTREG_RREN;
581
6cdeb002 582 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 583}
584
f4ba6315 585static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 586{
587 unsigned int reg;
588
6cdeb002 589 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 590 reg |= MX1_CSPICTRL_XCH;
6cdeb002 591 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 592}
593
f4ba6315 594static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
6cdeb002 595 struct spi_imx_config *config)
b5f3294f
SH		 596{
597 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
598
6cdeb002 599 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 600 MX1_CSPICTRL_DR_SHIFT;
601 reg |= config->bpw - 1;
602
603 if (config->mode & SPI_CPHA)
604 reg |= MX1_CSPICTRL_PHA;
605 if (config->mode & SPI_CPOL)
606 reg |= MX1_CSPICTRL_POL;
607
6cdeb002 608 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 609
610 return 0;
611}
612
f4ba6315 613static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 614{
6cdeb002 615 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
b5f3294f
SH		 616}
617
1723e66b
UKK		 618static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
619{
620 writel(1, spi_imx->base + MXC_RESET);
621}
622
04ee5854
SG		 623static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
624 .intctrl = mx1_intctrl,
625 .config = mx1_config,
626 .trigger = mx1_trigger,
627 .rx_available = mx1_rx_available,
628 .reset = mx1_reset,
629 .devtype = IMX1_CSPI,
630};
631
632static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
633 .intctrl = mx21_intctrl,
634 .config = mx21_config,
635 .trigger = mx21_trigger,
636 .rx_available = mx21_rx_available,
637 .reset = mx21_reset,
638 .devtype = IMX21_CSPI,
639};
640
641static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
642 /* i.mx27 cspi shares the functions with i.mx21 one */
643 .intctrl = mx21_intctrl,
644 .config = mx21_config,
645 .trigger = mx21_trigger,
646 .rx_available = mx21_rx_available,
647 .reset = mx21_reset,
648 .devtype = IMX27_CSPI,
649};
650
651static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
652 .intctrl = mx31_intctrl,
653 .config = mx31_config,
654 .trigger = mx31_trigger,
655 .rx_available = mx31_rx_available,
656 .reset = mx31_reset,
657 .devtype = IMX31_CSPI,
658};
659
660static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
661 /* i.mx35 and later cspi shares the functions with i.mx31 one */
662 .intctrl = mx31_intctrl,
663 .config = mx31_config,
664 .trigger = mx31_trigger,
665 .rx_available = mx31_rx_available,
666 .reset = mx31_reset,
667 .devtype = IMX35_CSPI,
668};
669
670static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
671 .intctrl = mx51_ecspi_intctrl,
672 .config = mx51_ecspi_config,
673 .trigger = mx51_ecspi_trigger,
674 .rx_available = mx51_ecspi_rx_available,
675 .reset = mx51_ecspi_reset,
676 .devtype = IMX51_ECSPI,
677};
678
679static struct platform_device_id spi_imx_devtype[] = {
680 {
681 .name = "imx1-cspi",
682 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
683 }, {
684 .name = "imx21-cspi",
685 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
686 }, {
687 .name = "imx27-cspi",
688 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
689 }, {
690 .name = "imx31-cspi",
691 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
692 }, {
693 .name = "imx35-cspi",
694 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
695 }, {
696 .name = "imx51-ecspi",
697 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
698 }, {
699 /* sentinel */
700 }
f4ba6315
UKK		 701};
702
22a85e4c
SG		 703static const struct of_device_id spi_imx_dt_ids[] = {
704 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
705 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
706 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
707 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
708 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
709 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
710 { /* sentinel */ }
711};
27743e0b 712MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
22a85e4c 713
6cdeb002 714static void spi_imx_chipselect(struct spi_device *spi, int is_active)
b5f3294f 715{
6cdeb002 716 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
6cdeb002 717 int gpio = spi_imx->chipselect[spi->chip_select];
e6a0a8bf
UKK		 718 int active = is_active != BITBANG_CS_INACTIVE;
719 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
b5f3294f 720
8b17e055 721 if (!gpio_is_valid(gpio))
b5f3294f 722 return;
b5f3294f 723
e6a0a8bf 724 gpio_set_value(gpio, dev_is_lowactive ^ active);
b5f3294f
SH		 725}
726
6cdeb002 727static void spi_imx_push(struct spi_imx_data *spi_imx)
b5f3294f 728{
04ee5854 729 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
6cdeb002 730 if (!spi_imx->count)
b5f3294f 731 break;
6cdeb002
UKK		 732 spi_imx->tx(spi_imx);
733 spi_imx->txfifo++;
b5f3294f
SH		 734 }
735
edd501bb 736 spi_imx->devtype_data->trigger(spi_imx);
b5f3294f
SH		 737}
738
6cdeb002 739static irqreturn_t spi_imx_isr(int irq, void *dev_id)
b5f3294f 740{
6cdeb002 741 struct spi_imx_data *spi_imx = dev_id;
b5f3294f 742
edd501bb 743 while (spi_imx->devtype_data->rx_available(spi_imx)) {
6cdeb002
UKK		 744 spi_imx->rx(spi_imx);
745 spi_imx->txfifo--;
b5f3294f
SH		 746 }
747
6cdeb002
UKK		 748 if (spi_imx->count) {
749 spi_imx_push(spi_imx);
b5f3294f
SH		 750 return IRQ_HANDLED;
751 }
752
6cdeb002 753 if (spi_imx->txfifo) {
b5f3294f
SH		 754 /* No data left to push, but still waiting for rx data,
755 * enable receive data available interrupt.
756 */
edd501bb 757 spi_imx->devtype_data->intctrl(
f4ba6315 758 spi_imx, MXC_INT_RR);
b5f3294f
SH		 759 return IRQ_HANDLED;
760 }
761
edd501bb 762 spi_imx->devtype_data->intctrl(spi_imx, 0);
6cdeb002 763 complete(&spi_imx->xfer_done);
b5f3294f
SH		 764
765 return IRQ_HANDLED;
766}
767
6cdeb002 768static int spi_imx_setupxfer(struct spi_device *spi,
b5f3294f
SH		 769 struct spi_transfer *t)
770{
6cdeb002
UKK		 771 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
772 struct spi_imx_config config;
b5f3294f
SH		 773
774 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
775 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
776 config.mode = spi->mode;
3b2aa89e 777 config.cs = spi->chip_select;
b5f3294f 778
462d26b5
SH		 779 if (!config.speed_hz)
780 config.speed_hz = spi->max_speed_hz;
781 if (!config.bpw)
782 config.bpw = spi->bits_per_word;
462d26b5 783
e6a0a8bf
UKK		 784 /* Initialize the functions for transfer */
785 if (config.bpw <= 8) {
786 spi_imx->rx = spi_imx_buf_rx_u8;
787 spi_imx->tx = spi_imx_buf_tx_u8;
788 } else if (config.bpw <= 16) {
789 spi_imx->rx = spi_imx_buf_rx_u16;
790 spi_imx->tx = spi_imx_buf_tx_u16;
6051426f 791 } else {
e6a0a8bf
UKK		 792 spi_imx->rx = spi_imx_buf_rx_u32;
793 spi_imx->tx = spi_imx_buf_tx_u32;
24778be2 794 }
e6a0a8bf 795
edd501bb 796 spi_imx->devtype_data->config(spi_imx, &config);
b5f3294f
SH		 797
798 return 0;
799}
800
f62caccd
RG		 801static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
802{
803 struct spi_master *master = spi_imx->bitbang.master;
804
805 if (master->dma_rx) {
806 dma_release_channel(master->dma_rx);
807 master->dma_rx = NULL;
808 }
809
810 if (master->dma_tx) {
811 dma_release_channel(master->dma_tx);
812 master->dma_tx = NULL;
813 }
814
815 spi_imx->dma_is_inited = 0;
816}
817
818static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
819 struct spi_master *master,
820 const struct resource *res)
821{
822 struct dma_slave_config slave_config = {};
823 int ret;
824
825 /* Prepare for TX DMA: */
826 master->dma_tx = dma_request_slave_channel(dev, "tx");
827 if (!master->dma_tx) {
828 dev_err(dev, "cannot get the TX DMA channel!\n");
829 ret = -EINVAL;
830 goto err;
831 }
832
833 slave_config.direction = DMA_MEM_TO_DEV;
834 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
835 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
836 slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
837 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
838 if (ret) {
839 dev_err(dev, "error in TX dma configuration.\n");
840 goto err;
841 }
842
843 /* Prepare for RX : */
844 master->dma_rx = dma_request_slave_channel(dev, "rx");
845 if (!master->dma_rx) {
846 dev_dbg(dev, "cannot get the DMA channel.\n");
847 ret = -EINVAL;
848 goto err;
849 }
850
851 slave_config.direction = DMA_DEV_TO_MEM;
852 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
853 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
854 slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
855 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
856 if (ret) {
857 dev_err(dev, "error in RX dma configuration.\n");
858 goto err;
859 }
860
861 init_completion(&spi_imx->dma_rx_completion);
862 init_completion(&spi_imx->dma_tx_completion);
863 master->can_dma = spi_imx_can_dma;
864 master->max_dma_len = MAX_SDMA_BD_BYTES;
865 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
866 SPI_MASTER_MUST_TX;
867 spi_imx->dma_is_inited = 1;
868
869 return 0;
870err:
871 spi_imx_sdma_exit(spi_imx);
872 return ret;
873}
874
875static void spi_imx_dma_rx_callback(void *cookie)
876{
877 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
878
879 complete(&spi_imx->dma_rx_completion);
880}
881
882static void spi_imx_dma_tx_callback(void *cookie)
883{
884 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
885
886 complete(&spi_imx->dma_tx_completion);
887}
888
889static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
890 struct spi_transfer *transfer)
891{
892 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
893 int ret;
894 u32 dma;
895 int left;
896 struct spi_master *master = spi_imx->bitbang.master;
897 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
898
899 if (tx) {
900 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
901 tx->sgl, tx->nents, DMA_TO_DEVICE,
902 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
903 if (!desc_tx)
904 goto no_dma;
905
906 desc_tx->callback = spi_imx_dma_tx_callback;
907 desc_tx->callback_param = (void *)spi_imx;
908 dmaengine_submit(desc_tx);
909 }
910
911 if (rx) {
912 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
913 rx->sgl, rx->nents, DMA_FROM_DEVICE,
914 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
915 if (!desc_rx)
916 goto no_dma;
917
918 desc_rx->callback = spi_imx_dma_rx_callback;
919 desc_rx->callback_param = (void *)spi_imx;
920 dmaengine_submit(desc_rx);
921 }
922
923 reinit_completion(&spi_imx->dma_rx_completion);
924 reinit_completion(&spi_imx->dma_tx_completion);
925
926 /* Trigger the cspi module. */
927 spi_imx->dma_finished = 0;
928
929 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
930 dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
931 /* Change RX_DMA_LENGTH trigger dma fetch tail data */
932 left = transfer->len % spi_imx->rxt_wml;
933 if (left)
934 writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
935 spi_imx->base + MX51_ECSPI_DMA);
936 spi_imx->devtype_data->trigger(spi_imx);
937
938 dma_async_issue_pending(master->dma_tx);
939 dma_async_issue_pending(master->dma_rx);
940 /* Wait SDMA to finish the data transfer.*/
941 ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
942 IMX_DMA_TIMEOUT);
943 if (!ret) {
944 pr_warn("%s %s: I/O Error in DMA TX\n",
945 dev_driver_string(&master->dev),
946 dev_name(&master->dev));
947 dmaengine_terminate_all(master->dma_tx);
948 } else {
949 ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
950 IMX_DMA_TIMEOUT);
951 if (!ret) {
952 pr_warn("%s %s: I/O Error in DMA RX\n",
953 dev_driver_string(&master->dev),
954 dev_name(&master->dev));
955 spi_imx->devtype_data->reset(spi_imx);
956 dmaengine_terminate_all(master->dma_rx);
957 }
958 writel(dma |
959 spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
960 spi_imx->base + MX51_ECSPI_DMA);
961 }
962
963 spi_imx->dma_finished = 1;
964 spi_imx->devtype_data->trigger(spi_imx);
965
966 if (!ret)
967 ret = -ETIMEDOUT;
968 else if (ret > 0)
969 ret = transfer->len;
970
971 return ret;
972
973no_dma:
974 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
975 dev_driver_string(&master->dev),
976 dev_name(&master->dev));
977 return -EAGAIN;
978}
979
980static int spi_imx_pio_transfer(struct spi_device *spi,
b5f3294f
SH		 981 struct spi_transfer *transfer)
982{
6cdeb002 983 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
b5f3294f 984
6cdeb002
UKK		 985 spi_imx->tx_buf = transfer->tx_buf;
986 spi_imx->rx_buf = transfer->rx_buf;
987 spi_imx->count = transfer->len;
988 spi_imx->txfifo = 0;
b5f3294f 989
aa0fe826 990 reinit_completion(&spi_imx->xfer_done);
b5f3294f 991
6cdeb002 992 spi_imx_push(spi_imx);
b5f3294f 993
edd501bb 994 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
b5f3294f 995
6cdeb002 996 wait_for_completion(&spi_imx->xfer_done);
b5f3294f
SH		 997
998 return transfer->len;
999}
1000
f62caccd
RG		 1001static int spi_imx_transfer(struct spi_device *spi,
1002 struct spi_transfer *transfer)
1003{
1004 int ret;
1005 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1006
1007 if (spi_imx->bitbang.master->can_dma &&
1008 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1009 spi_imx->usedma = true;
1010 ret = spi_imx_dma_transfer(spi_imx, transfer);
1011 if (ret != -EAGAIN)
1012 return ret;
1013 }
1014 spi_imx->usedma = false;
1015
1016 return spi_imx_pio_transfer(spi, transfer);
1017}
1018
6cdeb002 1019static int spi_imx_setup(struct spi_device *spi)
b5f3294f 1020{
6c23e5d4
SH		 1021 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1022 int gpio = spi_imx->chipselect[spi->chip_select];
1023
f4d4ecfe 1024 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
b5f3294f
SH		 1025 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1026
8b17e055 1027 if (gpio_is_valid(gpio))
6c23e5d4
SH		 1028 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1029
6cdeb002 1030 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
b5f3294f
SH		 1031
1032 return 0;
1033}
1034
6cdeb002 1035static void spi_imx_cleanup(struct spi_device *spi)
b5f3294f
SH		 1036{
1037}
1038
9e556dcc
HS		 1039static int
1040spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1041{
1042 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1043 int ret;
1044
1045 ret = clk_enable(spi_imx->clk_per);
1046 if (ret)
1047 return ret;
1048
1049 ret = clk_enable(spi_imx->clk_ipg);
1050 if (ret) {
1051 clk_disable(spi_imx->clk_per);
1052 return ret;
1053 }
1054
1055 return 0;
1056}
1057
1058static int
1059spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1060{
1061 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1062
1063 clk_disable(spi_imx->clk_ipg);
1064 clk_disable(spi_imx->clk_per);
1065 return 0;
1066}
1067
fd4a319b 1068static int spi_imx_probe(struct platform_device *pdev)
b5f3294f 1069{
22a85e4c
SG		 1070 struct device_node *np = pdev->dev.of_node;
1071 const struct of_device_id *of_id =
1072 of_match_device(spi_imx_dt_ids, &pdev->dev);
1073 struct spi_imx_master *mxc_platform_info =
1074 dev_get_platdata(&pdev->dev);
b5f3294f 1075 struct spi_master *master;
6cdeb002 1076 struct spi_imx_data *spi_imx;
b5f3294f 1077 struct resource *res;
4b5d6aad 1078 int i, ret, num_cs, irq;
b5f3294f 1079
22a85e4c 1080 if (!np && !mxc_platform_info) {
b5f3294f
SH		 1081 dev_err(&pdev->dev, "can't get the platform data\n");
1082 return -EINVAL;
1083 }
1084
22a85e4c 1085 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
39ec0d38
LW		 1086 if (ret < 0) {
1087 if (mxc_platform_info)
1088 num_cs = mxc_platform_info->num_chipselect;
1089 else
1090 return ret;
1091 }
22a85e4c 1092
c2387cb9
SG		 1093 master = spi_alloc_master(&pdev->dev,
1094 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
b5f3294f
SH		 1095 if (!master)
1096 return -ENOMEM;
1097
1098 platform_set_drvdata(pdev, master);
1099
24778be2 1100 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
b5f3294f 1101 master->bus_num = pdev->id;
c2387cb9 1102 master->num_chipselect = num_cs;
b5f3294f 1103
6cdeb002 1104 spi_imx = spi_master_get_devdata(master);
94c69f76 1105 spi_imx->bitbang.master = master;
b5f3294f
SH		 1106
1107 for (i = 0; i < master->num_chipselect; i++) {
22a85e4c 1108 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
8b17e055 1109 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
22a85e4c 1110 cs_gpio = mxc_platform_info->chipselect[i];
4cc122ac
FE		 1111
1112 spi_imx->chipselect[i] = cs_gpio;
8b17e055 1113 if (!gpio_is_valid(cs_gpio))
b5f3294f 1114 continue;
4cc122ac 1115
130b82c0
FE		 1116 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1117 DRIVER_NAME);
b5f3294f 1118 if (ret) {
bbd050af 1119 dev_err(&pdev->dev, "can't get cs gpios\n");
130b82c0 1120 goto out_master_put;
b5f3294f 1121 }
b5f3294f
SH		 1122 }
1123
6cdeb002
UKK		 1124 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1125 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1126 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1127 spi_imx->bitbang.master->setup = spi_imx_setup;
1128 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
9e556dcc
HS		 1129 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1130 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
3910f2cf 1131 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
b5f3294f 1132
6cdeb002 1133 init_completion(&spi_imx->xfer_done);
b5f3294f 1134
22a85e4c 1135 spi_imx->devtype_data = of_id ? of_id->data :
04ee5854 1136 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
f4ba6315 1137
b5f3294f 1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130b82c0
FE		 1139 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1140 if (IS_ERR(spi_imx->base)) {
1141 ret = PTR_ERR(spi_imx->base);
1142 goto out_master_put;
b5f3294f
SH		 1143 }
1144
4b5d6aad
FE		 1145 irq = platform_get_irq(pdev, 0);
1146 if (irq < 0) {
1147 ret = irq;
130b82c0 1148 goto out_master_put;
b5f3294f
SH		 1149 }
1150
4b5d6aad 1151 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
8fc39b51 1152 dev_name(&pdev->dev), spi_imx);
b5f3294f 1153 if (ret) {
4b5d6aad 1154 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
130b82c0 1155 goto out_master_put;
b5f3294f
SH		 1156 }
1157
aa29d840
SH		 1158 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1159 if (IS_ERR(spi_imx->clk_ipg)) {
1160 ret = PTR_ERR(spi_imx->clk_ipg);
130b82c0 1161 goto out_master_put;
b5f3294f
SH		 1162 }
1163
aa29d840
SH		 1164 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1165 if (IS_ERR(spi_imx->clk_per)) {
1166 ret = PTR_ERR(spi_imx->clk_per);
130b82c0 1167 goto out_master_put;
aa29d840
SH		 1168 }
1169
83174626
FE		 1170 ret = clk_prepare_enable(spi_imx->clk_per);
1171 if (ret)
1172 goto out_master_put;
1173
1174 ret = clk_prepare_enable(spi_imx->clk_ipg);
1175 if (ret)
1176 goto out_put_per;
aa29d840
SH		 1177
1178 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
f62caccd
RG		 1179 /*
1180 * Only validated on i.mx6 now, can remove the constrain if validated on
1181 * other chips.
1182 */
1183 if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
1184 && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
1185 dev_err(&pdev->dev, "dma setup error,use pio instead\n");
b5f3294f 1186
edd501bb 1187 spi_imx->devtype_data->reset(spi_imx);
ce1807b2 1188
edd501bb 1189 spi_imx->devtype_data->intctrl(spi_imx, 0);
b5f3294f 1190
22a85e4c 1191 master->dev.of_node = pdev->dev.of_node;
6cdeb002 1192 ret = spi_bitbang_start(&spi_imx->bitbang);
b5f3294f
SH		 1193 if (ret) {
1194 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1195 goto out_clk_put;
1196 }
1197
1198 dev_info(&pdev->dev, "probed\n");
1199
9e556dcc
HS		 1200 clk_disable(spi_imx->clk_ipg);
1201 clk_disable(spi_imx->clk_per);
b5f3294f
SH		 1202 return ret;
1203
1204out_clk_put:
aa29d840 1205 clk_disable_unprepare(spi_imx->clk_ipg);
83174626
FE		 1206out_put_per:
1207 clk_disable_unprepare(spi_imx->clk_per);
130b82c0 1208out_master_put:
b5f3294f 1209 spi_master_put(master);
130b82c0 1210
b5f3294f
SH		 1211 return ret;
1212}
1213
fd4a319b 1214static int spi_imx_remove(struct platform_device *pdev)
b5f3294f
SH		 1215{
1216 struct spi_master *master = platform_get_drvdata(pdev);
6cdeb002 1217 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
b5f3294f 1218
6cdeb002 1219 spi_bitbang_stop(&spi_imx->bitbang);
b5f3294f 1220
6cdeb002 1221 writel(0, spi_imx->base + MXC_CSPICTRL);
fd40dccb
PDM		 1222 clk_unprepare(spi_imx->clk_ipg);
1223 clk_unprepare(spi_imx->clk_per);
f62caccd 1224 spi_imx_sdma_exit(spi_imx);
b5f3294f
SH		 1225 spi_master_put(master);
1226
b5f3294f
SH		 1227 return 0;
1228}
1229
6cdeb002 1230static struct platform_driver spi_imx_driver = {
b5f3294f
SH		 1231 .driver = {
1232 .name = DRIVER_NAME,
22a85e4c 1233 .of_match_table = spi_imx_dt_ids,
b5f3294f 1234 },
f4ba6315 1235 .id_table = spi_imx_devtype,
6cdeb002 1236 .probe = spi_imx_probe,
fd4a319b 1237 .remove = spi_imx_remove,
b5f3294f 1238};
940ab889 1239module_platform_driver(spi_imx_driver);
b5f3294f
SH		 1240
1241MODULE_DESCRIPTION("SPI Master Controller driver");
1242MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1243MODULE_LICENSE("GPL");
3133fba3 1244MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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