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a568231f LL |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Leilk Liu <leilk.liu@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/interrupt.h> | |
dd69a0a6 | 19 | #include <linux/io.h> |
a568231f LL |
20 | #include <linux/ioport.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
37457607 | 23 | #include <linux/of_gpio.h> |
a568231f LL |
24 | #include <linux/platform_device.h> |
25 | #include <linux/platform_data/spi-mt65xx.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/spi/spi.h> | |
28 | ||
29 | #define SPI_CFG0_REG 0x0000 | |
30 | #define SPI_CFG1_REG 0x0004 | |
31 | #define SPI_TX_SRC_REG 0x0008 | |
32 | #define SPI_RX_DST_REG 0x000c | |
33 | #define SPI_TX_DATA_REG 0x0010 | |
34 | #define SPI_RX_DATA_REG 0x0014 | |
35 | #define SPI_CMD_REG 0x0018 | |
36 | #define SPI_STATUS0_REG 0x001c | |
37 | #define SPI_PAD_SEL_REG 0x0024 | |
38 | ||
39 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 | |
40 | #define SPI_CFG0_SCK_LOW_OFFSET 8 | |
41 | #define SPI_CFG0_CS_HOLD_OFFSET 16 | |
42 | #define SPI_CFG0_CS_SETUP_OFFSET 24 | |
43 | ||
44 | #define SPI_CFG1_CS_IDLE_OFFSET 0 | |
45 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 | |
46 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 | |
47 | #define SPI_CFG1_GET_TICK_DLY_OFFSET 30 | |
48 | ||
49 | #define SPI_CFG1_CS_IDLE_MASK 0xff | |
50 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 | |
51 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 | |
52 | ||
a71d6ea6 LL |
53 | #define SPI_CMD_ACT BIT(0) |
54 | #define SPI_CMD_RESUME BIT(1) | |
a568231f LL |
55 | #define SPI_CMD_RST BIT(2) |
56 | #define SPI_CMD_PAUSE_EN BIT(4) | |
57 | #define SPI_CMD_DEASSERT BIT(5) | |
58 | #define SPI_CMD_CPHA BIT(8) | |
59 | #define SPI_CMD_CPOL BIT(9) | |
60 | #define SPI_CMD_RX_DMA BIT(10) | |
61 | #define SPI_CMD_TX_DMA BIT(11) | |
62 | #define SPI_CMD_TXMSBF BIT(12) | |
63 | #define SPI_CMD_RXMSBF BIT(13) | |
64 | #define SPI_CMD_RX_ENDIAN BIT(14) | |
65 | #define SPI_CMD_TX_ENDIAN BIT(15) | |
66 | #define SPI_CMD_FINISH_IE BIT(16) | |
67 | #define SPI_CMD_PAUSE_IE BIT(17) | |
68 | ||
a568231f LL |
69 | #define MT8173_SPI_MAX_PAD_SEL 3 |
70 | ||
50f8fec2 LL |
71 | #define MTK_SPI_PAUSE_INT_STATUS 0x2 |
72 | ||
a568231f LL |
73 | #define MTK_SPI_IDLE 0 |
74 | #define MTK_SPI_PAUSED 1 | |
75 | ||
76 | #define MTK_SPI_MAX_FIFO_SIZE 32 | |
77 | #define MTK_SPI_PACKET_SIZE 1024 | |
78 | ||
79 | struct mtk_spi_compatible { | |
af57937e LL |
80 | bool need_pad_sel; |
81 | /* Must explicitly send dummy Tx bytes to do Rx only transfer */ | |
82 | bool must_tx; | |
a568231f LL |
83 | }; |
84 | ||
85 | struct mtk_spi { | |
86 | void __iomem *base; | |
87 | u32 state; | |
37457607 LL |
88 | int pad_num; |
89 | u32 *pad_sel; | |
adcbcfea | 90 | struct clk *parent_clk, *sel_clk, *spi_clk; |
a568231f LL |
91 | struct spi_transfer *cur_transfer; |
92 | u32 xfer_len; | |
93 | struct scatterlist *tx_sgl, *rx_sgl; | |
94 | u32 tx_sgl_len, rx_sgl_len; | |
95 | const struct mtk_spi_compatible *dev_comp; | |
96 | }; | |
97 | ||
4eaf6f73 | 98 | static const struct mtk_spi_compatible mtk_common_compat; |
a568231f | 99 | static const struct mtk_spi_compatible mt8173_compat = { |
af57937e LL |
100 | .need_pad_sel = true, |
101 | .must_tx = true, | |
a568231f LL |
102 | }; |
103 | ||
104 | /* | |
105 | * A piece of default chip info unless the platform | |
106 | * supplies it. | |
107 | */ | |
108 | static const struct mtk_chip_config mtk_default_chip_info = { | |
109 | .rx_mlsb = 1, | |
110 | .tx_mlsb = 1, | |
a568231f LL |
111 | }; |
112 | ||
113 | static const struct of_device_id mtk_spi_of_match[] = { | |
4eaf6f73 LL |
114 | { .compatible = "mediatek,mt6589-spi", |
115 | .data = (void *)&mtk_common_compat, | |
116 | }, | |
117 | { .compatible = "mediatek,mt8135-spi", | |
118 | .data = (void *)&mtk_common_compat, | |
119 | }, | |
120 | { .compatible = "mediatek,mt8173-spi", | |
121 | .data = (void *)&mt8173_compat, | |
122 | }, | |
a568231f LL |
123 | {} |
124 | }; | |
125 | MODULE_DEVICE_TABLE(of, mtk_spi_of_match); | |
126 | ||
127 | static void mtk_spi_reset(struct mtk_spi *mdata) | |
128 | { | |
129 | u32 reg_val; | |
130 | ||
131 | /* set the software reset bit in SPI_CMD_REG. */ | |
132 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
133 | reg_val |= SPI_CMD_RST; | |
134 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
135 | ||
136 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
137 | reg_val &= ~SPI_CMD_RST; | |
138 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
139 | } | |
140 | ||
79b5d3f2 LL |
141 | static int mtk_spi_prepare_message(struct spi_master *master, |
142 | struct spi_message *msg) | |
a568231f | 143 | { |
79b5d3f2 | 144 | u16 cpha, cpol; |
a568231f | 145 | u32 reg_val; |
79b5d3f2 | 146 | struct spi_device *spi = msg->spi; |
58a984c7 | 147 | struct mtk_chip_config *chip_config = spi->controller_data; |
79b5d3f2 LL |
148 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
149 | ||
150 | cpha = spi->mode & SPI_CPHA ? 1 : 0; | |
151 | cpol = spi->mode & SPI_CPOL ? 1 : 0; | |
152 | ||
79b5d3f2 LL |
153 | reg_val = readl(mdata->base + SPI_CMD_REG); |
154 | if (cpha) | |
155 | reg_val |= SPI_CMD_CPHA; | |
156 | else | |
157 | reg_val &= ~SPI_CMD_CPHA; | |
158 | if (cpol) | |
159 | reg_val |= SPI_CMD_CPOL; | |
160 | else | |
161 | reg_val &= ~SPI_CMD_CPOL; | |
a568231f LL |
162 | |
163 | /* set the mlsbx and mlsbtx */ | |
a71d6ea6 LL |
164 | if (chip_config->tx_mlsb) |
165 | reg_val |= SPI_CMD_TXMSBF; | |
166 | else | |
167 | reg_val &= ~SPI_CMD_TXMSBF; | |
168 | if (chip_config->rx_mlsb) | |
169 | reg_val |= SPI_CMD_RXMSBF; | |
170 | else | |
171 | reg_val &= ~SPI_CMD_RXMSBF; | |
a568231f LL |
172 | |
173 | /* set the tx/rx endian */ | |
44f636da LL |
174 | #ifdef __LITTLE_ENDIAN |
175 | reg_val &= ~SPI_CMD_TX_ENDIAN; | |
176 | reg_val &= ~SPI_CMD_RX_ENDIAN; | |
177 | #else | |
178 | reg_val |= SPI_CMD_TX_ENDIAN; | |
179 | reg_val |= SPI_CMD_RX_ENDIAN; | |
180 | #endif | |
a568231f LL |
181 | |
182 | /* set finish and pause interrupt always enable */ | |
15293324 | 183 | reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; |
a568231f LL |
184 | |
185 | /* disable dma mode */ | |
186 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); | |
187 | ||
188 | /* disable deassert mode */ | |
189 | reg_val &= ~SPI_CMD_DEASSERT; | |
190 | ||
191 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
192 | ||
193 | /* pad select */ | |
194 | if (mdata->dev_comp->need_pad_sel) | |
37457607 LL |
195 | writel(mdata->pad_sel[spi->chip_select], |
196 | mdata->base + SPI_PAD_SEL_REG); | |
a568231f LL |
197 | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static void mtk_spi_set_cs(struct spi_device *spi, bool enable) | |
202 | { | |
203 | u32 reg_val; | |
204 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
205 | ||
206 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
6583d203 | 207 | if (!enable) { |
a568231f | 208 | reg_val |= SPI_CMD_PAUSE_EN; |
6583d203 LL |
209 | writel(reg_val, mdata->base + SPI_CMD_REG); |
210 | } else { | |
a568231f | 211 | reg_val &= ~SPI_CMD_PAUSE_EN; |
6583d203 LL |
212 | writel(reg_val, mdata->base + SPI_CMD_REG); |
213 | mdata->state = MTK_SPI_IDLE; | |
214 | mtk_spi_reset(mdata); | |
215 | } | |
a568231f LL |
216 | } |
217 | ||
218 | static void mtk_spi_prepare_transfer(struct spi_master *master, | |
219 | struct spi_transfer *xfer) | |
220 | { | |
2ce0acf5 | 221 | u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; |
a568231f LL |
222 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
223 | ||
224 | spi_clk_hz = clk_get_rate(mdata->spi_clk); | |
225 | if (xfer->speed_hz < spi_clk_hz / 2) | |
226 | div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); | |
227 | else | |
228 | div = 1; | |
229 | ||
2ce0acf5 LL |
230 | sck_time = (div + 1) / 2; |
231 | cs_time = sck_time * 2; | |
a568231f | 232 | |
2ce0acf5 LL |
233 | reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); |
234 | reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); | |
235 | reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); | |
236 | reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); | |
a568231f LL |
237 | writel(reg_val, mdata->base + SPI_CFG0_REG); |
238 | ||
239 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
240 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; | |
2ce0acf5 | 241 | reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); |
a568231f LL |
242 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
243 | } | |
244 | ||
245 | static void mtk_spi_setup_packet(struct spi_master *master) | |
246 | { | |
247 | u32 packet_size, packet_loop, reg_val; | |
248 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
249 | ||
50f8fec2 | 250 | packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); |
a568231f LL |
251 | packet_loop = mdata->xfer_len / packet_size; |
252 | ||
253 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
50f8fec2 | 254 | reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); |
a568231f LL |
255 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; |
256 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; | |
257 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
258 | } | |
259 | ||
260 | static void mtk_spi_enable_transfer(struct spi_master *master) | |
261 | { | |
50f8fec2 | 262 | u32 cmd; |
a568231f LL |
263 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
264 | ||
265 | cmd = readl(mdata->base + SPI_CMD_REG); | |
266 | if (mdata->state == MTK_SPI_IDLE) | |
a71d6ea6 | 267 | cmd |= SPI_CMD_ACT; |
a568231f | 268 | else |
a71d6ea6 | 269 | cmd |= SPI_CMD_RESUME; |
a568231f LL |
270 | writel(cmd, mdata->base + SPI_CMD_REG); |
271 | } | |
272 | ||
50f8fec2 | 273 | static int mtk_spi_get_mult_delta(u32 xfer_len) |
a568231f | 274 | { |
50f8fec2 | 275 | u32 mult_delta; |
a568231f LL |
276 | |
277 | if (xfer_len > MTK_SPI_PACKET_SIZE) | |
278 | mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; | |
279 | else | |
280 | mult_delta = 0; | |
281 | ||
282 | return mult_delta; | |
283 | } | |
284 | ||
285 | static void mtk_spi_update_mdata_len(struct spi_master *master) | |
286 | { | |
287 | int mult_delta; | |
288 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
289 | ||
290 | if (mdata->tx_sgl_len && mdata->rx_sgl_len) { | |
291 | if (mdata->tx_sgl_len > mdata->rx_sgl_len) { | |
292 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
293 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
294 | mdata->rx_sgl_len = mult_delta; | |
295 | mdata->tx_sgl_len -= mdata->xfer_len; | |
296 | } else { | |
297 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
298 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
299 | mdata->tx_sgl_len = mult_delta; | |
300 | mdata->rx_sgl_len -= mdata->xfer_len; | |
301 | } | |
302 | } else if (mdata->tx_sgl_len) { | |
303 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
304 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
305 | mdata->tx_sgl_len = mult_delta; | |
306 | } else if (mdata->rx_sgl_len) { | |
307 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
308 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
309 | mdata->rx_sgl_len = mult_delta; | |
310 | } | |
311 | } | |
312 | ||
313 | static void mtk_spi_setup_dma_addr(struct spi_master *master, | |
314 | struct spi_transfer *xfer) | |
315 | { | |
316 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
317 | ||
318 | if (mdata->tx_sgl) | |
39ba928f | 319 | writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG); |
a568231f | 320 | if (mdata->rx_sgl) |
39ba928f | 321 | writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG); |
a568231f LL |
322 | } |
323 | ||
324 | static int mtk_spi_fifo_transfer(struct spi_master *master, | |
325 | struct spi_device *spi, | |
326 | struct spi_transfer *xfer) | |
327 | { | |
44f636da | 328 | int cnt; |
a568231f LL |
329 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
330 | ||
331 | mdata->cur_transfer = xfer; | |
332 | mdata->xfer_len = xfer->len; | |
333 | mtk_spi_prepare_transfer(master, xfer); | |
334 | mtk_spi_setup_packet(master); | |
335 | ||
336 | if (xfer->len % 4) | |
337 | cnt = xfer->len / 4 + 1; | |
338 | else | |
339 | cnt = xfer->len / 4; | |
44f636da | 340 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); |
a568231f LL |
341 | |
342 | mtk_spi_enable_transfer(master); | |
343 | ||
344 | return 1; | |
345 | } | |
346 | ||
347 | static int mtk_spi_dma_transfer(struct spi_master *master, | |
348 | struct spi_device *spi, | |
349 | struct spi_transfer *xfer) | |
350 | { | |
351 | int cmd; | |
352 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
353 | ||
354 | mdata->tx_sgl = NULL; | |
355 | mdata->rx_sgl = NULL; | |
356 | mdata->tx_sgl_len = 0; | |
357 | mdata->rx_sgl_len = 0; | |
358 | mdata->cur_transfer = xfer; | |
359 | ||
360 | mtk_spi_prepare_transfer(master, xfer); | |
361 | ||
362 | cmd = readl(mdata->base + SPI_CMD_REG); | |
363 | if (xfer->tx_buf) | |
364 | cmd |= SPI_CMD_TX_DMA; | |
365 | if (xfer->rx_buf) | |
366 | cmd |= SPI_CMD_RX_DMA; | |
367 | writel(cmd, mdata->base + SPI_CMD_REG); | |
368 | ||
369 | if (xfer->tx_buf) | |
370 | mdata->tx_sgl = xfer->tx_sg.sgl; | |
371 | if (xfer->rx_buf) | |
372 | mdata->rx_sgl = xfer->rx_sg.sgl; | |
373 | ||
374 | if (mdata->tx_sgl) { | |
375 | xfer->tx_dma = sg_dma_address(mdata->tx_sgl); | |
376 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
377 | } | |
378 | if (mdata->rx_sgl) { | |
379 | xfer->rx_dma = sg_dma_address(mdata->rx_sgl); | |
380 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
381 | } | |
382 | ||
383 | mtk_spi_update_mdata_len(master); | |
384 | mtk_spi_setup_packet(master); | |
385 | mtk_spi_setup_dma_addr(master, xfer); | |
386 | mtk_spi_enable_transfer(master); | |
387 | ||
388 | return 1; | |
389 | } | |
390 | ||
391 | static int mtk_spi_transfer_one(struct spi_master *master, | |
392 | struct spi_device *spi, | |
393 | struct spi_transfer *xfer) | |
394 | { | |
395 | if (master->can_dma(master, spi, xfer)) | |
396 | return mtk_spi_dma_transfer(master, spi, xfer); | |
397 | else | |
398 | return mtk_spi_fifo_transfer(master, spi, xfer); | |
399 | } | |
400 | ||
401 | static bool mtk_spi_can_dma(struct spi_master *master, | |
402 | struct spi_device *spi, | |
403 | struct spi_transfer *xfer) | |
404 | { | |
405 | return xfer->len > MTK_SPI_MAX_FIFO_SIZE; | |
406 | } | |
407 | ||
58a984c7 LL |
408 | static int mtk_spi_setup(struct spi_device *spi) |
409 | { | |
410 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
411 | ||
412 | if (!spi->controller_data) | |
413 | spi->controller_data = (void *)&mtk_default_chip_info; | |
414 | ||
98c8dccf | 415 | if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) |
37457607 LL |
416 | gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); |
417 | ||
58a984c7 LL |
418 | return 0; |
419 | } | |
420 | ||
a568231f LL |
421 | static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) |
422 | { | |
44f636da | 423 | u32 cmd, reg_val, cnt; |
a568231f LL |
424 | struct spi_master *master = dev_id; |
425 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
426 | struct spi_transfer *trans = mdata->cur_transfer; | |
427 | ||
428 | reg_val = readl(mdata->base + SPI_STATUS0_REG); | |
50f8fec2 | 429 | if (reg_val & MTK_SPI_PAUSE_INT_STATUS) |
a568231f LL |
430 | mdata->state = MTK_SPI_PAUSED; |
431 | else | |
432 | mdata->state = MTK_SPI_IDLE; | |
433 | ||
434 | if (!master->can_dma(master, master->cur_msg->spi, trans)) { | |
a568231f | 435 | if (trans->rx_buf) { |
44f636da LL |
436 | if (mdata->xfer_len % 4) |
437 | cnt = mdata->xfer_len / 4 + 1; | |
438 | else | |
439 | cnt = mdata->xfer_len / 4; | |
440 | ioread32_rep(mdata->base + SPI_RX_DATA_REG, | |
441 | trans->rx_buf, cnt); | |
a568231f LL |
442 | } |
443 | spi_finalize_current_transfer(master); | |
444 | return IRQ_HANDLED; | |
445 | } | |
446 | ||
447 | if (mdata->tx_sgl) | |
448 | trans->tx_dma += mdata->xfer_len; | |
449 | if (mdata->rx_sgl) | |
450 | trans->rx_dma += mdata->xfer_len; | |
451 | ||
452 | if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { | |
453 | mdata->tx_sgl = sg_next(mdata->tx_sgl); | |
454 | if (mdata->tx_sgl) { | |
455 | trans->tx_dma = sg_dma_address(mdata->tx_sgl); | |
456 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
457 | } | |
458 | } | |
459 | if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { | |
460 | mdata->rx_sgl = sg_next(mdata->rx_sgl); | |
461 | if (mdata->rx_sgl) { | |
462 | trans->rx_dma = sg_dma_address(mdata->rx_sgl); | |
463 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
464 | } | |
465 | } | |
466 | ||
467 | if (!mdata->tx_sgl && !mdata->rx_sgl) { | |
468 | /* spi disable dma */ | |
469 | cmd = readl(mdata->base + SPI_CMD_REG); | |
470 | cmd &= ~SPI_CMD_TX_DMA; | |
471 | cmd &= ~SPI_CMD_RX_DMA; | |
472 | writel(cmd, mdata->base + SPI_CMD_REG); | |
473 | ||
474 | spi_finalize_current_transfer(master); | |
475 | return IRQ_HANDLED; | |
476 | } | |
477 | ||
478 | mtk_spi_update_mdata_len(master); | |
479 | mtk_spi_setup_packet(master); | |
480 | mtk_spi_setup_dma_addr(master, trans); | |
481 | mtk_spi_enable_transfer(master); | |
482 | ||
483 | return IRQ_HANDLED; | |
484 | } | |
485 | ||
486 | static int mtk_spi_probe(struct platform_device *pdev) | |
487 | { | |
488 | struct spi_master *master; | |
489 | struct mtk_spi *mdata; | |
490 | const struct of_device_id *of_id; | |
491 | struct resource *res; | |
37457607 | 492 | int i, irq, ret; |
a568231f LL |
493 | |
494 | master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); | |
495 | if (!master) { | |
496 | dev_err(&pdev->dev, "failed to alloc spi master\n"); | |
497 | return -ENOMEM; | |
498 | } | |
499 | ||
500 | master->auto_runtime_pm = true; | |
501 | master->dev.of_node = pdev->dev.of_node; | |
502 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
503 | ||
504 | master->set_cs = mtk_spi_set_cs; | |
a568231f LL |
505 | master->prepare_message = mtk_spi_prepare_message; |
506 | master->transfer_one = mtk_spi_transfer_one; | |
507 | master->can_dma = mtk_spi_can_dma; | |
58a984c7 | 508 | master->setup = mtk_spi_setup; |
a568231f LL |
509 | |
510 | of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); | |
511 | if (!of_id) { | |
512 | dev_err(&pdev->dev, "failed to probe of_node\n"); | |
513 | ret = -EINVAL; | |
514 | goto err_put_master; | |
515 | } | |
516 | ||
517 | mdata = spi_master_get_devdata(master); | |
518 | mdata->dev_comp = of_id->data; | |
519 | if (mdata->dev_comp->must_tx) | |
520 | master->flags = SPI_MASTER_MUST_TX; | |
521 | ||
522 | if (mdata->dev_comp->need_pad_sel) { | |
37457607 LL |
523 | mdata->pad_num = of_property_count_u32_elems( |
524 | pdev->dev.of_node, | |
525 | "mediatek,pad-select"); | |
526 | if (mdata->pad_num < 0) { | |
527 | dev_err(&pdev->dev, | |
528 | "No 'mediatek,pad-select' property\n"); | |
529 | ret = -EINVAL; | |
a568231f LL |
530 | goto err_put_master; |
531 | } | |
532 | ||
37457607 LL |
533 | mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, |
534 | sizeof(u32), GFP_KERNEL); | |
535 | if (!mdata->pad_sel) { | |
536 | ret = -ENOMEM; | |
a568231f LL |
537 | goto err_put_master; |
538 | } | |
37457607 LL |
539 | |
540 | for (i = 0; i < mdata->pad_num; i++) { | |
541 | of_property_read_u32_index(pdev->dev.of_node, | |
542 | "mediatek,pad-select", | |
543 | i, &mdata->pad_sel[i]); | |
544 | if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { | |
545 | dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", | |
546 | i, mdata->pad_sel[i]); | |
547 | ret = -EINVAL; | |
548 | goto err_put_master; | |
549 | } | |
550 | } | |
a568231f LL |
551 | } |
552 | ||
553 | platform_set_drvdata(pdev, master); | |
554 | ||
555 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
556 | if (!res) { | |
557 | ret = -ENODEV; | |
558 | dev_err(&pdev->dev, "failed to determine base address\n"); | |
559 | goto err_put_master; | |
560 | } | |
561 | ||
562 | mdata->base = devm_ioremap_resource(&pdev->dev, res); | |
563 | if (IS_ERR(mdata->base)) { | |
564 | ret = PTR_ERR(mdata->base); | |
565 | goto err_put_master; | |
566 | } | |
567 | ||
568 | irq = platform_get_irq(pdev, 0); | |
569 | if (irq < 0) { | |
570 | dev_err(&pdev->dev, "failed to get irq (%d)\n", irq); | |
571 | ret = irq; | |
572 | goto err_put_master; | |
573 | } | |
574 | ||
575 | if (!pdev->dev.dma_mask) | |
576 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
577 | ||
578 | ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, | |
579 | IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); | |
580 | if (ret) { | |
581 | dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); | |
582 | goto err_put_master; | |
583 | } | |
584 | ||
a568231f LL |
585 | mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); |
586 | if (IS_ERR(mdata->parent_clk)) { | |
587 | ret = PTR_ERR(mdata->parent_clk); | |
588 | dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); | |
589 | goto err_put_master; | |
590 | } | |
591 | ||
adcbcfea LL |
592 | mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); |
593 | if (IS_ERR(mdata->sel_clk)) { | |
e26d15f7 | 594 | ret = PTR_ERR(mdata->sel_clk); |
adcbcfea | 595 | dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); |
a568231f LL |
596 | goto err_put_master; |
597 | } | |
598 | ||
adcbcfea LL |
599 | mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); |
600 | if (IS_ERR(mdata->spi_clk)) { | |
e26d15f7 | 601 | ret = PTR_ERR(mdata->spi_clk); |
adcbcfea | 602 | dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); |
a568231f LL |
603 | goto err_put_master; |
604 | } | |
605 | ||
606 | ret = clk_prepare_enable(mdata->spi_clk); | |
607 | if (ret < 0) { | |
608 | dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); | |
609 | goto err_put_master; | |
610 | } | |
611 | ||
adcbcfea | 612 | ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); |
a568231f LL |
613 | if (ret < 0) { |
614 | dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); | |
e38da37f LL |
615 | clk_disable_unprepare(mdata->spi_clk); |
616 | goto err_put_master; | |
a568231f LL |
617 | } |
618 | ||
619 | clk_disable_unprepare(mdata->spi_clk); | |
620 | ||
621 | pm_runtime_enable(&pdev->dev); | |
622 | ||
623 | ret = devm_spi_register_master(&pdev->dev, master); | |
624 | if (ret) { | |
625 | dev_err(&pdev->dev, "failed to register master (%d)\n", ret); | |
e38da37f | 626 | goto err_disable_runtime_pm; |
a568231f LL |
627 | } |
628 | ||
37457607 LL |
629 | if (mdata->dev_comp->need_pad_sel) { |
630 | if (mdata->pad_num != master->num_chipselect) { | |
631 | dev_err(&pdev->dev, | |
632 | "pad_num does not match num_chipselect(%d != %d)\n", | |
633 | mdata->pad_num, master->num_chipselect); | |
634 | ret = -EINVAL; | |
e38da37f | 635 | goto err_disable_runtime_pm; |
37457607 LL |
636 | } |
637 | ||
98c8dccf NB |
638 | if (!master->cs_gpios && master->num_chipselect > 1) { |
639 | dev_err(&pdev->dev, | |
640 | "cs_gpios not specified and num_chipselect > 1\n"); | |
641 | ret = -EINVAL; | |
e38da37f | 642 | goto err_disable_runtime_pm; |
98c8dccf NB |
643 | } |
644 | ||
645 | if (master->cs_gpios) { | |
646 | for (i = 0; i < master->num_chipselect; i++) { | |
647 | ret = devm_gpio_request(&pdev->dev, | |
648 | master->cs_gpios[i], | |
649 | dev_name(&pdev->dev)); | |
650 | if (ret) { | |
651 | dev_err(&pdev->dev, | |
652 | "can't get CS GPIO %i\n", i); | |
e38da37f | 653 | goto err_disable_runtime_pm; |
98c8dccf | 654 | } |
37457607 LL |
655 | } |
656 | } | |
657 | } | |
658 | ||
a568231f LL |
659 | return 0; |
660 | ||
e38da37f LL |
661 | err_disable_runtime_pm: |
662 | pm_runtime_disable(&pdev->dev); | |
a568231f LL |
663 | err_put_master: |
664 | spi_master_put(master); | |
665 | ||
666 | return ret; | |
667 | } | |
668 | ||
669 | static int mtk_spi_remove(struct platform_device *pdev) | |
670 | { | |
671 | struct spi_master *master = platform_get_drvdata(pdev); | |
672 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
673 | ||
674 | pm_runtime_disable(&pdev->dev); | |
675 | ||
676 | mtk_spi_reset(mdata); | |
a568231f LL |
677 | spi_master_put(master); |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | #ifdef CONFIG_PM_SLEEP | |
683 | static int mtk_spi_suspend(struct device *dev) | |
684 | { | |
685 | int ret; | |
686 | struct spi_master *master = dev_get_drvdata(dev); | |
687 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
688 | ||
689 | ret = spi_master_suspend(master); | |
690 | if (ret) | |
691 | return ret; | |
692 | ||
693 | if (!pm_runtime_suspended(dev)) | |
694 | clk_disable_unprepare(mdata->spi_clk); | |
695 | ||
696 | return ret; | |
697 | } | |
698 | ||
699 | static int mtk_spi_resume(struct device *dev) | |
700 | { | |
701 | int ret; | |
702 | struct spi_master *master = dev_get_drvdata(dev); | |
703 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
704 | ||
705 | if (!pm_runtime_suspended(dev)) { | |
706 | ret = clk_prepare_enable(mdata->spi_clk); | |
13da5a0b LL |
707 | if (ret < 0) { |
708 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
a568231f | 709 | return ret; |
13da5a0b | 710 | } |
a568231f LL |
711 | } |
712 | ||
713 | ret = spi_master_resume(master); | |
714 | if (ret < 0) | |
715 | clk_disable_unprepare(mdata->spi_clk); | |
716 | ||
717 | return ret; | |
718 | } | |
719 | #endif /* CONFIG_PM_SLEEP */ | |
720 | ||
721 | #ifdef CONFIG_PM | |
722 | static int mtk_spi_runtime_suspend(struct device *dev) | |
723 | { | |
724 | struct spi_master *master = dev_get_drvdata(dev); | |
725 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
726 | ||
727 | clk_disable_unprepare(mdata->spi_clk); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | static int mtk_spi_runtime_resume(struct device *dev) | |
733 | { | |
734 | struct spi_master *master = dev_get_drvdata(dev); | |
735 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
13da5a0b LL |
736 | int ret; |
737 | ||
738 | ret = clk_prepare_enable(mdata->spi_clk); | |
739 | if (ret < 0) { | |
740 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); | |
741 | return ret; | |
742 | } | |
a568231f | 743 | |
13da5a0b | 744 | return 0; |
a568231f LL |
745 | } |
746 | #endif /* CONFIG_PM */ | |
747 | ||
748 | static const struct dev_pm_ops mtk_spi_pm = { | |
749 | SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) | |
750 | SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, | |
751 | mtk_spi_runtime_resume, NULL) | |
752 | }; | |
753 | ||
4299aaaa | 754 | static struct platform_driver mtk_spi_driver = { |
a568231f LL |
755 | .driver = { |
756 | .name = "mtk-spi", | |
757 | .pm = &mtk_spi_pm, | |
758 | .of_match_table = mtk_spi_of_match, | |
759 | }, | |
760 | .probe = mtk_spi_probe, | |
761 | .remove = mtk_spi_remove, | |
762 | }; | |
763 | ||
764 | module_platform_driver(mtk_spi_driver); | |
765 | ||
766 | MODULE_DESCRIPTION("MTK SPI Controller driver"); | |
767 | MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); | |
768 | MODULE_LICENSE("GPL v2"); | |
e4001885 | 769 | MODULE_ALIAS("platform:mtk-spi"); |