Commit | Line | Data |
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646781d3 MV |
1 | /* |
2 | * Freescale MXS SPI master driver | |
3 | * | |
4 | * Copyright 2012 DENX Software Engineering, GmbH. | |
5 | * Copyright 2012 Freescale Semiconductor, Inc. | |
6 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
7 | * | |
8 | * Rework and transition to new API by: | |
9 | * Marek Vasut <marex@denx.de> | |
10 | * | |
11 | * Based on previous attempt by: | |
12 | * Fabio Estevam <fabio.estevam@freescale.com> | |
13 | * | |
14 | * Based on code from U-Boot bootloader by: | |
15 | * Marek Vasut <marex@denx.de> | |
16 | * | |
17 | * Based on spi-stmp.c, which is: | |
18 | * Author: Dmitry Pervushin <dimka@embeddedalley.com> | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_gpio.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/dmaengine.h> | |
42 | #include <linux/highmem.h> | |
43 | #include <linux/clk.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/completion.h> | |
46 | #include <linux/gpio.h> | |
47 | #include <linux/regulator/consumer.h> | |
48 | #include <linux/module.h> | |
646781d3 MV |
49 | #include <linux/stmp_device.h> |
50 | #include <linux/spi/spi.h> | |
51 | #include <linux/spi/mxs-spi.h> | |
52 | ||
53 | #define DRIVER_NAME "mxs-spi" | |
54 | ||
010b4818 MV |
55 | /* Use 10S timeout for very long transfers, it should suffice. */ |
56 | #define SSP_TIMEOUT 10000 | |
646781d3 | 57 | |
474afc04 MV |
58 | #define SG_MAXLEN 0xff00 |
59 | ||
28cad125 TP |
60 | /* |
61 | * Flags for txrx functions. More efficient that using an argument register for | |
62 | * each one. | |
63 | */ | |
64 | #define TXRX_WRITE (1<<0) /* This is a write */ | |
65 | #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */ | |
66 | ||
646781d3 MV |
67 | struct mxs_spi { |
68 | struct mxs_ssp ssp; | |
474afc04 | 69 | struct completion c; |
646781d3 MV |
70 | }; |
71 | ||
72 | static int mxs_spi_setup_transfer(struct spi_device *dev, | |
73 | struct spi_transfer *t) | |
74 | { | |
75 | struct mxs_spi *spi = spi_master_get_devdata(dev->master); | |
76 | struct mxs_ssp *ssp = &spi->ssp; | |
646781d3 MV |
77 | uint32_t hz = 0; |
78 | ||
646781d3 MV |
79 | hz = dev->max_speed_hz; |
80 | if (t && t->speed_hz) | |
81 | hz = min(hz, t->speed_hz); | |
82 | if (hz == 0) { | |
83 | dev_err(&dev->dev, "Cannot continue with zero clock\n"); | |
84 | return -EINVAL; | |
85 | } | |
86 | ||
87 | mxs_ssp_set_clk_rate(ssp, hz); | |
88 | ||
58f46e41 TP |
89 | writel(BM_SSP_CTRL0_LOCK_CS, |
90 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
646781d3 MV |
91 | writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | |
92 | BF_SSP_CTRL1_WORD_LENGTH | |
93 | (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | | |
94 | ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | | |
95 | ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), | |
96 | ssp->base + HW_SSP_CTRL1(ssp)); | |
97 | ||
98 | writel(0x0, ssp->base + HW_SSP_CMD0); | |
99 | writel(0x0, ssp->base + HW_SSP_CMD1); | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | static int mxs_spi_setup(struct spi_device *dev) | |
105 | { | |
646781d3 MV |
106 | if (!dev->bits_per_word) |
107 | dev->bits_per_word = 8; | |
108 | ||
9c97e342 | 109 | return 0; |
646781d3 MV |
110 | } |
111 | ||
112 | static uint32_t mxs_spi_cs_to_reg(unsigned cs) | |
113 | { | |
114 | uint32_t select = 0; | |
115 | ||
116 | /* | |
117 | * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 | |
118 | * | |
119 | * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ | |
120 | * in HW_SSP_CTRL0 register do have multiple usage, please refer to | |
121 | * the datasheet for further details. In SPI mode, they are used to | |
122 | * toggle the chip-select lines (nCS pins). | |
123 | */ | |
124 | if (cs & 1) | |
125 | select |= BM_SSP_CTRL0_WAIT_FOR_CMD; | |
126 | if (cs & 2) | |
127 | select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
128 | ||
129 | return select; | |
130 | } | |
131 | ||
646781d3 MV |
132 | static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) |
133 | { | |
f13639dc | 134 | const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); |
646781d3 MV |
135 | struct mxs_ssp *ssp = &spi->ssp; |
136 | uint32_t reg; | |
137 | ||
f13639dc | 138 | do { |
646781d3 MV |
139 | reg = readl_relaxed(ssp->base + offset); |
140 | ||
f13639dc MV |
141 | if (!set) |
142 | reg = ~reg; | |
646781d3 | 143 | |
f13639dc | 144 | reg &= mask; |
646781d3 | 145 | |
f13639dc MV |
146 | if (reg == mask) |
147 | return 0; | |
148 | } while (time_before(jiffies, timeout)); | |
646781d3 | 149 | |
f13639dc | 150 | return -ETIMEDOUT; |
646781d3 MV |
151 | } |
152 | ||
474afc04 MV |
153 | static void mxs_ssp_dma_irq_callback(void *param) |
154 | { | |
155 | struct mxs_spi *spi = param; | |
156 | complete(&spi->c); | |
157 | } | |
158 | ||
159 | static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) | |
160 | { | |
161 | struct mxs_ssp *ssp = dev_id; | |
162 | dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", | |
163 | __func__, __LINE__, | |
164 | readl(ssp->base + HW_SSP_CTRL1(ssp)), | |
165 | readl(ssp->base + HW_SSP_STATUS(ssp))); | |
166 | return IRQ_HANDLED; | |
167 | } | |
168 | ||
0b782f70 | 169 | static int mxs_spi_txrx_dma(struct mxs_spi *spi, |
474afc04 | 170 | unsigned char *buf, int len, |
28cad125 | 171 | unsigned int flags) |
474afc04 MV |
172 | { |
173 | struct mxs_ssp *ssp = &spi->ssp; | |
010b4818 MV |
174 | struct dma_async_tx_descriptor *desc = NULL; |
175 | const bool vmalloced_buf = is_vmalloc_addr(buf); | |
176 | const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN; | |
177 | const int sgs = DIV_ROUND_UP(len, desc_len); | |
474afc04 | 178 | int sg_count; |
010b4818 MV |
179 | int min, ret; |
180 | uint32_t ctrl0; | |
181 | struct page *vm_page; | |
182 | void *sg_buf; | |
183 | struct { | |
184 | uint32_t pio[4]; | |
185 | struct scatterlist sg; | |
186 | } *dma_xfer; | |
187 | ||
188 | if (!len) | |
474afc04 | 189 | return -EINVAL; |
010b4818 MV |
190 | |
191 | dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL); | |
192 | if (!dma_xfer) | |
193 | return -ENOMEM; | |
474afc04 | 194 | |
41682e03 | 195 | INIT_COMPLETION(spi->c); |
474afc04 | 196 | |
0b782f70 | 197 | /* Chip select was already programmed into CTRL0 */ |
010b4818 | 198 | ctrl0 = readl(ssp->base + HW_SSP_CTRL0); |
df23286e TP |
199 | ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | |
200 | BM_SSP_CTRL0_READ); | |
0b782f70 | 201 | ctrl0 |= BM_SSP_CTRL0_DATA_XFER; |
010b4818 | 202 | |
28cad125 | 203 | if (!(flags & TXRX_WRITE)) |
010b4818 | 204 | ctrl0 |= BM_SSP_CTRL0_READ; |
474afc04 MV |
205 | |
206 | /* Queue the DMA data transfer. */ | |
010b4818 | 207 | for (sg_count = 0; sg_count < sgs; sg_count++) { |
28cad125 | 208 | /* Prepare the transfer descriptor. */ |
010b4818 MV |
209 | min = min(len, desc_len); |
210 | ||
28cad125 TP |
211 | /* |
212 | * De-assert CS on last segment if flag is set (i.e., no more | |
213 | * transfers will follow) | |
214 | */ | |
215 | if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS)) | |
010b4818 MV |
216 | ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; |
217 | ||
ba486a2a JL |
218 | if (ssp->devid == IMX23_SSP) { |
219 | ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; | |
010b4818 | 220 | ctrl0 |= min; |
ba486a2a | 221 | } |
010b4818 MV |
222 | |
223 | dma_xfer[sg_count].pio[0] = ctrl0; | |
224 | dma_xfer[sg_count].pio[3] = min; | |
225 | ||
226 | if (vmalloced_buf) { | |
227 | vm_page = vmalloc_to_page(buf); | |
228 | if (!vm_page) { | |
229 | ret = -ENOMEM; | |
230 | goto err_vmalloc; | |
231 | } | |
232 | sg_buf = page_address(vm_page) + | |
233 | ((size_t)buf & ~PAGE_MASK); | |
234 | } else { | |
235 | sg_buf = buf; | |
236 | } | |
237 | ||
238 | sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min); | |
239 | ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | |
28cad125 | 240 | (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
010b4818 MV |
241 | |
242 | len -= min; | |
243 | buf += min; | |
244 | ||
245 | /* Queue the PIO register write transfer. */ | |
246 | desc = dmaengine_prep_slave_sg(ssp->dmach, | |
247 | (struct scatterlist *)dma_xfer[sg_count].pio, | |
248 | (ssp->devid == IMX23_SSP) ? 1 : 4, | |
249 | DMA_TRANS_NONE, | |
250 | sg_count ? DMA_PREP_INTERRUPT : 0); | |
251 | if (!desc) { | |
252 | dev_err(ssp->dev, | |
253 | "Failed to get PIO reg. write descriptor.\n"); | |
254 | ret = -EINVAL; | |
255 | goto err_mapped; | |
256 | } | |
257 | ||
258 | desc = dmaengine_prep_slave_sg(ssp->dmach, | |
259 | &dma_xfer[sg_count].sg, 1, | |
28cad125 | 260 | (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, |
010b4818 MV |
261 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
262 | ||
263 | if (!desc) { | |
264 | dev_err(ssp->dev, | |
265 | "Failed to get DMA data write descriptor.\n"); | |
266 | ret = -EINVAL; | |
267 | goto err_mapped; | |
268 | } | |
474afc04 MV |
269 | } |
270 | ||
271 | /* | |
272 | * The last descriptor must have this callback, | |
273 | * to finish the DMA transaction. | |
274 | */ | |
275 | desc->callback = mxs_ssp_dma_irq_callback; | |
276 | desc->callback_param = spi; | |
277 | ||
278 | /* Start the transfer. */ | |
279 | dmaengine_submit(desc); | |
280 | dma_async_issue_pending(ssp->dmach); | |
281 | ||
282 | ret = wait_for_completion_timeout(&spi->c, | |
283 | msecs_to_jiffies(SSP_TIMEOUT)); | |
474afc04 MV |
284 | if (!ret) { |
285 | dev_err(ssp->dev, "DMA transfer timeout\n"); | |
286 | ret = -ETIMEDOUT; | |
44968466 | 287 | dmaengine_terminate_all(ssp->dmach); |
010b4818 | 288 | goto err_vmalloc; |
474afc04 MV |
289 | } |
290 | ||
291 | ret = 0; | |
292 | ||
010b4818 MV |
293 | err_vmalloc: |
294 | while (--sg_count >= 0) { | |
295 | err_mapped: | |
296 | dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | |
28cad125 | 297 | (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
474afc04 MV |
298 | } |
299 | ||
010b4818 MV |
300 | kfree(dma_xfer); |
301 | ||
474afc04 MV |
302 | return ret; |
303 | } | |
304 | ||
0b782f70 | 305 | static int mxs_spi_txrx_pio(struct mxs_spi *spi, |
646781d3 | 306 | unsigned char *buf, int len, |
28cad125 | 307 | unsigned int flags) |
646781d3 MV |
308 | { |
309 | struct mxs_ssp *ssp = &spi->ssp; | |
310 | ||
75e73fa2 TP |
311 | writel(BM_SSP_CTRL0_IGNORE_CRC, |
312 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
646781d3 | 313 | |
646781d3 | 314 | while (len--) { |
28cad125 | 315 | if (len == 0 && (flags & TXRX_DEASSERT_CS)) |
f5bc7384 TP |
316 | writel(BM_SSP_CTRL0_IGNORE_CRC, |
317 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
646781d3 MV |
318 | |
319 | if (ssp->devid == IMX23_SSP) { | |
320 | writel(BM_SSP_CTRL0_XFER_COUNT, | |
321 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
322 | writel(1, | |
323 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
324 | } else { | |
325 | writel(1, ssp->base + HW_SSP_XFER_SIZE); | |
326 | } | |
327 | ||
28cad125 | 328 | if (flags & TXRX_WRITE) |
646781d3 MV |
329 | writel(BM_SSP_CTRL0_READ, |
330 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
331 | else | |
332 | writel(BM_SSP_CTRL0_READ, | |
333 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
334 | ||
335 | writel(BM_SSP_CTRL0_RUN, | |
336 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
337 | ||
338 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) | |
339 | return -ETIMEDOUT; | |
340 | ||
28cad125 | 341 | if (flags & TXRX_WRITE) |
646781d3 MV |
342 | writel(*buf, ssp->base + HW_SSP_DATA(ssp)); |
343 | ||
344 | writel(BM_SSP_CTRL0_DATA_XFER, | |
345 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
346 | ||
28cad125 | 347 | if (!(flags & TXRX_WRITE)) { |
646781d3 MV |
348 | if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), |
349 | BM_SSP_STATUS_FIFO_EMPTY, 0)) | |
350 | return -ETIMEDOUT; | |
351 | ||
352 | *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); | |
353 | } | |
354 | ||
355 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) | |
356 | return -ETIMEDOUT; | |
357 | ||
358 | buf++; | |
359 | } | |
360 | ||
361 | if (len <= 0) | |
362 | return 0; | |
363 | ||
364 | return -ETIMEDOUT; | |
365 | } | |
366 | ||
367 | static int mxs_spi_transfer_one(struct spi_master *master, | |
368 | struct spi_message *m) | |
369 | { | |
370 | struct mxs_spi *spi = spi_master_get_devdata(master); | |
371 | struct mxs_ssp *ssp = &spi->ssp; | |
646781d3 | 372 | struct spi_transfer *t, *tmp_t; |
28cad125 | 373 | unsigned int flag; |
646781d3 | 374 | int status = 0; |
646781d3 | 375 | |
0b782f70 TP |
376 | /* Program CS register bits here, it will be used for all transfers. */ |
377 | writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ, | |
378 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
379 | writel(mxs_spi_cs_to_reg(m->spi->chip_select), | |
380 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
646781d3 MV |
381 | |
382 | list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { | |
383 | ||
384 | status = mxs_spi_setup_transfer(m->spi, t); | |
385 | if (status) | |
386 | break; | |
387 | ||
28cad125 TP |
388 | /* De-assert on last transfer, inverted by cs_change flag */ |
389 | flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ? | |
390 | TXRX_DEASSERT_CS : 0; | |
646781d3 | 391 | |
474afc04 MV |
392 | /* |
393 | * Small blocks can be transfered via PIO. | |
394 | * Measured by empiric means: | |
395 | * | |
396 | * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1 | |
397 | * | |
398 | * DMA only: 2.164808 seconds, 473.0KB/s | |
399 | * Combined: 1.676276 seconds, 610.9KB/s | |
400 | */ | |
727c10e3 | 401 | if (t->len < 32) { |
474afc04 MV |
402 | writel(BM_SSP_CTRL1_DMA_ENABLE, |
403 | ssp->base + HW_SSP_CTRL1(ssp) + | |
404 | STMP_OFFSET_REG_CLR); | |
405 | ||
406 | if (t->tx_buf) | |
0b782f70 | 407 | status = mxs_spi_txrx_pio(spi, |
474afc04 | 408 | (void *)t->tx_buf, |
28cad125 | 409 | t->len, flag | TXRX_WRITE); |
474afc04 | 410 | if (t->rx_buf) |
0b782f70 | 411 | status = mxs_spi_txrx_pio(spi, |
474afc04 | 412 | t->rx_buf, t->len, |
28cad125 | 413 | flag); |
474afc04 MV |
414 | } else { |
415 | writel(BM_SSP_CTRL1_DMA_ENABLE, | |
416 | ssp->base + HW_SSP_CTRL1(ssp) + | |
417 | STMP_OFFSET_REG_SET); | |
418 | ||
419 | if (t->tx_buf) | |
0b782f70 | 420 | status = mxs_spi_txrx_dma(spi, |
474afc04 | 421 | (void *)t->tx_buf, t->len, |
28cad125 | 422 | flag | TXRX_WRITE); |
474afc04 | 423 | if (t->rx_buf) |
0b782f70 | 424 | status = mxs_spi_txrx_dma(spi, |
474afc04 | 425 | t->rx_buf, t->len, |
28cad125 | 426 | flag); |
474afc04 | 427 | } |
646781d3 | 428 | |
c895db0f MV |
429 | if (status) { |
430 | stmp_reset_block(ssp->base); | |
646781d3 | 431 | break; |
c895db0f | 432 | } |
646781d3 | 433 | |
204e706f | 434 | m->actual_length += t->len; |
646781d3 MV |
435 | } |
436 | ||
d856f1eb | 437 | m->status = status; |
646781d3 MV |
438 | spi_finalize_current_message(master); |
439 | ||
440 | return status; | |
441 | } | |
442 | ||
443 | static const struct of_device_id mxs_spi_dt_ids[] = { | |
444 | { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, | |
445 | { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, | |
446 | { /* sentinel */ } | |
447 | }; | |
448 | MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); | |
449 | ||
fd4a319b | 450 | static int mxs_spi_probe(struct platform_device *pdev) |
646781d3 MV |
451 | { |
452 | const struct of_device_id *of_id = | |
453 | of_match_device(mxs_spi_dt_ids, &pdev->dev); | |
454 | struct device_node *np = pdev->dev.of_node; | |
455 | struct spi_master *master; | |
456 | struct mxs_spi *spi; | |
457 | struct mxs_ssp *ssp; | |
26aafa77 | 458 | struct resource *iores; |
646781d3 MV |
459 | struct clk *clk; |
460 | void __iomem *base; | |
26aafa77 SG |
461 | int devid, clk_freq; |
462 | int ret = 0, irq_err; | |
646781d3 | 463 | |
e64d07a2 MV |
464 | /* |
465 | * Default clock speed for the SPI core. 160MHz seems to | |
466 | * work reasonably well with most SPI flashes, so use this | |
467 | * as a default. Override with "clock-frequency" DT prop. | |
468 | */ | |
469 | const int clk_freq_default = 160000000; | |
470 | ||
646781d3 | 471 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
474afc04 | 472 | irq_err = platform_get_irq(pdev, 0); |
796305a2 | 473 | if (irq_err < 0) |
646781d3 MV |
474 | return -EINVAL; |
475 | ||
b0ee5605 TR |
476 | base = devm_ioremap_resource(&pdev->dev, iores); |
477 | if (IS_ERR(base)) | |
478 | return PTR_ERR(base); | |
646781d3 | 479 | |
646781d3 MV |
480 | clk = devm_clk_get(&pdev->dev, NULL); |
481 | if (IS_ERR(clk)) | |
482 | return PTR_ERR(clk); | |
483 | ||
26aafa77 SG |
484 | devid = (enum mxs_ssp_id) of_id->data; |
485 | ret = of_property_read_u32(np, "clock-frequency", | |
486 | &clk_freq); | |
487 | if (ret) | |
e64d07a2 | 488 | clk_freq = clk_freq_default; |
646781d3 MV |
489 | |
490 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); | |
491 | if (!master) | |
492 | return -ENOMEM; | |
493 | ||
494 | master->transfer_one_message = mxs_spi_transfer_one; | |
495 | master->setup = mxs_spi_setup; | |
24778be2 | 496 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
646781d3 MV |
497 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
498 | master->num_chipselect = 3; | |
499 | master->dev.of_node = np; | |
500 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
501 | ||
502 | spi = spi_master_get_devdata(master); | |
503 | ssp = &spi->ssp; | |
504 | ssp->dev = &pdev->dev; | |
505 | ssp->clk = clk; | |
506 | ssp->base = base; | |
507 | ssp->devid = devid; | |
474afc04 | 508 | |
41682e03 MV |
509 | init_completion(&spi->c); |
510 | ||
474afc04 MV |
511 | ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, |
512 | DRIVER_NAME, ssp); | |
513 | if (ret) | |
514 | goto out_master_free; | |
515 | ||
26aafa77 | 516 | ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx"); |
474afc04 MV |
517 | if (!ssp->dmach) { |
518 | dev_err(ssp->dev, "Failed to request DMA\n"); | |
58ad60bb | 519 | ret = -ENODEV; |
474afc04 MV |
520 | goto out_master_free; |
521 | } | |
646781d3 | 522 | |
9c4a39af FE |
523 | ret = clk_prepare_enable(ssp->clk); |
524 | if (ret) | |
525 | goto out_dma_release; | |
526 | ||
e64d07a2 | 527 | clk_set_rate(ssp->clk, clk_freq); |
646781d3 | 528 | |
8498bce9 FE |
529 | ret = stmp_reset_block(ssp->base); |
530 | if (ret) | |
531 | goto out_disable_clk; | |
646781d3 MV |
532 | |
533 | platform_set_drvdata(pdev, master); | |
534 | ||
535 | ret = spi_register_master(master); | |
536 | if (ret) { | |
537 | dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); | |
9c4a39af | 538 | goto out_disable_clk; |
646781d3 MV |
539 | } |
540 | ||
541 | return 0; | |
542 | ||
9c4a39af | 543 | out_disable_clk: |
646781d3 | 544 | clk_disable_unprepare(ssp->clk); |
9c4a39af | 545 | out_dma_release: |
e11933f6 | 546 | dma_release_channel(ssp->dmach); |
474afc04 | 547 | out_master_free: |
646781d3 MV |
548 | spi_master_put(master); |
549 | return ret; | |
550 | } | |
551 | ||
fd4a319b | 552 | static int mxs_spi_remove(struct platform_device *pdev) |
646781d3 MV |
553 | { |
554 | struct spi_master *master; | |
555 | struct mxs_spi *spi; | |
556 | struct mxs_ssp *ssp; | |
557 | ||
7d520d28 | 558 | master = spi_master_get(platform_get_drvdata(pdev)); |
646781d3 MV |
559 | spi = spi_master_get_devdata(master); |
560 | ssp = &spi->ssp; | |
561 | ||
562 | spi_unregister_master(master); | |
646781d3 | 563 | clk_disable_unprepare(ssp->clk); |
e11933f6 | 564 | dma_release_channel(ssp->dmach); |
646781d3 MV |
565 | spi_master_put(master); |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static struct platform_driver mxs_spi_driver = { | |
571 | .probe = mxs_spi_probe, | |
fd4a319b | 572 | .remove = mxs_spi_remove, |
646781d3 MV |
573 | .driver = { |
574 | .name = DRIVER_NAME, | |
575 | .owner = THIS_MODULE, | |
576 | .of_match_table = mxs_spi_dt_ids, | |
577 | }, | |
578 | }; | |
579 | ||
580 | module_platform_driver(mxs_spi_driver); | |
581 | ||
582 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
583 | MODULE_DESCRIPTION("MXS SPI master driver"); | |
584 | MODULE_LICENSE("GPL"); | |
585 | MODULE_ALIAS("platform:mxs-spi"); |