[deliverable/linux.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t hz = 0;

	hz = dev->max_speed_hz;
	if (t && t->speed_hz)
		hz = min(hz, t->speed_hz);
	if (hz == 0) {
		dev_err(&dev->dev, "Cannot continue with zero clock\n");
		return -EINVAL;
	}

	mxs_ssp_set_clk_rate(ssp, hz);

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
		     BF_SSP_CTRL1_WORD_LENGTH
		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
		     ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static int mxs_spi_setup(struct spi_device *dev)
{
	int err = 0;

	if (!dev->bits_per_word)
		dev->bits_per_word = 8;

	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
		return -EINVAL;

	err = mxs_spi_setup_transfer(dev, NULL);
	if (err) {
		dev_err(&dev->dev,
			"Failed to setup transfer, error = %d\n", err);
	}

	return err;
}

static uint32_t mxs_spi_cs_to_reg(unsigned cs)
{
	uint32_t select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
{
	const uint32_t mask =
		BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
	uint32_t select;
	struct mxs_ssp *ssp = &spi->ssp;

	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	select = mxs_spi_cs_to_reg(cs);
	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;
	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;
	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	uint32_t ctrl0;
	struct page *vm_page;
	void *sg_buf;
	struct {
		uint32_t		pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	INIT_COMPLETION(spi->c);

	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);

	if (!write)
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		min = min(len, desc_len);

		/* Prepare the transfer descriptor. */
		if ((sg_count + 1 == sgs) && *last)
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}
			sg_buf = page_address(vm_page) +
				((size_t)buf & ~PAGE_MASK);
		} else {
			sg_buf = buf;
		}

		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	ret = wait_for_completion_timeout(&spi->c,
				msecs_to_jiffies(SSP_TIMEOUT));
	if (!ret) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;

	if (*first)
		writel(BM_SSP_CTRL0_IGNORE_CRC,
		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	mxs_spi_set_cs(spi, cs);

	while (len--) {
		if (*last && len == 0)
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (write)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (write)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!write) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int first, last;
	struct spi_transfer *t, *tmp_t;
	int status = 0;
	int cs;

	first = last = 0;

	cs = m->spi->chip_select;

	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		if (&t->transfer_list == m->transfers.next)
			first = 1;
		if (&t->transfer_list == m->transfers.prev)
			last = 1;
		if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
			dev_err(ssp->dev,
				"Cannot send and receive simultaneously\n");
			status = -EINVAL;
			break;
		}

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						(void *)t->tx_buf,
						t->len, &first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						(void *)t->tx_buf, t->len,
						&first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
		first = last = 0;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return -EINVAL;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->setup = mxs_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       DRIVER_NAME, ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		goto out_dma_release;

	clk_set_rate(ssp->clk, clk_freq);
	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_disable_clk;

	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_disable_clk;
	}

	return 0;

out_disable_clk:
	clk_disable_unprepare(ssp->clk);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = spi_master_get(platform_get_drvdata(pdev));
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	spi_unregister_master(master);
	clk_disable_unprepare(ssp->clk);
	dma_release_channel(ssp->dmach);
	spi_master_put(master);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/of.h>
	35	#include <linux/of_device.h>
	36	#include <linux/of_gpio.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/dmaengine.h>
	42	#include <linux/highmem.h>
	43	#include <linux/clk.h>
	44	#include <linux/err.h>
	45	#include <linux/completion.h>
	46	#include <linux/gpio.h>
	47	#include <linux/regulator/consumer.h>
	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
646781d3 MV	60	struct mxs_spi {
646781d3 MV	61	struct mxs_ssp ssp;
474afc04	62	struct completion c;
646781d3 MV	63	};
	64
	65	static int mxs_spi_setup_transfer(struct spi_device *dev,
	66	struct spi_transfer *t)
	67	{
	68	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	69	struct mxs_ssp *ssp = &spi->ssp;
646781d3 MV	70	uint32_t hz = 0;
646781d3 MV	71
646781d3 MV	72	hz = dev->max_speed_hz;
	73	if (t && t->speed_hz)
	74	hz = min(hz, t->speed_hz);
	75	if (hz == 0) {
	76	dev_err(&dev->dev, "Cannot continue with zero clock\n");
	77	return -EINVAL;
	78	}
	79
	80	mxs_ssp_set_clk_rate(ssp, hz);
	81
58f46e41 TP	82	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	83	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	84	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
	85	BF_SSP_CTRL1_WORD_LENGTH
	86	(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	87	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	88	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	89	ssp->base + HW_SSP_CTRL1(ssp));
	90
	91	writel(0x0, ssp->base + HW_SSP_CMD0);
	92	writel(0x0, ssp->base + HW_SSP_CMD1);
	93
	94	return 0;
	95	}
	96
	97	static int mxs_spi_setup(struct spi_device *dev)
	98	{
	99	int err = 0;
	100
	101	if (!dev->bits_per_word)
	102	dev->bits_per_word = 8;
	103
	104	if (dev->mode & ~(SPI_CPOL \| SPI_CPHA))
	105	return -EINVAL;
	106
	107	err = mxs_spi_setup_transfer(dev, NULL);
	108	if (err) {
	109	dev_err(&dev->dev,
	110	"Failed to setup transfer, error = %d\n", err);
	111	}
	112
	113	return err;
	114	}
	115
	116	static uint32_t mxs_spi_cs_to_reg(unsigned cs)
	117	{
	118	uint32_t select = 0;
	119
	120	/*
	121	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	122	*
	123	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	124	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	125	* the datasheet for further details. In SPI mode, they are used to
	126	* toggle the chip-select lines (nCS pins).
	127	*/
	128	if (cs & 1)
	129	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	130	if (cs & 2)
	131	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	132
	133	return select;
	134	}
	135
	136	static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
	137	{
	138	const uint32_t mask =
	139	BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ;
	140	uint32_t select;
	141	struct mxs_ssp *ssp = &spi->ssp;
	142
	143	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	144	select = mxs_spi_cs_to_reg(cs);
	145	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	146	}
	147
646781d3 MV	148	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	149	{
f13639dc	150	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3 MV	151	struct mxs_ssp *ssp = &spi->ssp;
	152	uint32_t reg;
	153
f13639dc	154	do {
646781d3 MV	155	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	156
f13639dc MV	157	if (!set)
f13639dc MV	158	reg = ~reg;
646781d3	159
f13639dc	160	reg &= mask;
646781d3	161
f13639dc MV	162	if (reg == mask)
	163	return 0;
	164	} while (time_before(jiffies, timeout));
646781d3	165
f13639dc	166	return -ETIMEDOUT;
646781d3 MV	167	}
646781d3 MV	168
474afc04 MV	169	static void mxs_ssp_dma_irq_callback(void *param)
	170	{
	171	struct mxs_spi *spi = param;
	172	complete(&spi->c);
	173	}
	174
	175	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	176	{
	177	struct mxs_ssp *ssp = dev_id;
	178	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	179	__func__, __LINE__,
	180	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	181	readl(ssp->base + HW_SSP_STATUS(ssp)));
	182	return IRQ_HANDLED;
	183	}
	184
	185	static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
	186	unsigned char *buf, int len,
	187	int first, int last, int write)
	188	{
	189	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	190	struct dma_async_tx_descriptor *desc = NULL;
	191	const bool vmalloced_buf = is_vmalloc_addr(buf);
	192	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	193	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	194	int sg_count;
010b4818 MV	195	int min, ret;
	196	uint32_t ctrl0;
	197	struct page *vm_page;
	198	void *sg_buf;
	199	struct {
	200	uint32_t pio[4];
	201	struct scatterlist sg;
	202	} *dma_xfer;
	203
	204	if (!len)
474afc04	205	return -EINVAL;
010b4818 MV	206
	207	dma_xfer = kzalloc(sizeof(dma_xfer) sgs, GFP_KERNEL);
	208	if (!dma_xfer)
	209	return -ENOMEM;
474afc04	210
41682e03	211	INIT_COMPLETION(spi->c);
474afc04	212
010b4818	213	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
ba486a2a	214	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818 MV	215	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER \| mxs_spi_cs_to_reg(cs);
010b4818 MV	216
474afc04	217	if (!write)
010b4818	218	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	219
474afc04 MV	220	/* Queue the DMA data transfer. */
010b4818 MV	221	for (sg_count = 0; sg_count < sgs; sg_count++) {
	222	min = min(len, desc_len);
	223
	224	/* Prepare the transfer descriptor. */
	225	if ((sg_count + 1 == sgs) && *last)
	226	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
	227
ba486a2a JL	228	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	229	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	230	ctrl0 \|= min;
ba486a2a	231	}
010b4818 MV	232
	233	dma_xfer[sg_count].pio[0] = ctrl0;
	234	dma_xfer[sg_count].pio[3] = min;
	235
	236	if (vmalloced_buf) {
	237	vm_page = vmalloc_to_page(buf);
	238	if (!vm_page) {
	239	ret = -ENOMEM;
	240	goto err_vmalloc;
	241	}
	242	sg_buf = page_address(vm_page) +
	243	((size_t)buf & ~PAGE_MASK);
	244	} else {
	245	sg_buf = buf;
	246	}
	247
	248	sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
	249	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
	250	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	251
	252	len -= min;
	253	buf += min;
	254
	255	/* Queue the PIO register write transfer. */
	256	desc = dmaengine_prep_slave_sg(ssp->dmach,
	257	(struct scatterlist *)dma_xfer[sg_count].pio,
	258	(ssp->devid == IMX23_SSP) ? 1 : 4,
	259	DMA_TRANS_NONE,
	260	sg_count ? DMA_PREP_INTERRUPT : 0);
	261	if (!desc) {
	262	dev_err(ssp->dev,
	263	"Failed to get PIO reg. write descriptor.\n");
	264	ret = -EINVAL;
	265	goto err_mapped;
	266	}
	267
	268	desc = dmaengine_prep_slave_sg(ssp->dmach,
	269	&dma_xfer[sg_count].sg, 1,
	270	write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
	271	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	272
	273	if (!desc) {
	274	dev_err(ssp->dev,
	275	"Failed to get DMA data write descriptor.\n");
	276	ret = -EINVAL;
	277	goto err_mapped;
	278	}
474afc04 MV	279	}
	280
	281	/*
	282	* The last descriptor must have this callback,
	283	* to finish the DMA transaction.
	284	*/
	285	desc->callback = mxs_ssp_dma_irq_callback;
	286	desc->callback_param = spi;
	287
	288	/* Start the transfer. */
	289	dmaengine_submit(desc);
	290	dma_async_issue_pending(ssp->dmach);
	291
	292	ret = wait_for_completion_timeout(&spi->c,
	293	msecs_to_jiffies(SSP_TIMEOUT));
474afc04 MV	294	if (!ret) {
	295	dev_err(ssp->dev, "DMA transfer timeout\n");
	296	ret = -ETIMEDOUT;
44968466	297	dmaengine_terminate_all(ssp->dmach);
010b4818	298	goto err_vmalloc;
474afc04 MV	299	}
	300
	301	ret = 0;
	302
010b4818 MV	303	err_vmalloc:
	304	while (--sg_count >= 0) {
	305	err_mapped:
	306	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
474afc04 MV	307	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	308	}
	309
010b4818 MV	310	kfree(dma_xfer);
010b4818 MV	311
474afc04 MV	312	return ret;
	313	}
	314
646781d3 MV	315	static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
	316	unsigned char *buf, int len,
	317	int first, int last, int write)
	318	{
	319	struct mxs_ssp *ssp = &spi->ssp;
	320
	321	if (*first)
f5bc7384 TP	322	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	323	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	324
	325	mxs_spi_set_cs(spi, cs);
	326
	327	while (len--) {
	328	if (*last && len == 0)
f5bc7384 TP	329	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	330	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	331
	332	if (ssp->devid == IMX23_SSP) {
	333	writel(BM_SSP_CTRL0_XFER_COUNT,
	334	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	335	writel(1,
	336	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	337	} else {
	338	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	339	}
	340
	341	if (write)
	342	writel(BM_SSP_CTRL0_READ,
	343	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	344	else
	345	writel(BM_SSP_CTRL0_READ,
	346	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	347
	348	writel(BM_SSP_CTRL0_RUN,
	349	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	350
	351	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	352	return -ETIMEDOUT;
	353
	354	if (write)
	355	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	356
	357	writel(BM_SSP_CTRL0_DATA_XFER,
	358	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	359
	360	if (!write) {
	361	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	362	BM_SSP_STATUS_FIFO_EMPTY, 0))
	363	return -ETIMEDOUT;
	364
	365	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	366	}
	367
	368	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	369	return -ETIMEDOUT;
	370
	371	buf++;
	372	}
	373
	374	if (len <= 0)
	375	return 0;
	376
	377	return -ETIMEDOUT;
	378	}
	379
	380	static int mxs_spi_transfer_one(struct spi_master *master,
	381	struct spi_message *m)
	382	{
	383	struct mxs_spi *spi = spi_master_get_devdata(master);
	384	struct mxs_ssp *ssp = &spi->ssp;
	385	int first, last;
	386	struct spi_transfer t, tmp_t;
	387	int status = 0;
	388	int cs;
	389
	390	first = last = 0;
	391
	392	cs = m->spi->chip_select;
	393
	394	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
395
396	status = mxs_spi_setup_transfer(m->spi, t);
397	if (status)
398	break;
399
400	if (&t->transfer_list == m->transfers.next)
401	first = 1;
402	if (&t->transfer_list == m->transfers.prev)
403	last = 1;
474afc04	404	if ((t->rx_buf && t->tx_buf) \|\| (t->rx_dma && t->tx_dma)) {
646781d3 MV	405	dev_err(ssp->dev,
	406	"Cannot send and receive simultaneously\n");
	407	status = -EINVAL;
	408	break;
	409	}
	410
474afc04 MV	411	/*
	412	* Small blocks can be transfered via PIO.
	413	* Measured by empiric means:
	414	*
	415	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	416	*
	417	* DMA only: 2.164808 seconds, 473.0KB/s
	418	* Combined: 1.676276 seconds, 610.9KB/s
	419	*/
727c10e3	420	if (t->len < 32) {
474afc04 MV	421	writel(BM_SSP_CTRL1_DMA_ENABLE,
	422	ssp->base + HW_SSP_CTRL1(ssp) +
	423	STMP_OFFSET_REG_CLR);
	424
	425	if (t->tx_buf)
	426	status = mxs_spi_txrx_pio(spi, cs,
	427	(void *)t->tx_buf,
	428	t->len, &first, &last, 1);
	429	if (t->rx_buf)
	430	status = mxs_spi_txrx_pio(spi, cs,
	431	t->rx_buf, t->len,
	432	&first, &last, 0);
	433	} else {
	434	writel(BM_SSP_CTRL1_DMA_ENABLE,
	435	ssp->base + HW_SSP_CTRL1(ssp) +
	436	STMP_OFFSET_REG_SET);
	437
	438	if (t->tx_buf)
	439	status = mxs_spi_txrx_dma(spi, cs,
	440	(void *)t->tx_buf, t->len,
	441	&first, &last, 1);
	442	if (t->rx_buf)
	443	status = mxs_spi_txrx_dma(spi, cs,
	444	t->rx_buf, t->len,
	445	&first, &last, 0);
	446	}
646781d3	447
c895db0f MV	448	if (status) {
c895db0f MV	449	stmp_reset_block(ssp->base);
646781d3	450	break;
c895db0f	451	}
646781d3	452
204e706f	453	m->actual_length += t->len;
646781d3 MV	454	first = last = 0;
	455	}
	456
d856f1eb	457	m->status = status;
646781d3 MV	458	spi_finalize_current_message(master);
	459
	460	return status;
	461	}
	462
	463	static const struct of_device_id mxs_spi_dt_ids[] = {
	464	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	465	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	466	{ /* sentinel */ }
	467	};
	468	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	469
fd4a319b	470	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	471	{
	472	const struct of_device_id *of_id =
	473	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	474	struct device_node *np = pdev->dev.of_node;
	475	struct spi_master *master;
	476	struct mxs_spi *spi;
	477	struct mxs_ssp *ssp;
26aafa77	478	struct resource *iores;
646781d3 MV	479	struct clk *clk;
646781d3 MV	480	void __iomem *base;
26aafa77 SG	481	int devid, clk_freq;
26aafa77 SG	482	int ret = 0, irq_err;
646781d3	483
e64d07a2 MV	484	/*
	485	* Default clock speed for the SPI core. 160MHz seems to
	486	* work reasonably well with most SPI flashes, so use this
	487	* as a default. Override with "clock-frequency" DT prop.
	488	*/
	489	const int clk_freq_default = 160000000;
	490
646781d3	491	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	492	irq_err = platform_get_irq(pdev, 0);
796305a2	493	if (irq_err < 0)
646781d3 MV	494	return -EINVAL;
646781d3 MV	495
b0ee5605 TR	496	base = devm_ioremap_resource(&pdev->dev, iores);
	497	if (IS_ERR(base))
	498	return PTR_ERR(base);
646781d3	499
646781d3 MV	500	clk = devm_clk_get(&pdev->dev, NULL);
	501	if (IS_ERR(clk))
	502	return PTR_ERR(clk);
	503
26aafa77 SG	504	devid = (enum mxs_ssp_id) of_id->data;
	505	ret = of_property_read_u32(np, "clock-frequency",
	506	&clk_freq);
	507	if (ret)
e64d07a2	508	clk_freq = clk_freq_default;
646781d3 MV	509
	510	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	511	if (!master)
	512	return -ENOMEM;
	513
	514	master->transfer_one_message = mxs_spi_transfer_one;
	515	master->setup = mxs_spi_setup;
24778be2	516	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	517	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	518	master->num_chipselect = 3;
	519	master->dev.of_node = np;
	520	master->flags = SPI_MASTER_HALF_DUPLEX;
	521
	522	spi = spi_master_get_devdata(master);
	523	ssp = &spi->ssp;
	524	ssp->dev = &pdev->dev;
	525	ssp->clk = clk;
	526	ssp->base = base;
	527	ssp->devid = devid;
474afc04	528
41682e03 MV	529	init_completion(&spi->c);
41682e03 MV	530
474afc04 MV	531	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
	532	DRIVER_NAME, ssp);
	533	if (ret)
	534	goto out_master_free;
	535
26aafa77	536	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	537	if (!ssp->dmach) {
474afc04 MV	538	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	539	ret = -ENODEV;
474afc04 MV	540	goto out_master_free;
474afc04 MV	541	}
646781d3	542
9c4a39af FE	543	ret = clk_prepare_enable(ssp->clk);
	544	if (ret)
	545	goto out_dma_release;
	546
e64d07a2	547	clk_set_rate(ssp->clk, clk_freq);
646781d3 MV	548	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
646781d3 MV	549
8498bce9 FE	550	ret = stmp_reset_block(ssp->base);
	551	if (ret)
	552	goto out_disable_clk;
646781d3 MV	553
	554	platform_set_drvdata(pdev, master);
	555
	556	ret = spi_register_master(master);
	557	if (ret) {
	558	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
9c4a39af	559	goto out_disable_clk;
646781d3 MV	560	}
	561
	562	return 0;
	563
9c4a39af	564	out_disable_clk:
646781d3	565	clk_disable_unprepare(ssp->clk);
9c4a39af	566	out_dma_release:
e11933f6	567	dma_release_channel(ssp->dmach);
474afc04	568	out_master_free:
646781d3 MV	569	spi_master_put(master);
	570	return ret;
	571	}
	572
fd4a319b	573	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	574	{
	575	struct spi_master *master;
	576	struct mxs_spi *spi;
	577	struct mxs_ssp *ssp;
	578
7d520d28	579	master = spi_master_get(platform_get_drvdata(pdev));
646781d3 MV	580	spi = spi_master_get_devdata(master);
	581	ssp = &spi->ssp;
	582
	583	spi_unregister_master(master);
646781d3	584	clk_disable_unprepare(ssp->clk);
e11933f6	585	dma_release_channel(ssp->dmach);
646781d3 MV	586	spi_master_put(master);
	587
	588	return 0;
	589	}
	590
	591	static struct platform_driver mxs_spi_driver = {
	592	.probe = mxs_spi_probe,
fd4a319b	593	.remove = mxs_spi_remove,
646781d3 MV	594	.driver = {
	595	.name = DRIVER_NAME,
	596	.owner = THIS_MODULE,
	597	.of_match_table = mxs_spi_dt_ids,
	598	},
	599	};
	600
	601	module_platform_driver(mxs_spi_driver);
	602
	603	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	604	MODULE_DESCRIPTION("MXS SPI master driver");
	605	MODULE_LICENSE("GPL");
	606	MODULE_ALIAS("platform:mxs-spi");