[deliverable/linux.git] / drivers / spi / spi-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2011, 2012 Cavium, Inc.
 */

#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-mpi-defs.h>

#define OCTEON_SPI_MAX_BYTES 9

#define OCTEON_SPI_MAX_CLOCK_HZ 16000000

struct octeon_spi_regs {
	int config;
	int status;
	int tx;
	int data;
};

struct octeon_spi {
	void __iomem *register_base;
	u64 last_cfg;
	u64 cs_enax;
	int sys_freq;
	struct octeon_spi_regs regs;
};

#define OCTEON_SPI_CFG(x)	(x->regs.config)
#define OCTEON_SPI_STS(x)	(x->regs.status)
#define OCTEON_SPI_TX(x)	(x->regs.tx)
#define OCTEON_SPI_DAT0(x)	(x->regs.data)

static void octeon_spi_wait_ready(struct octeon_spi *p)
{
	union cvmx_mpi_sts mpi_sts;
	unsigned int loops = 0;

	do {
		if (loops++)
			__delay(500);
		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
	} while (mpi_sts.s.busy);
}

static int octeon_spi_do_transfer(struct octeon_spi *p,
				  struct spi_message *msg,
				  struct spi_transfer *xfer,
				  bool last_xfer)
{
	struct spi_device *spi = msg->spi;
	union cvmx_mpi_cfg mpi_cfg;
	union cvmx_mpi_tx mpi_tx;
	unsigned int clkdiv;
	int mode;
	bool cpha, cpol;
	const u8 *tx_buf;
	u8 *rx_buf;
	int len;
	int i;

	mode = spi->mode;
	cpha = mode & SPI_CPHA;
	cpol = mode & SPI_CPOL;

	clkdiv = p->sys_freq / (2 * xfer->speed_hz);

	mpi_cfg.u64 = 0;

	mpi_cfg.s.clkdiv = clkdiv;
	mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
	mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
	mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
	mpi_cfg.s.idlelo = cpha != cpol;
	mpi_cfg.s.cslate = cpha ? 1 : 0;
	mpi_cfg.s.enable = 1;

	if (spi->chip_select < 4)
		p->cs_enax |= 1ull << (12 + spi->chip_select);
	mpi_cfg.u64 |= p->cs_enax;

	if (mpi_cfg.u64 != p->last_cfg) {
		p->last_cfg = mpi_cfg.u64;
		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
	}
	tx_buf = xfer->tx_buf;
	rx_buf = xfer->rx_buf;
	len = xfer->len;
	while (len > OCTEON_SPI_MAX_BYTES) {
		for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
			u8 d;
			if (tx_buf)
				d = *tx_buf++;
			else
				d = 0;
			writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
		}
		mpi_tx.u64 = 0;
		mpi_tx.s.csid = spi->chip_select;
		mpi_tx.s.leavecs = 1;
		mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
		mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

		octeon_spi_wait_ready(p);
		if (rx_buf)
			for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
				u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
				*rx_buf++ = (u8)v;
			}
		len -= OCTEON_SPI_MAX_BYTES;
	}

	for (i = 0; i < len; i++) {
		u8 d;
		if (tx_buf)
			d = *tx_buf++;
		else
			d = 0;
		writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
	}

	mpi_tx.u64 = 0;
	mpi_tx.s.csid = spi->chip_select;
	if (last_xfer)
		mpi_tx.s.leavecs = xfer->cs_change;
	else
		mpi_tx.s.leavecs = !xfer->cs_change;
	mpi_tx.s.txnum = tx_buf ? len : 0;
	mpi_tx.s.totnum = len;
	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));

	octeon_spi_wait_ready(p);
	if (rx_buf)
		for (i = 0; i < len; i++) {
			u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
			*rx_buf++ = (u8)v;
		}

	if (xfer->delay_usecs)
		udelay(xfer->delay_usecs);

	return xfer->len;
}

static int octeon_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *msg)
{
	struct octeon_spi *p = spi_master_get_devdata(master);
	unsigned int total_len = 0;
	int status = 0;
	struct spi_transfer *xfer;

	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		bool last_xfer = list_is_last(&xfer->transfer_list,
					      &msg->transfers);
		int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
		if (r < 0) {
			status = r;
			goto err;
		}
		total_len += r;
	}
err:
	msg->status = status;
	msg->actual_length = total_len;
	spi_finalize_current_message(master);
	return status;
}

static int octeon_spi_probe(struct platform_device *pdev)
{
	struct resource *res_mem;
	void __iomem *reg_base;
	struct spi_master *master;
	struct octeon_spi *p;
	int err = -ENOENT;

	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
	if (!master)
		return -ENOMEM;
	p = spi_master_get_devdata(master);
	platform_set_drvdata(pdev, master);

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
	if (IS_ERR(reg_base)) {
		err = PTR_ERR(reg_base);
		goto fail;
	}

	p->register_base = reg_base;
	p->sys_freq = octeon_get_io_clock_rate();

	p->regs.config = 0;
	p->regs.status = 0x08;
	p->regs.tx = 0x10;
	p->regs.data = 0x80;

	master->num_chipselect = 4;
	master->mode_bits = SPI_CPHA |
			    SPI_CPOL |
			    SPI_CS_HIGH |
			    SPI_LSB_FIRST |
			    SPI_3WIRE;

	master->transfer_one_message = octeon_spi_transfer_one_message;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;

	master->dev.of_node = pdev->dev.of_node;
	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "register master failed: %d\n", err);
		goto fail;
	}

	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");

	return 0;
fail:
	spi_master_put(master);
	return err;
}

static int octeon_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct octeon_spi *p = spi_master_get_devdata(master);

	/* Clear the CSENA* and put everything in a known state. */
	writeq(0, p->register_base + OCTEON_SPI_CFG(p));

	return 0;
}

static const struct of_device_id octeon_spi_match[] = {
	{ .compatible = "cavium,octeon-3010-spi", },
	{},
};
MODULE_DEVICE_TABLE(of, octeon_spi_match);

static struct platform_driver octeon_spi_driver = {
	.driver = {
		.name		= "spi-octeon",
		.of_match_table = octeon_spi_match,
	},
	.probe		= octeon_spi_probe,
	.remove		= octeon_spi_remove,
};

module_platform_driver(octeon_spi_driver);

MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
Commit	Line	Data
6b52c00f DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2011, 2012 Cavium, Inc.
	7	*/
	8
	9	#include <linux/platform_device.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/spi/spi.h>
	12	#include <linux/module.h>
	13	#include <linux/delay.h>
6b52c00f DD	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16
	17	#include <asm/octeon/octeon.h>
	18	#include <asm/octeon/cvmx-mpi-defs.h>
	19
6b52c00f DD	20	#define OCTEON_SPI_MAX_BYTES 9
	21
	22	#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
	23
ee423c53 JG	24	struct octeon_spi_regs {
	25	int config;
	26	int status;
	27	int tx;
	28	int data;
	29	};
	30
6b52c00f	31	struct octeon_spi {
187fc9b3	32	void __iomem *register_base;
6b52c00f DD	33	u64 last_cfg;
6b52c00f DD	34	u64 cs_enax;
b9e64763	35	int sys_freq;
ee423c53	36	struct octeon_spi_regs regs;
6b52c00f DD	37	};
6b52c00f DD	38
ee423c53 JG	39	#define OCTEON_SPI_CFG(x) (x->regs.config)
	40	#define OCTEON_SPI_STS(x) (x->regs.status)
	41	#define OCTEON_SPI_TX(x) (x->regs.tx)
	42	#define OCTEON_SPI_DAT0(x) (x->regs.data)
	43
6b52c00f DD	44	static void octeon_spi_wait_ready(struct octeon_spi *p)
	45	{
	46	union cvmx_mpi_sts mpi_sts;
	47	unsigned int loops = 0;
	48
	49	do {
	50	if (loops++)
	51	__delay(500);
ee423c53	52	mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
6b52c00f DD	53	} while (mpi_sts.s.busy);
	54	}
	55
	56	static int octeon_spi_do_transfer(struct octeon_spi *p,
	57	struct spi_message *msg,
	58	struct spi_transfer *xfer,
	59	bool last_xfer)
	60	{
85fe414d	61	struct spi_device *spi = msg->spi;
6b52c00f DD	62	union cvmx_mpi_cfg mpi_cfg;
	63	union cvmx_mpi_tx mpi_tx;
	64	unsigned int clkdiv;
6b52c00f DD	65	int mode;
6b52c00f DD	66	bool cpha, cpol;
6b52c00f DD	67	const u8 *tx_buf;
	68	u8 *rx_buf;
	69	int len;
	70	int i;
	71
85fe414d	72	mode = spi->mode;
6b52c00f DD	73	cpha = mode & SPI_CPHA;
6b52c00f DD	74	cpol = mode & SPI_CPOL;
6b52c00f	75
b9e64763	76	clkdiv = p->sys_freq / (2 * xfer->speed_hz);
6b52c00f DD	77
	78	mpi_cfg.u64 = 0;
	79
	80	mpi_cfg.s.clkdiv = clkdiv;
	81	mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
	82	mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
	83	mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
	84	mpi_cfg.s.idlelo = cpha != cpol;
	85	mpi_cfg.s.cslate = cpha ? 1 : 0;
	86	mpi_cfg.s.enable = 1;
	87
85fe414d AL	88	if (spi->chip_select < 4)
85fe414d AL	89	p->cs_enax \|= 1ull << (12 + spi->chip_select);
6b52c00f DD	90	mpi_cfg.u64 \|= p->cs_enax;
	91
	92	if (mpi_cfg.u64 != p->last_cfg) {
	93	p->last_cfg = mpi_cfg.u64;
ee423c53	94	writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
6b52c00f DD	95	}
	96	tx_buf = xfer->tx_buf;
	97	rx_buf = xfer->rx_buf;
	98	len = xfer->len;
	99	while (len > OCTEON_SPI_MAX_BYTES) {
	100	for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
	101	u8 d;
	102	if (tx_buf)
	103	d = *tx_buf++;
	104	else
	105	d = 0;
ee423c53	106	writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
6b52c00f DD	107	}
6b52c00f DD	108	mpi_tx.u64 = 0;
85fe414d	109	mpi_tx.s.csid = spi->chip_select;
6b52c00f DD	110	mpi_tx.s.leavecs = 1;
	111	mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
	112	mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
ee423c53	113	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
6b52c00f DD	114
	115	octeon_spi_wait_ready(p);
	116	if (rx_buf)
	117	for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
ee423c53	118	u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
6b52c00f DD	119	*rx_buf++ = (u8)v;
	120	}
	121	len -= OCTEON_SPI_MAX_BYTES;
	122	}
	123
	124	for (i = 0; i < len; i++) {
	125	u8 d;
	126	if (tx_buf)
	127	d = *tx_buf++;
	128	else
	129	d = 0;
ee423c53	130	writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
6b52c00f DD	131	}
	132
	133	mpi_tx.u64 = 0;
85fe414d	134	mpi_tx.s.csid = spi->chip_select;
6b52c00f DD	135	if (last_xfer)
	136	mpi_tx.s.leavecs = xfer->cs_change;
	137	else
	138	mpi_tx.s.leavecs = !xfer->cs_change;
	139	mpi_tx.s.txnum = tx_buf ? len : 0;
	140	mpi_tx.s.totnum = len;
ee423c53	141	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
6b52c00f DD	142
	143	octeon_spi_wait_ready(p);
	144	if (rx_buf)
	145	for (i = 0; i < len; i++) {
ee423c53	146	u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
6b52c00f DD	147	*rx_buf++ = (u8)v;
	148	}
	149
	150	if (xfer->delay_usecs)
	151	udelay(xfer->delay_usecs);
	152
	153	return xfer->len;
	154	}
	155
6b52c00f DD	156	static int octeon_spi_transfer_one_message(struct spi_master *master,
	157	struct spi_message *msg)
	158	{
	159	struct octeon_spi *p = spi_master_get_devdata(master);
	160	unsigned int total_len = 0;
	161	int status = 0;
	162	struct spi_transfer *xfer;
	163
6b52c00f	164	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
0a4e210e AL	165	bool last_xfer = list_is_last(&xfer->transfer_list,
0a4e210e AL	166	&msg->transfers);
6b52c00f DD	167	int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
	168	if (r < 0) {
	169	status = r;
	170	goto err;
	171	}
	172	total_len += r;
	173	}
	174	err:
	175	msg->status = status;
	176	msg->actual_length = total_len;
	177	spi_finalize_current_message(master);
	178	return status;
	179	}
	180
fd4a319b	181	static int octeon_spi_probe(struct platform_device *pdev)
6b52c00f	182	{
6b52c00f	183	struct resource *res_mem;
3ae36c8b	184	void __iomem *reg_base;
6b52c00f DD	185	struct spi_master *master;
	186	struct octeon_spi *p;
	187	int err = -ENOENT;
	188
	189	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
	190	if (!master)
	191	return -ENOMEM;
	192	p = spi_master_get_devdata(master);
e1b18ea8	193	platform_set_drvdata(pdev, master);
6b52c00f DD	194
6b52c00f DD	195	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3ae36c8b AL	196	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
	197	if (IS_ERR(reg_base)) {
	198	err = PTR_ERR(reg_base);
6b52c00f DD	199	goto fail;
6b52c00f DD	200	}
3ae36c8b	201
187fc9b3	202	p->register_base = reg_base;
b9e64763	203	p->sys_freq = octeon_get_io_clock_rate();
6b52c00f	204
ee423c53 JG	205	p->regs.config = 0;
	206	p->regs.status = 0x08;
	207	p->regs.tx = 0x10;
	208	p->regs.data = 0x80;
	209
6b52c00f DD	210	master->num_chipselect = 4;
	211	master->mode_bits = SPI_CPHA \|
	212	SPI_CPOL \|
	213	SPI_CS_HIGH \|
	214	SPI_LSB_FIRST \|
	215	SPI_3WIRE;
	216
6b52c00f	217	master->transfer_one_message = octeon_spi_transfer_one_message;
f79cc88e	218	master->bits_per_word_mask = SPI_BPW_MASK(8);
7984b5ca	219	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
6b52c00f DD	220
6b52c00f DD	221	master->dev.of_node = pdev->dev.of_node;
22ad2d8d	222	err = devm_spi_register_master(&pdev->dev, master);
6b52c00f DD	223	if (err) {
	224	dev_err(&pdev->dev, "register master failed: %d\n", err);
	225	goto fail;
	226	}
	227
	228	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
	229
	230	return 0;
	231	fail:
	232	spi_master_put(master);
	233	return err;
	234	}
	235
fd4a319b	236	static int octeon_spi_remove(struct platform_device *pdev)
6b52c00f	237	{
e1b18ea8 AL	238	struct spi_master *master = platform_get_drvdata(pdev);
e1b18ea8 AL	239	struct octeon_spi *p = spi_master_get_devdata(master);
6b52c00f	240
6b52c00f	241	/* Clear the CSENA* and put everything in a known state. */
ee423c53	242	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
6b52c00f DD	243
	244	return 0;
	245	}
	246
09355402	247	static const struct of_device_id octeon_spi_match[] = {
6b52c00f DD	248	{ .compatible = "cavium,octeon-3010-spi", },
	249	{},
	250	};
	251	MODULE_DEVICE_TABLE(of, octeon_spi_match);
	252
	253	static struct platform_driver octeon_spi_driver = {
	254	.driver = {
	255	.name = "spi-octeon",
6b52c00f DD	256	.of_match_table = octeon_spi_match,
	257	},
	258	.probe = octeon_spi_probe,
fd4a319b	259	.remove = octeon_spi_remove,
6b52c00f DD	260	};
	261
	262	module_platform_driver(octeon_spi_driver);
	263
	264	MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
	265	MODULE_AUTHOR("David Daney");
	266	MODULE_LICENSE("GPL");