Commit | Line | Data |
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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
25 | #include <linux/interrupt.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
30 | #include <linux/dmaengine.h> |
31 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
32 | #include <linux/platform_device.h> |
33 | #include <linux/err.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/io.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1f1a4384 | 37 | #include <linux/pm_runtime.h> |
d5a80031 BC |
38 | #include <linux/of.h> |
39 | #include <linux/of_device.h> | |
d33f473d | 40 | #include <linux/gcd.h> |
ccdc7bf9 SO |
41 | |
42 | #include <linux/spi/spi.h> | |
43 | ||
2203747c | 44 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
45 | |
46 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 47 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
48 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
49 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 50 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
51 | |
52 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
53 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
54 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
55 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
56 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
57 | #define OMAP2_MCSPI_SYST 0x24 | |
58 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 59 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
60 | |
61 | /* per-channel banks, 0x14 bytes each, first is: */ | |
62 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
63 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
64 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
65 | #define OMAP2_MCSPI_TX0 0x38 | |
66 | #define OMAP2_MCSPI_RX0 0x3c | |
67 | ||
68 | /* per-register bitmasks: */ | |
d33f473d | 69 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
72 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
73 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 74 | |
7a8fa725 JH |
75 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
76 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 77 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 78 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
81 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 82 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
83 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
84 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
85 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
86 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
87 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
88 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
89 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
90 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
91 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 92 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 93 | |
7a8fa725 JH |
94 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
95 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
96 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 97 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 98 | |
7a8fa725 | 99 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 100 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 101 | |
7a8fa725 | 102 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
103 | |
104 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
105 | struct omap2_mcspi_dma { | |
53741ed8 RK |
106 | struct dma_chan *dma_tx; |
107 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
108 | |
109 | int dma_tx_sync_dev; | |
110 | int dma_rx_sync_dev; | |
111 | ||
112 | struct completion dma_tx_completion; | |
113 | struct completion dma_rx_completion; | |
74f3aaad MP |
114 | |
115 | char dma_rx_ch_name[14]; | |
116 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
117 | }; |
118 | ||
119 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
120 | * cache operations; better heuristics consider wordsize and bitrate. | |
121 | */ | |
8b66c134 | 122 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
123 | |
124 | ||
1bd897f8 BC |
125 | /* |
126 | * Used for context save and restore, structure members to be updated whenever | |
127 | * corresponding registers are modified. | |
128 | */ | |
129 | struct omap2_mcspi_regs { | |
130 | u32 modulctrl; | |
131 | u32 wakeupenable; | |
132 | struct list_head cs; | |
133 | }; | |
134 | ||
ccdc7bf9 | 135 | struct omap2_mcspi { |
ccdc7bf9 | 136 | struct spi_master *master; |
ccdc7bf9 SO |
137 | /* Virtual base address of the controller */ |
138 | void __iomem *base; | |
e5480b73 | 139 | unsigned long phys; |
ccdc7bf9 SO |
140 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
141 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 142 | struct device *dev; |
1bd897f8 | 143 | struct omap2_mcspi_regs ctx; |
d33f473d | 144 | int fifo_depth; |
0384e90b | 145 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
146 | }; |
147 | ||
148 | struct omap2_mcspi_cs { | |
149 | void __iomem *base; | |
e5480b73 | 150 | unsigned long phys; |
ccdc7bf9 | 151 | int word_len; |
97ca0d6c | 152 | u16 mode; |
89c05372 | 153 | struct list_head node; |
a41ae1ad | 154 | /* Context save and restore shadow register */ |
faee9b05 | 155 | u32 chconf0, chctrl0; |
a41ae1ad H |
156 | }; |
157 | ||
ccdc7bf9 SO |
158 | static inline void mcspi_write_reg(struct spi_master *master, |
159 | int idx, u32 val) | |
160 | { | |
161 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
162 | ||
21b2ce5e | 163 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
164 | } |
165 | ||
166 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
167 | { | |
168 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
169 | ||
21b2ce5e | 170 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
171 | } |
172 | ||
173 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
174 | int idx, u32 val) | |
175 | { | |
176 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
177 | ||
21b2ce5e | 178 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
179 | } |
180 | ||
181 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
182 | { | |
183 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
184 | ||
21b2ce5e | 185 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
186 | } |
187 | ||
a41ae1ad H |
188 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
189 | { | |
190 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
191 | ||
192 | return cs->chconf0; | |
193 | } | |
194 | ||
195 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
196 | { | |
197 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
198 | ||
199 | cs->chconf0 = val; | |
200 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 201 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
202 | } |
203 | ||
56cd5c15 IS |
204 | static inline int mcspi_bytes_per_word(int word_len) |
205 | { | |
206 | if (word_len <= 8) | |
207 | return 1; | |
208 | else if (word_len <= 16) | |
209 | return 2; | |
210 | else /* word_len <= 32 */ | |
211 | return 4; | |
212 | } | |
213 | ||
ccdc7bf9 SO |
214 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
215 | int is_read, int enable) | |
216 | { | |
217 | u32 l, rw; | |
218 | ||
a41ae1ad | 219 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
220 | |
221 | if (is_read) /* 1 is read, 0 write */ | |
222 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
223 | else | |
224 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
225 | ||
af4e944d S |
226 | if (enable) |
227 | l |= rw; | |
228 | else | |
229 | l &= ~rw; | |
230 | ||
a41ae1ad | 231 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
232 | } |
233 | ||
234 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
235 | { | |
faee9b05 | 236 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
237 | u32 l; |
238 | ||
faee9b05 SS |
239 | l = cs->chctrl0; |
240 | if (enable) | |
241 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
242 | else | |
243 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
244 | cs->chctrl0 = l; | |
245 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
246 | /* Flash post-writes */ |
247 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
248 | } |
249 | ||
250 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
251 | { | |
252 | u32 l; | |
253 | ||
a41ae1ad | 254 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
255 | if (cs_active) |
256 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
257 | else | |
258 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
259 | ||
a41ae1ad | 260 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
261 | } |
262 | ||
263 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
264 | { | |
1bd897f8 BC |
265 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
266 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
267 | u32 l; |
268 | ||
1bd897f8 BC |
269 | /* |
270 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
271 | * to single-channel master mode |
272 | */ | |
273 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
274 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
275 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 276 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 277 | |
1bd897f8 | 278 | ctx->modulctrl = l; |
a41ae1ad H |
279 | } |
280 | ||
d33f473d IS |
281 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
282 | struct spi_transfer *t, int enable) | |
283 | { | |
284 | struct spi_master *master = spi->master; | |
285 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
286 | struct omap2_mcspi *mcspi; | |
287 | unsigned int wcnt; | |
5db542ed | 288 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
289 | u32 chconf, xferlevel; |
290 | ||
291 | mcspi = spi_master_get_devdata(master); | |
292 | ||
293 | chconf = mcspi_cached_chconf0(spi); | |
294 | if (enable) { | |
295 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
296 | if (t->len % bytes_per_word != 0) | |
297 | goto disable_fifo; | |
298 | ||
5db542ed IS |
299 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
300 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
301 | else | |
302 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
303 | ||
304 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
305 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
306 | goto disable_fifo; | |
307 | ||
308 | wcnt = t->len / bytes_per_word; | |
309 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
310 | goto disable_fifo; | |
311 | ||
312 | xferlevel = wcnt << 16; | |
313 | if (t->rx_buf != NULL) { | |
314 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
315 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
316 | } |
317 | if (t->tx_buf != NULL) { | |
d33f473d IS |
318 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
319 | xferlevel |= fifo_depth - 1; | |
320 | } | |
321 | ||
322 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
323 | mcspi_write_chconf0(spi, chconf); | |
324 | mcspi->fifo_depth = fifo_depth; | |
325 | ||
326 | return; | |
327 | } | |
328 | ||
329 | disable_fifo: | |
330 | if (t->rx_buf != NULL) | |
331 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
332 | |
333 | if (t->tx_buf != NULL) | |
d33f473d IS |
334 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
335 | ||
336 | mcspi_write_chconf0(spi, chconf); | |
337 | mcspi->fifo_depth = 0; | |
338 | } | |
339 | ||
a41ae1ad H |
340 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
341 | { | |
1bd897f8 BC |
342 | struct spi_master *spi_cntrl = mcspi->master; |
343 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
344 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
345 | |
346 | /* McSPI: context restore */ | |
1bd897f8 BC |
347 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
348 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 349 | |
1bd897f8 | 350 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 351 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 352 | } |
ccdc7bf9 | 353 | |
2764c500 IK |
354 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
355 | { | |
356 | unsigned long timeout; | |
357 | ||
358 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 359 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 360 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 361 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
362 | return -ETIMEDOUT; |
363 | else | |
364 | return 0; | |
365 | } | |
2764c500 IK |
366 | cpu_relax(); |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
53741ed8 RK |
371 | static void omap2_mcspi_rx_callback(void *data) |
372 | { | |
373 | struct spi_device *spi = data; | |
374 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
375 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
376 | ||
53741ed8 RK |
377 | /* We must disable the DMA RX request */ |
378 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
379 | |
380 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
381 | } |
382 | ||
383 | static void omap2_mcspi_tx_callback(void *data) | |
384 | { | |
385 | struct spi_device *spi = data; | |
386 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
387 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
388 | ||
53741ed8 RK |
389 | /* We must disable the DMA TX request */ |
390 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
391 | |
392 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
393 | } |
394 | ||
d7b4394e S |
395 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
396 | struct spi_transfer *xfer, | |
397 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
398 | { |
399 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 400 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 401 | unsigned int count; |
ccdc7bf9 SO |
402 | |
403 | mcspi = spi_master_get_devdata(spi->master); | |
404 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 405 | count = xfer->len; |
ccdc7bf9 | 406 | |
d7b4394e | 407 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
408 | struct dma_async_tx_descriptor *tx; |
409 | struct scatterlist sg; | |
410 | ||
411 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
412 | ||
413 | sg_init_table(&sg, 1); | |
414 | sg_dma_address(&sg) = xfer->tx_dma; | |
415 | sg_dma_len(&sg) = xfer->len; | |
416 | ||
417 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 418 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
419 | if (tx) { |
420 | tx->callback = omap2_mcspi_tx_callback; | |
421 | tx->callback_param = spi; | |
422 | dmaengine_submit(tx); | |
423 | } else { | |
424 | /* FIXME: fall back to PIO? */ | |
425 | } | |
426 | } | |
d7b4394e S |
427 | dma_async_issue_pending(mcspi_dma->dma_tx); |
428 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
429 | ||
d7b4394e | 430 | } |
53741ed8 | 431 | |
d7b4394e S |
432 | static unsigned |
433 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
434 | struct dma_slave_config cfg, | |
435 | unsigned es) | |
436 | { | |
437 | struct omap2_mcspi *mcspi; | |
438 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 439 | unsigned int count, dma_count; |
d7b4394e S |
440 | u32 l; |
441 | int elements = 0; | |
442 | int word_len, element_count; | |
443 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
444 | mcspi = spi_master_get_devdata(spi->master); | |
445 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
446 | count = xfer->len; | |
d33f473d IS |
447 | dma_count = xfer->len; |
448 | ||
449 | if (mcspi->fifo_depth == 0) | |
450 | dma_count -= es; | |
451 | ||
d7b4394e S |
452 | word_len = cs->word_len; |
453 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 454 | |
d7b4394e S |
455 | if (word_len <= 8) |
456 | element_count = count; | |
457 | else if (word_len <= 16) | |
458 | element_count = count >> 1; | |
459 | else /* word_len <= 32 */ | |
460 | element_count = count >> 2; | |
461 | ||
462 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
463 | struct dma_async_tx_descriptor *tx; |
464 | struct scatterlist sg; | |
53741ed8 RK |
465 | |
466 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
467 | ||
d33f473d IS |
468 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
469 | dma_count -= es; | |
53741ed8 RK |
470 | |
471 | sg_init_table(&sg, 1); | |
472 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 473 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
474 | |
475 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
476 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
477 | DMA_CTRL_ACK); | |
53741ed8 RK |
478 | if (tx) { |
479 | tx->callback = omap2_mcspi_rx_callback; | |
480 | tx->callback_param = spi; | |
481 | dmaengine_submit(tx); | |
482 | } else { | |
d7b4394e | 483 | /* FIXME: fall back to PIO? */ |
2764c500 | 484 | } |
ccdc7bf9 SO |
485 | } |
486 | ||
d7b4394e S |
487 | dma_async_issue_pending(mcspi_dma->dma_rx); |
488 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 489 | |
d7b4394e S |
490 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
491 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
492 | DMA_FROM_DEVICE); | |
d33f473d IS |
493 | |
494 | if (mcspi->fifo_depth > 0) | |
495 | return count; | |
496 | ||
d7b4394e | 497 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 498 | |
d7b4394e | 499 | elements = element_count - 1; |
4743a0f8 | 500 | |
d7b4394e S |
501 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
502 | elements--; | |
4743a0f8 | 503 | |
57c5c28d | 504 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 505 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
506 | u32 w; |
507 | ||
508 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
509 | if (word_len <= 8) | |
d7b4394e | 510 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 511 | else if (word_len <= 16) |
d7b4394e | 512 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 513 | else /* word_len <= 32 */ |
d7b4394e | 514 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 515 | } else { |
56cd5c15 | 516 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 517 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 518 | count -= (bytes_per_word << 1); |
d7b4394e S |
519 | omap2_mcspi_set_enable(spi, 1); |
520 | return count; | |
57c5c28d | 521 | } |
ccdc7bf9 | 522 | } |
d7b4394e S |
523 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
524 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
525 | u32 w; | |
526 | ||
527 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
528 | if (word_len <= 8) | |
529 | ((u8 *)xfer->rx_buf)[elements] = w; | |
530 | else if (word_len <= 16) | |
531 | ((u16 *)xfer->rx_buf)[elements] = w; | |
532 | else /* word_len <= 32 */ | |
533 | ((u32 *)xfer->rx_buf)[elements] = w; | |
534 | } else { | |
a1829d2b | 535 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 536 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
537 | } |
538 | omap2_mcspi_set_enable(spi, 1); | |
539 | return count; | |
540 | } | |
541 | ||
542 | static unsigned | |
543 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
544 | { | |
545 | struct omap2_mcspi *mcspi; | |
546 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
547 | struct omap2_mcspi_dma *mcspi_dma; | |
548 | unsigned int count; | |
549 | u32 l; | |
550 | u8 *rx; | |
551 | const u8 *tx; | |
552 | struct dma_slave_config cfg; | |
553 | enum dma_slave_buswidth width; | |
554 | unsigned es; | |
d33f473d | 555 | u32 burst; |
e47a682a | 556 | void __iomem *chstat_reg; |
d33f473d IS |
557 | void __iomem *irqstat_reg; |
558 | int wait_res; | |
d7b4394e S |
559 | |
560 | mcspi = spi_master_get_devdata(spi->master); | |
561 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
562 | l = mcspi_cached_chconf0(spi); | |
563 | ||
564 | ||
565 | if (cs->word_len <= 8) { | |
566 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
567 | es = 1; | |
568 | } else if (cs->word_len <= 16) { | |
569 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
570 | es = 2; | |
571 | } else { | |
572 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
573 | es = 4; | |
574 | } | |
575 | ||
d33f473d IS |
576 | count = xfer->len; |
577 | burst = 1; | |
578 | ||
579 | if (mcspi->fifo_depth > 0) { | |
580 | if (count > mcspi->fifo_depth) | |
581 | burst = mcspi->fifo_depth / es; | |
582 | else | |
583 | burst = count / es; | |
584 | } | |
585 | ||
d7b4394e S |
586 | memset(&cfg, 0, sizeof(cfg)); |
587 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
588 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
589 | cfg.src_addr_width = width; | |
590 | cfg.dst_addr_width = width; | |
d33f473d IS |
591 | cfg.src_maxburst = burst; |
592 | cfg.dst_maxburst = burst; | |
d7b4394e S |
593 | |
594 | rx = xfer->rx_buf; | |
595 | tx = xfer->tx_buf; | |
596 | ||
d7b4394e S |
597 | if (tx != NULL) |
598 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
599 | ||
600 | if (rx != NULL) | |
e47a682a S |
601 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
602 | ||
603 | if (tx != NULL) { | |
e47a682a S |
604 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
605 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
606 | DMA_TO_DEVICE); | |
607 | ||
d33f473d IS |
608 | if (mcspi->fifo_depth > 0) { |
609 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
610 | ||
611 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
612 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
613 | dev_err(&spi->dev, "EOW timed out\n"); | |
614 | ||
615 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
616 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
617 | } | |
618 | ||
e47a682a S |
619 | /* for TX_ONLY mode, be sure all words have shifted out */ |
620 | if (rx == NULL) { | |
d33f473d IS |
621 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
622 | if (mcspi->fifo_depth > 0) { | |
623 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
624 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
625 | if (wait_res < 0) | |
626 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
627 | } else { | |
628 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
629 | OMAP2_MCSPI_CHSTAT_TXS); | |
630 | if (wait_res < 0) | |
631 | dev_err(&spi->dev, "TXS timed out\n"); | |
632 | } | |
633 | if (wait_res >= 0 && | |
634 | (mcspi_wait_for_reg_bit(chstat_reg, | |
635 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
636 | dev_err(&spi->dev, "EOT timed out\n"); |
637 | } | |
638 | } | |
ccdc7bf9 SO |
639 | return count; |
640 | } | |
641 | ||
ccdc7bf9 SO |
642 | static unsigned |
643 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
644 | { | |
645 | struct omap2_mcspi *mcspi; | |
646 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
647 | unsigned int count, c; | |
648 | u32 l; | |
649 | void __iomem *base = cs->base; | |
650 | void __iomem *tx_reg; | |
651 | void __iomem *rx_reg; | |
652 | void __iomem *chstat_reg; | |
653 | int word_len; | |
654 | ||
655 | mcspi = spi_master_get_devdata(spi->master); | |
656 | count = xfer->len; | |
657 | c = count; | |
658 | word_len = cs->word_len; | |
659 | ||
a41ae1ad | 660 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
661 | |
662 | /* We store the pre-calculated register addresses on stack to speed | |
663 | * up the transfer loop. */ | |
664 | tx_reg = base + OMAP2_MCSPI_TX0; | |
665 | rx_reg = base + OMAP2_MCSPI_RX0; | |
666 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
667 | ||
adef658d MJ |
668 | if (c < (word_len>>3)) |
669 | return 0; | |
670 | ||
ccdc7bf9 SO |
671 | if (word_len <= 8) { |
672 | u8 *rx; | |
673 | const u8 *tx; | |
674 | ||
675 | rx = xfer->rx_buf; | |
676 | tx = xfer->tx_buf; | |
677 | ||
678 | do { | |
feed9bab | 679 | c -= 1; |
ccdc7bf9 SO |
680 | if (tx != NULL) { |
681 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
682 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
683 | dev_err(&spi->dev, "TXS timed out\n"); | |
684 | goto out; | |
685 | } | |
079a176d | 686 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 687 | word_len, *tx); |
21b2ce5e | 688 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
689 | } |
690 | if (rx != NULL) { | |
691 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
692 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
693 | dev_err(&spi->dev, "RXS timed out\n"); | |
694 | goto out; | |
695 | } | |
4743a0f8 RT |
696 | |
697 | if (c == 1 && tx == NULL && | |
698 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
699 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 700 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 701 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 702 | word_len, *(rx - 1)); |
4743a0f8 RT |
703 | if (mcspi_wait_for_reg_bit(chstat_reg, |
704 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
705 | dev_err(&spi->dev, | |
706 | "RXS timed out\n"); | |
707 | goto out; | |
708 | } | |
709 | c = 0; | |
710 | } else if (c == 0 && tx == NULL) { | |
711 | omap2_mcspi_set_enable(spi, 0); | |
712 | } | |
713 | ||
21b2ce5e | 714 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 715 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 716 | word_len, *(rx - 1)); |
ccdc7bf9 | 717 | } |
95c5c3ab | 718 | } while (c); |
ccdc7bf9 SO |
719 | } else if (word_len <= 16) { |
720 | u16 *rx; | |
721 | const u16 *tx; | |
722 | ||
723 | rx = xfer->rx_buf; | |
724 | tx = xfer->tx_buf; | |
725 | do { | |
feed9bab | 726 | c -= 2; |
ccdc7bf9 SO |
727 | if (tx != NULL) { |
728 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
729 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
730 | dev_err(&spi->dev, "TXS timed out\n"); | |
731 | goto out; | |
732 | } | |
079a176d | 733 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 734 | word_len, *tx); |
21b2ce5e | 735 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
736 | } |
737 | if (rx != NULL) { | |
738 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
739 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
740 | dev_err(&spi->dev, "RXS timed out\n"); | |
741 | goto out; | |
742 | } | |
4743a0f8 RT |
743 | |
744 | if (c == 2 && tx == NULL && | |
745 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
746 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 747 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 748 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 749 | word_len, *(rx - 1)); |
4743a0f8 RT |
750 | if (mcspi_wait_for_reg_bit(chstat_reg, |
751 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
752 | dev_err(&spi->dev, | |
753 | "RXS timed out\n"); | |
754 | goto out; | |
755 | } | |
756 | c = 0; | |
757 | } else if (c == 0 && tx == NULL) { | |
758 | omap2_mcspi_set_enable(spi, 0); | |
759 | } | |
760 | ||
21b2ce5e | 761 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 762 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 763 | word_len, *(rx - 1)); |
ccdc7bf9 | 764 | } |
95c5c3ab | 765 | } while (c >= 2); |
ccdc7bf9 SO |
766 | } else if (word_len <= 32) { |
767 | u32 *rx; | |
768 | const u32 *tx; | |
769 | ||
770 | rx = xfer->rx_buf; | |
771 | tx = xfer->tx_buf; | |
772 | do { | |
feed9bab | 773 | c -= 4; |
ccdc7bf9 SO |
774 | if (tx != NULL) { |
775 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
776 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
777 | dev_err(&spi->dev, "TXS timed out\n"); | |
778 | goto out; | |
779 | } | |
079a176d | 780 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 781 | word_len, *tx); |
21b2ce5e | 782 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
783 | } |
784 | if (rx != NULL) { | |
785 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
786 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
787 | dev_err(&spi->dev, "RXS timed out\n"); | |
788 | goto out; | |
789 | } | |
4743a0f8 RT |
790 | |
791 | if (c == 4 && tx == NULL && | |
792 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
793 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 794 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 795 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 796 | word_len, *(rx - 1)); |
4743a0f8 RT |
797 | if (mcspi_wait_for_reg_bit(chstat_reg, |
798 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
799 | dev_err(&spi->dev, | |
800 | "RXS timed out\n"); | |
801 | goto out; | |
802 | } | |
803 | c = 0; | |
804 | } else if (c == 0 && tx == NULL) { | |
805 | omap2_mcspi_set_enable(spi, 0); | |
806 | } | |
807 | ||
21b2ce5e | 808 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 809 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 810 | word_len, *(rx - 1)); |
ccdc7bf9 | 811 | } |
95c5c3ab | 812 | } while (c >= 4); |
ccdc7bf9 SO |
813 | } |
814 | ||
815 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
816 | if (xfer->rx_buf == NULL) { | |
817 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
818 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
819 | dev_err(&spi->dev, "TXS timed out\n"); | |
820 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
821 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
822 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
823 | |
824 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
825 | * otherwise these rx datas will affect the direct following | |
826 | * RX_ONLY transfer. | |
827 | */ | |
828 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
829 | } |
830 | out: | |
4743a0f8 | 831 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
832 | return count - c; |
833 | } | |
834 | ||
57d9c10d HH |
835 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
836 | { | |
837 | u32 div; | |
838 | ||
839 | for (div = 0; div < 15; div++) | |
840 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
841 | return div; | |
842 | ||
843 | return 15; | |
844 | } | |
845 | ||
ccdc7bf9 SO |
846 | /* called only when no transfer is active to this device */ |
847 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
848 | struct spi_transfer *t) | |
849 | { | |
850 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
851 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 852 | struct spi_master *spi_cntrl; |
faee9b05 | 853 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 854 | u8 word_len = spi->bits_per_word; |
9bd4517d | 855 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
856 | |
857 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 858 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
859 | |
860 | if (t != NULL && t->bits_per_word) | |
861 | word_len = t->bits_per_word; | |
862 | ||
863 | cs->word_len = word_len; | |
864 | ||
9bd4517d SE |
865 | if (t && t->speed_hz) |
866 | speed_hz = t->speed_hz; | |
867 | ||
57d9c10d | 868 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
869 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
870 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
871 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
872 | clkg = 0; | |
873 | } else { | |
874 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
875 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
876 | clkd = (div - 1) & 0xf; | |
877 | extclk = (div - 1) >> 4; | |
878 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
879 | } | |
ccdc7bf9 | 880 | |
a41ae1ad | 881 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
882 | |
883 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
884 | * REVISIT: this controller could support SPI_3WIRE mode. | |
885 | */ | |
2cd45179 | 886 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
887 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
888 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
889 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
890 | } else { | |
891 | l |= OMAP2_MCSPI_CHCONF_IS; | |
892 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
893 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
894 | } | |
ccdc7bf9 SO |
895 | |
896 | /* wordlength */ | |
897 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
898 | l |= (word_len - 1) << 7; | |
899 | ||
900 | /* set chipselect polarity; manage with FORCE */ | |
901 | if (!(spi->mode & SPI_CS_HIGH)) | |
902 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
903 | else | |
904 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
905 | ||
906 | /* set clock divisor */ | |
907 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
908 | l |= clkd << 2; |
909 | ||
910 | /* set clock granularity */ | |
911 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
912 | l |= clkg; | |
913 | if (clkg) { | |
914 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
915 | cs->chctrl0 |= extclk << 8; | |
916 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
917 | } | |
ccdc7bf9 SO |
918 | |
919 | /* set SPI mode 0..3 */ | |
920 | if (spi->mode & SPI_CPOL) | |
921 | l |= OMAP2_MCSPI_CHCONF_POL; | |
922 | else | |
923 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
924 | if (spi->mode & SPI_CPHA) | |
925 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
926 | else | |
927 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
928 | ||
a41ae1ad | 929 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 930 | |
97ca0d6c MG |
931 | cs->mode = spi->mode; |
932 | ||
ccdc7bf9 | 933 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 934 | speed_hz, |
ccdc7bf9 SO |
935 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
936 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
ddc5cdf1 TL |
941 | /* |
942 | * Note that we currently allow DMA only if we get a channel | |
943 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
944 | */ | |
ccdc7bf9 SO |
945 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
946 | { | |
947 | struct spi_master *master = spi->master; | |
948 | struct omap2_mcspi *mcspi; | |
949 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
950 | dma_cap_mask_t mask; |
951 | unsigned sig; | |
ccdc7bf9 SO |
952 | |
953 | mcspi = spi_master_get_devdata(master); | |
954 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
955 | ||
53741ed8 RK |
956 | init_completion(&mcspi_dma->dma_rx_completion); |
957 | init_completion(&mcspi_dma->dma_tx_completion); | |
958 | ||
959 | dma_cap_zero(mask); | |
960 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 961 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
962 | |
963 | mcspi_dma->dma_rx = | |
964 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
965 | &sig, &master->dev, | |
966 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
967 | if (!mcspi_dma->dma_rx) |
968 | goto no_dma; | |
ccdc7bf9 | 969 | |
53741ed8 | 970 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
971 | mcspi_dma->dma_tx = |
972 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
973 | &sig, &master->dev, | |
974 | mcspi_dma->dma_tx_ch_name); | |
975 | ||
53741ed8 | 976 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
977 | dma_release_channel(mcspi_dma->dma_rx); |
978 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 979 | goto no_dma; |
ccdc7bf9 SO |
980 | } |
981 | ||
ccdc7bf9 | 982 | return 0; |
ddc5cdf1 TL |
983 | |
984 | no_dma: | |
985 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
986 | return -EAGAIN; | |
ccdc7bf9 SO |
987 | } |
988 | ||
ccdc7bf9 SO |
989 | static int omap2_mcspi_setup(struct spi_device *spi) |
990 | { | |
991 | int ret; | |
1bd897f8 BC |
992 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
993 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
994 | struct omap2_mcspi_dma *mcspi_dma; |
995 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
996 | ||
ccdc7bf9 SO |
997 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
998 | ||
999 | if (!cs) { | |
10aa5a35 | 1000 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
1001 | if (!cs) |
1002 | return -ENOMEM; | |
1003 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1004 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1005 | cs->mode = 0; |
a41ae1ad | 1006 | cs->chconf0 = 0; |
faee9b05 | 1007 | cs->chctrl0 = 0; |
ccdc7bf9 | 1008 | spi->controller_state = cs; |
89c05372 | 1009 | /* Link this to context save list */ |
1bd897f8 | 1010 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
1011 | } |
1012 | ||
8c7494a5 | 1013 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1014 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1015 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1016 | return ret; |
1017 | } | |
1018 | ||
034d3dc9 | 1019 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1020 | if (ret < 0) |
1021 | return ret; | |
a41ae1ad | 1022 | |
86eeb6fe | 1023 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1024 | pm_runtime_mark_last_busy(mcspi->dev); |
1025 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1026 | |
1027 | return ret; | |
1028 | } | |
1029 | ||
1030 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1031 | { | |
1032 | struct omap2_mcspi *mcspi; | |
1033 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1034 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1035 | |
1036 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1037 | |
5e774943 SE |
1038 | if (spi->controller_state) { |
1039 | /* Unlink controller state from context save list */ | |
1040 | cs = spi->controller_state; | |
1041 | list_del(&cs->node); | |
89c05372 | 1042 | |
10aa5a35 | 1043 | kfree(cs); |
5e774943 | 1044 | } |
ccdc7bf9 | 1045 | |
99f1a43f SE |
1046 | if (spi->chip_select < spi->master->num_chipselect) { |
1047 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1048 | ||
53741ed8 RK |
1049 | if (mcspi_dma->dma_rx) { |
1050 | dma_release_channel(mcspi_dma->dma_rx); | |
1051 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1052 | } |
53741ed8 RK |
1053 | if (mcspi_dma->dma_tx) { |
1054 | dma_release_channel(mcspi_dma->dma_tx); | |
1055 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1056 | } |
ccdc7bf9 SO |
1057 | } |
1058 | } | |
1059 | ||
5fda88f5 | 1060 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 1061 | { |
ccdc7bf9 SO |
1062 | |
1063 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1064 | * -- although this controller would gladly |
ccdc7bf9 SO |
1065 | * arbitrate among multiple channels. This corresponds to "single |
1066 | * channel" master mode. As a side effect, we need to manage the | |
1067 | * chipselect with the FORCE bit ... CS != channel enable. | |
1068 | */ | |
ccdc7bf9 | 1069 | |
5fda88f5 S |
1070 | struct spi_device *spi; |
1071 | struct spi_transfer *t = NULL; | |
5cbc7ca9 | 1072 | struct spi_master *master; |
ddc5cdf1 | 1073 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1074 | int cs_active = 0; |
1075 | struct omap2_mcspi_cs *cs; | |
1076 | struct omap2_mcspi_device_config *cd; | |
1077 | int par_override = 0; | |
1078 | int status = 0; | |
1079 | u32 chconf; | |
ccdc7bf9 | 1080 | |
5fda88f5 | 1081 | spi = m->spi; |
5cbc7ca9 | 1082 | master = spi->master; |
ddc5cdf1 | 1083 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1084 | cs = spi->controller_state; |
1085 | cd = spi->controller_data; | |
ccdc7bf9 | 1086 | |
97ca0d6c MG |
1087 | /* |
1088 | * The slave driver could have changed spi->mode in which case | |
1089 | * it will be different from cs->mode (the current hardware setup). | |
1090 | * If so, set par_override (even though its not a parity issue) so | |
1091 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1092 | * with the correct mode on the first iteration of the loop below. | |
1093 | */ | |
1094 | if (spi->mode != cs->mode) | |
1095 | par_override = 1; | |
1096 | ||
d33f473d | 1097 | omap2_mcspi_set_enable(spi, 0); |
5fda88f5 S |
1098 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1099 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
1100 | status = -EINVAL; | |
1101 | break; | |
1102 | } | |
2bd16e3e SS |
1103 | if (par_override || |
1104 | (t->speed_hz != spi->max_speed_hz) || | |
1105 | (t->bits_per_word != spi->bits_per_word)) { | |
5fda88f5 S |
1106 | par_override = 1; |
1107 | status = omap2_mcspi_setup_transfer(spi, t); | |
1108 | if (status < 0) | |
1109 | break; | |
2bd16e3e SS |
1110 | if (t->speed_hz == spi->max_speed_hz && |
1111 | t->bits_per_word == spi->bits_per_word) | |
5fda88f5 S |
1112 | par_override = 0; |
1113 | } | |
5cbc7ca9 MB |
1114 | if (cd && cd->cs_per_word) { |
1115 | chconf = mcspi->ctx.modulctrl; | |
1116 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1117 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1118 | mcspi->ctx.modulctrl = | |
1119 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1120 | } | |
1121 | ||
4743a0f8 | 1122 | |
5fda88f5 S |
1123 | if (!cs_active) { |
1124 | omap2_mcspi_force_cs(spi, 1); | |
1125 | cs_active = 1; | |
1126 | } | |
4743a0f8 | 1127 | |
5fda88f5 S |
1128 | chconf = mcspi_cached_chconf0(spi); |
1129 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1130 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 1131 | |
5fda88f5 S |
1132 | if (t->tx_buf == NULL) |
1133 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1134 | else if (t->rx_buf == NULL) | |
1135 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 1136 | |
5fda88f5 S |
1137 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
1138 | /* Turbo mode is for more than one word */ | |
1139 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1140 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1141 | } | |
ccdc7bf9 | 1142 | |
5fda88f5 | 1143 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1144 | |
5fda88f5 S |
1145 | if (t->len) { |
1146 | unsigned count; | |
1147 | ||
d33f473d IS |
1148 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1149 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
1150 | omap2_mcspi_set_fifo(spi, t, 1); | |
1151 | ||
1152 | omap2_mcspi_set_enable(spi, 1); | |
1153 | ||
5fda88f5 S |
1154 | /* RX_ONLY mode needs dummy data in TX reg */ |
1155 | if (t->tx_buf == NULL) | |
21b2ce5e | 1156 | writel_relaxed(0, cs->base |
5fda88f5 | 1157 | + OMAP2_MCSPI_TX0); |
ccdc7bf9 | 1158 | |
ddc5cdf1 TL |
1159 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1160 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
5fda88f5 S |
1161 | count = omap2_mcspi_txrx_dma(spi, t); |
1162 | else | |
1163 | count = omap2_mcspi_txrx_pio(spi, t); | |
1164 | m->actual_length += count; | |
ccdc7bf9 | 1165 | |
5fda88f5 S |
1166 | if (count != t->len) { |
1167 | status = -EIO; | |
1168 | break; | |
ccdc7bf9 SO |
1169 | } |
1170 | } | |
1171 | ||
5fda88f5 S |
1172 | if (t->delay_usecs) |
1173 | udelay(t->delay_usecs); | |
ccdc7bf9 | 1174 | |
5fda88f5 S |
1175 | /* ignore the "leave it on after last xfer" hint */ |
1176 | if (t->cs_change) { | |
ccdc7bf9 | 1177 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1178 | cs_active = 0; |
1179 | } | |
d33f473d IS |
1180 | |
1181 | omap2_mcspi_set_enable(spi, 0); | |
1182 | ||
1183 | if (mcspi->fifo_depth > 0) | |
1184 | omap2_mcspi_set_fifo(spi, t, 0); | |
5fda88f5 S |
1185 | } |
1186 | /* Restore defaults if they were overriden */ | |
1187 | if (par_override) { | |
1188 | par_override = 0; | |
1189 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1190 | } | |
ccdc7bf9 | 1191 | |
5fda88f5 S |
1192 | if (cs_active) |
1193 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1194 | |
5cbc7ca9 MB |
1195 | if (cd && cd->cs_per_word) { |
1196 | chconf = mcspi->ctx.modulctrl; | |
1197 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1198 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1199 | mcspi->ctx.modulctrl = | |
1200 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1201 | } | |
1202 | ||
5fda88f5 | 1203 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1204 | |
d33f473d IS |
1205 | if (mcspi->fifo_depth > 0 && t) |
1206 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1207 | |
d33f473d | 1208 | m->status = status; |
ccdc7bf9 SO |
1209 | } |
1210 | ||
5fda88f5 | 1211 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
18dd6199 | 1212 | struct spi_message *m) |
ccdc7bf9 | 1213 | { |
ddc5cdf1 | 1214 | struct spi_device *spi; |
ccdc7bf9 | 1215 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1216 | struct omap2_mcspi_dma *mcspi_dma; |
ccdc7bf9 SO |
1217 | struct spi_transfer *t; |
1218 | ||
ddc5cdf1 | 1219 | spi = m->spi; |
5fda88f5 | 1220 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1221 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 SO |
1222 | m->actual_length = 0; |
1223 | m->status = 0; | |
1224 | ||
ccdc7bf9 SO |
1225 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1226 | const void *tx_buf = t->tx_buf; | |
1227 | void *rx_buf = t->rx_buf; | |
1228 | unsigned len = t->len; | |
1229 | ||
aca0924b | 1230 | if ((len && !(rx_buf || tx_buf))) { |
5fda88f5 | 1231 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1232 | t->speed_hz, |
1233 | len, | |
1234 | tx_buf ? "tx" : "", | |
1235 | rx_buf ? "rx" : "", | |
1236 | t->bits_per_word); | |
1237 | return -EINVAL; | |
1238 | } | |
ccdc7bf9 SO |
1239 | |
1240 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1241 | continue; | |
1242 | ||
ddc5cdf1 | 1243 | if (mcspi_dma->dma_tx && tx_buf != NULL) { |
5fda88f5 | 1244 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1245 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1246 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1247 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1248 | 'T', len); |
1249 | return -EINVAL; | |
1250 | } | |
1251 | } | |
ddc5cdf1 | 1252 | if (mcspi_dma->dma_rx && rx_buf != NULL) { |
5fda88f5 | 1253 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1254 | DMA_FROM_DEVICE); |
5fda88f5 S |
1255 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1256 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1257 | 'R', len); |
1258 | if (tx_buf != NULL) | |
5fda88f5 | 1259 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1260 | len, DMA_TO_DEVICE); |
1261 | return -EINVAL; | |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | ||
5fda88f5 S |
1266 | omap2_mcspi_work(mcspi, m); |
1267 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1268 | return 0; |
1269 | } | |
1270 | ||
fd4a319b | 1271 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1272 | { |
1273 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1274 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1275 | int ret = 0; |
ccdc7bf9 | 1276 | |
034d3dc9 | 1277 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1278 | if (ret < 0) |
1279 | return ret; | |
ddb22195 | 1280 | |
39f8052d | 1281 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1282 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1283 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1284 | |
1285 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1286 | pm_runtime_mark_last_busy(mcspi->dev); |
1287 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1288 | return 0; |
1289 | } | |
1290 | ||
1f1a4384 G |
1291 | static int omap_mcspi_runtime_resume(struct device *dev) |
1292 | { | |
1293 | struct omap2_mcspi *mcspi; | |
1294 | struct spi_master *master; | |
1295 | ||
1296 | master = dev_get_drvdata(dev); | |
1297 | mcspi = spi_master_get_devdata(master); | |
1298 | omap2_mcspi_restore_ctx(mcspi); | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
d5a80031 BC |
1303 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1304 | .regs_offset = 0, | |
1305 | }; | |
1306 | ||
1307 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1308 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1309 | }; | |
1310 | ||
1311 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1312 | { | |
1313 | .compatible = "ti,omap2-mcspi", | |
1314 | .data = &omap2_pdata, | |
1315 | }, | |
1316 | { | |
1317 | .compatible = "ti,omap4-mcspi", | |
1318 | .data = &omap4_pdata, | |
1319 | }, | |
1320 | { }, | |
1321 | }; | |
1322 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1323 | |
fd4a319b | 1324 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1325 | { |
1326 | struct spi_master *master; | |
83a01e72 | 1327 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1328 | struct omap2_mcspi *mcspi; |
1329 | struct resource *r; | |
1330 | int status = 0, i; | |
d5a80031 BC |
1331 | u32 regs_offset = 0; |
1332 | static int bus_num = 1; | |
1333 | struct device_node *node = pdev->dev.of_node; | |
1334 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1335 | |
1336 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1337 | if (master == NULL) { | |
1338 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1339 | return -ENOMEM; | |
1340 | } | |
1341 | ||
e7db06b5 DB |
1342 | /* the spi->mode bits understood by this driver: */ |
1343 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1344 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1345 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1346 | master->auto_runtime_pm = true; |
5fda88f5 | 1347 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
ccdc7bf9 | 1348 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1349 | master->dev.of_node = node; |
aca0924b AL |
1350 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1351 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1352 | |
24b5a82c | 1353 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1354 | |
1355 | mcspi = spi_master_get_devdata(master); | |
1356 | mcspi->master = master; | |
1357 | ||
d5a80031 BC |
1358 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1359 | if (match) { | |
1360 | u32 num_cs = 1; /* default number of chipselect */ | |
1361 | pdata = match->data; | |
1362 | ||
1363 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1364 | master->num_chipselect = num_cs; | |
1365 | master->bus_num = bus_num++; | |
2cd45179 DM |
1366 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1367 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1368 | } else { |
8074cf06 | 1369 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1370 | master->num_chipselect = pdata->num_cs; |
1371 | if (pdev->id != -1) | |
1372 | master->bus_num = pdev->id; | |
0384e90b | 1373 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1374 | } |
1375 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1376 | |
ccdc7bf9 SO |
1377 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1378 | if (r == NULL) { | |
1379 | status = -ENODEV; | |
39f1b565 | 1380 | goto free_master; |
ccdc7bf9 | 1381 | } |
1458d160 | 1382 | |
d5a80031 BC |
1383 | r->start += regs_offset; |
1384 | r->end += regs_offset; | |
1458d160 | 1385 | mcspi->phys = r->start; |
ccdc7bf9 | 1386 | |
b0ee5605 TR |
1387 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1388 | if (IS_ERR(mcspi->base)) { | |
1389 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1390 | goto free_master; |
55c381e4 | 1391 | } |
ccdc7bf9 | 1392 | |
1f1a4384 | 1393 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1394 | |
1bd897f8 | 1395 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1396 | |
a6f936db AL |
1397 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1398 | sizeof(struct omap2_mcspi_dma), | |
1399 | GFP_KERNEL); | |
1400 | if (mcspi->dma_channels == NULL) { | |
1401 | status = -ENOMEM; | |
1a77b127 | 1402 | goto free_master; |
a6f936db | 1403 | } |
ccdc7bf9 | 1404 | |
1a5d8190 | 1405 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1406 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1407 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1408 | struct resource *dma_res; |
1409 | ||
74f3aaad MP |
1410 | sprintf(dma_rx_ch_name, "rx%d", i); |
1411 | if (!pdev->dev.of_node) { | |
1412 | dma_res = | |
1413 | platform_get_resource_byname(pdev, | |
1414 | IORESOURCE_DMA, | |
1415 | dma_rx_ch_name); | |
1416 | if (!dma_res) { | |
1417 | dev_dbg(&pdev->dev, | |
1418 | "cannot get DMA RX channel\n"); | |
1419 | status = -ENODEV; | |
1420 | break; | |
1421 | } | |
1a5d8190 | 1422 | |
74f3aaad MP |
1423 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1424 | dma_res->start; | |
1a5d8190 | 1425 | } |
74f3aaad MP |
1426 | sprintf(dma_tx_ch_name, "tx%d", i); |
1427 | if (!pdev->dev.of_node) { | |
1428 | dma_res = | |
1429 | platform_get_resource_byname(pdev, | |
1430 | IORESOURCE_DMA, | |
1431 | dma_tx_ch_name); | |
1432 | if (!dma_res) { | |
1433 | dev_dbg(&pdev->dev, | |
1434 | "cannot get DMA TX channel\n"); | |
1435 | status = -ENODEV; | |
1436 | break; | |
1437 | } | |
1a5d8190 | 1438 | |
74f3aaad MP |
1439 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1440 | dma_res->start; | |
1441 | } | |
ccdc7bf9 SO |
1442 | } |
1443 | ||
39f1b565 | 1444 | if (status < 0) |
a6f936db | 1445 | goto free_master; |
39f1b565 | 1446 | |
27b5284c S |
1447 | pm_runtime_use_autosuspend(&pdev->dev); |
1448 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1449 | pm_runtime_enable(&pdev->dev); |
1450 | ||
142e07be WY |
1451 | status = omap2_mcspi_master_setup(mcspi); |
1452 | if (status < 0) | |
39f1b565 | 1453 | goto disable_pm; |
ccdc7bf9 | 1454 | |
b95e02b7 | 1455 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1456 | if (status < 0) |
37a2d84a | 1457 | goto disable_pm; |
ccdc7bf9 SO |
1458 | |
1459 | return status; | |
1460 | ||
39f1b565 | 1461 | disable_pm: |
751c925c | 1462 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1463 | free_master: |
37a2d84a | 1464 | spi_master_put(master); |
ccdc7bf9 SO |
1465 | return status; |
1466 | } | |
1467 | ||
fd4a319b | 1468 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1469 | { |
a6f936db AL |
1470 | struct spi_master *master = platform_get_drvdata(pdev); |
1471 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1472 | |
a93a2029 | 1473 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1474 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1475 | |
ccdc7bf9 SO |
1476 | return 0; |
1477 | } | |
1478 | ||
7e38c3c4 KS |
1479 | /* work with hotplug and coldplug */ |
1480 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1481 | ||
42ce7fd6 GC |
1482 | #ifdef CONFIG_SUSPEND |
1483 | /* | |
1484 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1485 | * unactive state when driver was suspend, then force it to unactive state at | |
1486 | * wake up. | |
1487 | */ | |
1488 | static int omap2_mcspi_resume(struct device *dev) | |
1489 | { | |
1490 | struct spi_master *master = dev_get_drvdata(dev); | |
1491 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1492 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1493 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1494 | |
034d3dc9 | 1495 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1496 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1497 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1498 | /* |
1499 | * We need to toggle CS state for OMAP take this | |
1500 | * change in account. | |
1501 | */ | |
af4e944d | 1502 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1503 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1504 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1505 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1506 | } |
1507 | } | |
034d3dc9 S |
1508 | pm_runtime_mark_last_busy(mcspi->dev); |
1509 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1510 | return 0; |
1511 | } | |
1512 | #else | |
1513 | #define omap2_mcspi_resume NULL | |
1514 | #endif | |
1515 | ||
1516 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1517 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1518 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1519 | }; |
1520 | ||
ccdc7bf9 SO |
1521 | static struct platform_driver omap2_mcspi_driver = { |
1522 | .driver = { | |
1523 | .name = "omap2_mcspi", | |
1524 | .owner = THIS_MODULE, | |
d5a80031 BC |
1525 | .pm = &omap2_mcspi_pm_ops, |
1526 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1527 | }, |
7d6b6d83 | 1528 | .probe = omap2_mcspi_probe, |
fd4a319b | 1529 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1530 | }; |
1531 | ||
9fdca9df | 1532 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1533 | MODULE_LICENSE("GPL"); |