Commit | Line | Data |
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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/omap-dma.h> | |
beca3655 | 27 | #include <linux/pinctrl/consumer.h> |
ccdc7bf9 SO |
28 | #include <linux/platform_device.h> |
29 | #include <linux/err.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
1f1a4384 | 33 | #include <linux/pm_runtime.h> |
d5a80031 BC |
34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | |
d33f473d | 36 | #include <linux/gcd.h> |
ccdc7bf9 SO |
37 | |
38 | #include <linux/spi/spi.h> | |
bc7f9bbc | 39 | #include <linux/gpio.h> |
ccdc7bf9 | 40 | |
2203747c | 41 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
42 | |
43 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 44 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
45 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
46 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 47 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
48 | |
49 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
52 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
54 | #define OMAP2_MCSPI_SYST 0x24 | |
55 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 56 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
57 | |
58 | /* per-channel banks, 0x14 bytes each, first is: */ | |
59 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
60 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
61 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
62 | #define OMAP2_MCSPI_TX0 0x38 | |
63 | #define OMAP2_MCSPI_RX0 0x3c | |
64 | ||
65 | /* per-register bitmasks: */ | |
d33f473d | 66 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 67 | |
7a8fa725 JH |
68 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
69 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
70 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 71 | |
7a8fa725 JH |
72 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
73 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 75 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 76 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
78 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
81 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
83 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
84 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
85 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
86 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
87 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
88 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 89 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 90 | |
7a8fa725 JH |
91 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
92 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
93 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 94 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 95 | |
7a8fa725 | 96 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 97 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 98 | |
7a8fa725 | 99 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
100 | |
101 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
102 | struct omap2_mcspi_dma { | |
53741ed8 RK |
103 | struct dma_chan *dma_tx; |
104 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
105 | |
106 | int dma_tx_sync_dev; | |
107 | int dma_rx_sync_dev; | |
108 | ||
109 | struct completion dma_tx_completion; | |
110 | struct completion dma_rx_completion; | |
74f3aaad MP |
111 | |
112 | char dma_rx_ch_name[14]; | |
113 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
114 | }; |
115 | ||
116 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
117 | * cache operations; better heuristics consider wordsize and bitrate. | |
118 | */ | |
8b66c134 | 119 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
120 | |
121 | ||
1bd897f8 BC |
122 | /* |
123 | * Used for context save and restore, structure members to be updated whenever | |
124 | * corresponding registers are modified. | |
125 | */ | |
126 | struct omap2_mcspi_regs { | |
127 | u32 modulctrl; | |
128 | u32 wakeupenable; | |
129 | struct list_head cs; | |
130 | }; | |
131 | ||
ccdc7bf9 | 132 | struct omap2_mcspi { |
ccdc7bf9 | 133 | struct spi_master *master; |
ccdc7bf9 SO |
134 | /* Virtual base address of the controller */ |
135 | void __iomem *base; | |
e5480b73 | 136 | unsigned long phys; |
ccdc7bf9 SO |
137 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
138 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 139 | struct device *dev; |
1bd897f8 | 140 | struct omap2_mcspi_regs ctx; |
d33f473d | 141 | int fifo_depth; |
0384e90b | 142 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
143 | }; |
144 | ||
145 | struct omap2_mcspi_cs { | |
146 | void __iomem *base; | |
e5480b73 | 147 | unsigned long phys; |
ccdc7bf9 | 148 | int word_len; |
97ca0d6c | 149 | u16 mode; |
89c05372 | 150 | struct list_head node; |
a41ae1ad | 151 | /* Context save and restore shadow register */ |
faee9b05 | 152 | u32 chconf0, chctrl0; |
a41ae1ad H |
153 | }; |
154 | ||
ccdc7bf9 SO |
155 | static inline void mcspi_write_reg(struct spi_master *master, |
156 | int idx, u32 val) | |
157 | { | |
158 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
159 | ||
21b2ce5e | 160 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
161 | } |
162 | ||
163 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
164 | { | |
165 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
166 | ||
21b2ce5e | 167 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
168 | } |
169 | ||
170 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
171 | int idx, u32 val) | |
172 | { | |
173 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
174 | ||
21b2ce5e | 175 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
176 | } |
177 | ||
178 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
179 | { | |
180 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
181 | ||
21b2ce5e | 182 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
183 | } |
184 | ||
a41ae1ad H |
185 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
186 | { | |
187 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
188 | ||
189 | return cs->chconf0; | |
190 | } | |
191 | ||
192 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
193 | { | |
194 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
195 | ||
196 | cs->chconf0 = val; | |
197 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 198 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
199 | } |
200 | ||
56cd5c15 IS |
201 | static inline int mcspi_bytes_per_word(int word_len) |
202 | { | |
203 | if (word_len <= 8) | |
204 | return 1; | |
205 | else if (word_len <= 16) | |
206 | return 2; | |
207 | else /* word_len <= 32 */ | |
208 | return 4; | |
209 | } | |
210 | ||
ccdc7bf9 SO |
211 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
212 | int is_read, int enable) | |
213 | { | |
214 | u32 l, rw; | |
215 | ||
a41ae1ad | 216 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
217 | |
218 | if (is_read) /* 1 is read, 0 write */ | |
219 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
220 | else | |
221 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
222 | ||
af4e944d S |
223 | if (enable) |
224 | l |= rw; | |
225 | else | |
226 | l &= ~rw; | |
227 | ||
a41ae1ad | 228 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
229 | } |
230 | ||
231 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
232 | { | |
faee9b05 | 233 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
234 | u32 l; |
235 | ||
faee9b05 SS |
236 | l = cs->chctrl0; |
237 | if (enable) | |
238 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
239 | else | |
240 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
241 | cs->chctrl0 = l; | |
242 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
243 | /* Flash post-writes */ |
244 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
245 | } |
246 | ||
ddcad7e9 | 247 | static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) |
ccdc7bf9 | 248 | { |
5f74db10 | 249 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
ccdc7bf9 SO |
250 | u32 l; |
251 | ||
4373f8b6 MW |
252 | /* The controller handles the inverted chip selects |
253 | * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert | |
254 | * the inversion from the core spi_set_cs function. | |
255 | */ | |
256 | if (spi->mode & SPI_CS_HIGH) | |
257 | enable = !enable; | |
258 | ||
ddcad7e9 | 259 | if (spi->controller_state) { |
5f74db10 SR |
260 | int err = pm_runtime_get_sync(mcspi->dev); |
261 | if (err < 0) { | |
262 | dev_err(mcspi->dev, "failed to get sync: %d\n", err); | |
263 | return; | |
264 | } | |
265 | ||
ddcad7e9 | 266 | l = mcspi_cached_chconf0(spi); |
af4e944d | 267 | |
ddcad7e9 MW |
268 | if (enable) |
269 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
270 | else | |
271 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
272 | ||
273 | mcspi_write_chconf0(spi, l); | |
5f74db10 SR |
274 | |
275 | pm_runtime_mark_last_busy(mcspi->dev); | |
276 | pm_runtime_put_autosuspend(mcspi->dev); | |
ddcad7e9 | 277 | } |
ccdc7bf9 SO |
278 | } |
279 | ||
280 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
281 | { | |
1bd897f8 BC |
282 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
283 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
284 | u32 l; |
285 | ||
1bd897f8 BC |
286 | /* |
287 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
288 | * to single-channel master mode |
289 | */ | |
290 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
291 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
292 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 293 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 294 | |
1bd897f8 | 295 | ctx->modulctrl = l; |
a41ae1ad H |
296 | } |
297 | ||
d33f473d IS |
298 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
299 | struct spi_transfer *t, int enable) | |
300 | { | |
301 | struct spi_master *master = spi->master; | |
302 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
303 | struct omap2_mcspi *mcspi; | |
304 | unsigned int wcnt; | |
5db542ed | 305 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
306 | u32 chconf, xferlevel; |
307 | ||
308 | mcspi = spi_master_get_devdata(master); | |
309 | ||
310 | chconf = mcspi_cached_chconf0(spi); | |
311 | if (enable) { | |
312 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
313 | if (t->len % bytes_per_word != 0) | |
314 | goto disable_fifo; | |
315 | ||
5db542ed IS |
316 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
317 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
318 | else | |
319 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
320 | ||
321 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
322 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
323 | goto disable_fifo; | |
324 | ||
325 | wcnt = t->len / bytes_per_word; | |
326 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
327 | goto disable_fifo; | |
328 | ||
329 | xferlevel = wcnt << 16; | |
330 | if (t->rx_buf != NULL) { | |
331 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
332 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
333 | } |
334 | if (t->tx_buf != NULL) { | |
d33f473d IS |
335 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
336 | xferlevel |= fifo_depth - 1; | |
337 | } | |
338 | ||
339 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
340 | mcspi_write_chconf0(spi, chconf); | |
341 | mcspi->fifo_depth = fifo_depth; | |
342 | ||
343 | return; | |
344 | } | |
345 | ||
346 | disable_fifo: | |
347 | if (t->rx_buf != NULL) | |
348 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
349 | |
350 | if (t->tx_buf != NULL) | |
d33f473d IS |
351 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
352 | ||
353 | mcspi_write_chconf0(spi, chconf); | |
354 | mcspi->fifo_depth = 0; | |
355 | } | |
356 | ||
a41ae1ad H |
357 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
358 | { | |
1bd897f8 BC |
359 | struct spi_master *spi_cntrl = mcspi->master; |
360 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
361 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
362 | |
363 | /* McSPI: context restore */ | |
1bd897f8 BC |
364 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
365 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 366 | |
1bd897f8 | 367 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 368 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 369 | } |
ccdc7bf9 | 370 | |
2764c500 IK |
371 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
372 | { | |
373 | unsigned long timeout; | |
374 | ||
375 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 376 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 377 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 378 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
379 | return -ETIMEDOUT; |
380 | else | |
381 | return 0; | |
382 | } | |
2764c500 IK |
383 | cpu_relax(); |
384 | } | |
385 | return 0; | |
386 | } | |
387 | ||
53741ed8 RK |
388 | static void omap2_mcspi_rx_callback(void *data) |
389 | { | |
390 | struct spi_device *spi = data; | |
391 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
392 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
393 | ||
53741ed8 RK |
394 | /* We must disable the DMA RX request */ |
395 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
396 | |
397 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
398 | } |
399 | ||
400 | static void omap2_mcspi_tx_callback(void *data) | |
401 | { | |
402 | struct spi_device *spi = data; | |
403 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
404 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
405 | ||
53741ed8 RK |
406 | /* We must disable the DMA TX request */ |
407 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
408 | |
409 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
410 | } |
411 | ||
d7b4394e S |
412 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
413 | struct spi_transfer *xfer, | |
414 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
415 | { |
416 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 417 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 418 | unsigned int count; |
ccdc7bf9 SO |
419 | |
420 | mcspi = spi_master_get_devdata(spi->master); | |
421 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 422 | count = xfer->len; |
ccdc7bf9 | 423 | |
d7b4394e | 424 | if (mcspi_dma->dma_tx) { |
53741ed8 | 425 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
426 | |
427 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
428 | ||
3525e0aa AM |
429 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, |
430 | xfer->tx_sg.nents, DMA_MEM_TO_DEV, | |
431 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
432 | if (tx) { |
433 | tx->callback = omap2_mcspi_tx_callback; | |
434 | tx->callback_param = spi; | |
435 | dmaengine_submit(tx); | |
436 | } else { | |
437 | /* FIXME: fall back to PIO? */ | |
438 | } | |
439 | } | |
d7b4394e S |
440 | dma_async_issue_pending(mcspi_dma->dma_tx); |
441 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
442 | ||
d7b4394e | 443 | } |
53741ed8 | 444 | |
d7b4394e S |
445 | static unsigned |
446 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
447 | struct dma_slave_config cfg, | |
448 | unsigned es) | |
449 | { | |
450 | struct omap2_mcspi *mcspi; | |
451 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 452 | unsigned int count, dma_count; |
d7b4394e S |
453 | u32 l; |
454 | int elements = 0; | |
455 | int word_len, element_count; | |
456 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
457 | mcspi = spi_master_get_devdata(spi->master); | |
458 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
459 | count = xfer->len; | |
d33f473d IS |
460 | dma_count = xfer->len; |
461 | ||
462 | if (mcspi->fifo_depth == 0) | |
463 | dma_count -= es; | |
464 | ||
d7b4394e S |
465 | word_len = cs->word_len; |
466 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 467 | |
d7b4394e S |
468 | if (word_len <= 8) |
469 | element_count = count; | |
470 | else if (word_len <= 16) | |
471 | element_count = count >> 1; | |
472 | else /* word_len <= 32 */ | |
473 | element_count = count >> 2; | |
474 | ||
475 | if (mcspi_dma->dma_rx) { | |
53741ed8 | 476 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
477 | |
478 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
479 | ||
d33f473d IS |
480 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
481 | dma_count -= es; | |
53741ed8 | 482 | |
3525e0aa AM |
483 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, xfer->rx_sg.sgl, |
484 | xfer->rx_sg.nents, DMA_DEV_TO_MEM, | |
485 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
486 | if (tx) { |
487 | tx->callback = omap2_mcspi_rx_callback; | |
488 | tx->callback_param = spi; | |
489 | dmaengine_submit(tx); | |
490 | } else { | |
d7b4394e | 491 | /* FIXME: fall back to PIO? */ |
2764c500 | 492 | } |
ccdc7bf9 SO |
493 | } |
494 | ||
d7b4394e S |
495 | dma_async_issue_pending(mcspi_dma->dma_rx); |
496 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 497 | |
d7b4394e | 498 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
d33f473d IS |
499 | |
500 | if (mcspi->fifo_depth > 0) | |
501 | return count; | |
502 | ||
d7b4394e | 503 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 504 | |
d7b4394e | 505 | elements = element_count - 1; |
4743a0f8 | 506 | |
d7b4394e S |
507 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
508 | elements--; | |
4743a0f8 | 509 | |
57c5c28d | 510 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 511 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
512 | u32 w; |
513 | ||
514 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
515 | if (word_len <= 8) | |
d7b4394e | 516 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 517 | else if (word_len <= 16) |
d7b4394e | 518 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 519 | else /* word_len <= 32 */ |
d7b4394e | 520 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 521 | } else { |
56cd5c15 | 522 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 523 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 524 | count -= (bytes_per_word << 1); |
d7b4394e S |
525 | omap2_mcspi_set_enable(spi, 1); |
526 | return count; | |
57c5c28d | 527 | } |
ccdc7bf9 | 528 | } |
d7b4394e S |
529 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
530 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
531 | u32 w; | |
532 | ||
533 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
534 | if (word_len <= 8) | |
535 | ((u8 *)xfer->rx_buf)[elements] = w; | |
536 | else if (word_len <= 16) | |
537 | ((u16 *)xfer->rx_buf)[elements] = w; | |
538 | else /* word_len <= 32 */ | |
539 | ((u32 *)xfer->rx_buf)[elements] = w; | |
540 | } else { | |
a1829d2b | 541 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 542 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
543 | } |
544 | omap2_mcspi_set_enable(spi, 1); | |
545 | return count; | |
546 | } | |
547 | ||
548 | static unsigned | |
549 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
550 | { | |
551 | struct omap2_mcspi *mcspi; | |
552 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
553 | struct omap2_mcspi_dma *mcspi_dma; | |
554 | unsigned int count; | |
555 | u32 l; | |
556 | u8 *rx; | |
557 | const u8 *tx; | |
558 | struct dma_slave_config cfg; | |
559 | enum dma_slave_buswidth width; | |
560 | unsigned es; | |
d33f473d | 561 | u32 burst; |
e47a682a | 562 | void __iomem *chstat_reg; |
d33f473d IS |
563 | void __iomem *irqstat_reg; |
564 | int wait_res; | |
d7b4394e S |
565 | |
566 | mcspi = spi_master_get_devdata(spi->master); | |
567 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
568 | l = mcspi_cached_chconf0(spi); | |
569 | ||
570 | ||
571 | if (cs->word_len <= 8) { | |
572 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
573 | es = 1; | |
574 | } else if (cs->word_len <= 16) { | |
575 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
576 | es = 2; | |
577 | } else { | |
578 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
579 | es = 4; | |
580 | } | |
581 | ||
d33f473d IS |
582 | count = xfer->len; |
583 | burst = 1; | |
584 | ||
585 | if (mcspi->fifo_depth > 0) { | |
586 | if (count > mcspi->fifo_depth) | |
587 | burst = mcspi->fifo_depth / es; | |
588 | else | |
589 | burst = count / es; | |
590 | } | |
591 | ||
d7b4394e S |
592 | memset(&cfg, 0, sizeof(cfg)); |
593 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
594 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
595 | cfg.src_addr_width = width; | |
596 | cfg.dst_addr_width = width; | |
d33f473d IS |
597 | cfg.src_maxburst = burst; |
598 | cfg.dst_maxburst = burst; | |
d7b4394e S |
599 | |
600 | rx = xfer->rx_buf; | |
601 | tx = xfer->tx_buf; | |
602 | ||
d7b4394e S |
603 | if (tx != NULL) |
604 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
605 | ||
606 | if (rx != NULL) | |
e47a682a S |
607 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
608 | ||
609 | if (tx != NULL) { | |
e47a682a | 610 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
e47a682a | 611 | |
d33f473d IS |
612 | if (mcspi->fifo_depth > 0) { |
613 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
614 | ||
615 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
616 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
617 | dev_err(&spi->dev, "EOW timed out\n"); | |
618 | ||
619 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
620 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
621 | } | |
622 | ||
e47a682a S |
623 | /* for TX_ONLY mode, be sure all words have shifted out */ |
624 | if (rx == NULL) { | |
d33f473d IS |
625 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
626 | if (mcspi->fifo_depth > 0) { | |
627 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
628 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
629 | if (wait_res < 0) | |
630 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
631 | } else { | |
632 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
633 | OMAP2_MCSPI_CHSTAT_TXS); | |
634 | if (wait_res < 0) | |
635 | dev_err(&spi->dev, "TXS timed out\n"); | |
636 | } | |
637 | if (wait_res >= 0 && | |
638 | (mcspi_wait_for_reg_bit(chstat_reg, | |
639 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
640 | dev_err(&spi->dev, "EOT timed out\n"); |
641 | } | |
642 | } | |
ccdc7bf9 SO |
643 | return count; |
644 | } | |
645 | ||
ccdc7bf9 SO |
646 | static unsigned |
647 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
648 | { | |
649 | struct omap2_mcspi *mcspi; | |
650 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
651 | unsigned int count, c; | |
652 | u32 l; | |
653 | void __iomem *base = cs->base; | |
654 | void __iomem *tx_reg; | |
655 | void __iomem *rx_reg; | |
656 | void __iomem *chstat_reg; | |
657 | int word_len; | |
658 | ||
659 | mcspi = spi_master_get_devdata(spi->master); | |
660 | count = xfer->len; | |
661 | c = count; | |
662 | word_len = cs->word_len; | |
663 | ||
a41ae1ad | 664 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
665 | |
666 | /* We store the pre-calculated register addresses on stack to speed | |
667 | * up the transfer loop. */ | |
668 | tx_reg = base + OMAP2_MCSPI_TX0; | |
669 | rx_reg = base + OMAP2_MCSPI_RX0; | |
670 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
671 | ||
adef658d MJ |
672 | if (c < (word_len>>3)) |
673 | return 0; | |
674 | ||
ccdc7bf9 SO |
675 | if (word_len <= 8) { |
676 | u8 *rx; | |
677 | const u8 *tx; | |
678 | ||
679 | rx = xfer->rx_buf; | |
680 | tx = xfer->tx_buf; | |
681 | ||
682 | do { | |
feed9bab | 683 | c -= 1; |
ccdc7bf9 SO |
684 | if (tx != NULL) { |
685 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
686 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
687 | dev_err(&spi->dev, "TXS timed out\n"); | |
688 | goto out; | |
689 | } | |
079a176d | 690 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 691 | word_len, *tx); |
21b2ce5e | 692 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
693 | } |
694 | if (rx != NULL) { | |
695 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
696 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
697 | dev_err(&spi->dev, "RXS timed out\n"); | |
698 | goto out; | |
699 | } | |
4743a0f8 RT |
700 | |
701 | if (c == 1 && tx == NULL && | |
702 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
703 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 704 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 705 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 706 | word_len, *(rx - 1)); |
4743a0f8 RT |
707 | if (mcspi_wait_for_reg_bit(chstat_reg, |
708 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
709 | dev_err(&spi->dev, | |
710 | "RXS timed out\n"); | |
711 | goto out; | |
712 | } | |
713 | c = 0; | |
714 | } else if (c == 0 && tx == NULL) { | |
715 | omap2_mcspi_set_enable(spi, 0); | |
716 | } | |
717 | ||
21b2ce5e | 718 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 719 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 720 | word_len, *(rx - 1)); |
ccdc7bf9 | 721 | } |
95c5c3ab | 722 | } while (c); |
ccdc7bf9 SO |
723 | } else if (word_len <= 16) { |
724 | u16 *rx; | |
725 | const u16 *tx; | |
726 | ||
727 | rx = xfer->rx_buf; | |
728 | tx = xfer->tx_buf; | |
729 | do { | |
feed9bab | 730 | c -= 2; |
ccdc7bf9 SO |
731 | if (tx != NULL) { |
732 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
733 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
734 | dev_err(&spi->dev, "TXS timed out\n"); | |
735 | goto out; | |
736 | } | |
079a176d | 737 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 738 | word_len, *tx); |
21b2ce5e | 739 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
740 | } |
741 | if (rx != NULL) { | |
742 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
743 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
744 | dev_err(&spi->dev, "RXS timed out\n"); | |
745 | goto out; | |
746 | } | |
4743a0f8 RT |
747 | |
748 | if (c == 2 && tx == NULL && | |
749 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
750 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 751 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 752 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 753 | word_len, *(rx - 1)); |
4743a0f8 RT |
754 | if (mcspi_wait_for_reg_bit(chstat_reg, |
755 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
756 | dev_err(&spi->dev, | |
757 | "RXS timed out\n"); | |
758 | goto out; | |
759 | } | |
760 | c = 0; | |
761 | } else if (c == 0 && tx == NULL) { | |
762 | omap2_mcspi_set_enable(spi, 0); | |
763 | } | |
764 | ||
21b2ce5e | 765 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 766 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 767 | word_len, *(rx - 1)); |
ccdc7bf9 | 768 | } |
95c5c3ab | 769 | } while (c >= 2); |
ccdc7bf9 SO |
770 | } else if (word_len <= 32) { |
771 | u32 *rx; | |
772 | const u32 *tx; | |
773 | ||
774 | rx = xfer->rx_buf; | |
775 | tx = xfer->tx_buf; | |
776 | do { | |
feed9bab | 777 | c -= 4; |
ccdc7bf9 SO |
778 | if (tx != NULL) { |
779 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
780 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
781 | dev_err(&spi->dev, "TXS timed out\n"); | |
782 | goto out; | |
783 | } | |
079a176d | 784 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 785 | word_len, *tx); |
21b2ce5e | 786 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
787 | } |
788 | if (rx != NULL) { | |
789 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
790 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
791 | dev_err(&spi->dev, "RXS timed out\n"); | |
792 | goto out; | |
793 | } | |
4743a0f8 RT |
794 | |
795 | if (c == 4 && tx == NULL && | |
796 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
797 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 798 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 799 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 800 | word_len, *(rx - 1)); |
4743a0f8 RT |
801 | if (mcspi_wait_for_reg_bit(chstat_reg, |
802 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
803 | dev_err(&spi->dev, | |
804 | "RXS timed out\n"); | |
805 | goto out; | |
806 | } | |
807 | c = 0; | |
808 | } else if (c == 0 && tx == NULL) { | |
809 | omap2_mcspi_set_enable(spi, 0); | |
810 | } | |
811 | ||
21b2ce5e | 812 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 813 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 814 | word_len, *(rx - 1)); |
ccdc7bf9 | 815 | } |
95c5c3ab | 816 | } while (c >= 4); |
ccdc7bf9 SO |
817 | } |
818 | ||
819 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
820 | if (xfer->rx_buf == NULL) { | |
821 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
822 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
823 | dev_err(&spi->dev, "TXS timed out\n"); | |
824 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
825 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
826 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
827 | |
828 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
829 | * otherwise these rx datas will affect the direct following | |
830 | * RX_ONLY transfer. | |
831 | */ | |
832 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
833 | } |
834 | out: | |
4743a0f8 | 835 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
836 | return count - c; |
837 | } | |
838 | ||
57d9c10d HH |
839 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
840 | { | |
841 | u32 div; | |
842 | ||
843 | for (div = 0; div < 15; div++) | |
844 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
845 | return div; | |
846 | ||
847 | return 15; | |
848 | } | |
849 | ||
ccdc7bf9 SO |
850 | /* called only when no transfer is active to this device */ |
851 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
852 | struct spi_transfer *t) | |
853 | { | |
854 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
855 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 856 | struct spi_master *spi_cntrl; |
faee9b05 | 857 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 858 | u8 word_len = spi->bits_per_word; |
9bd4517d | 859 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
860 | |
861 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 862 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
863 | |
864 | if (t != NULL && t->bits_per_word) | |
865 | word_len = t->bits_per_word; | |
866 | ||
867 | cs->word_len = word_len; | |
868 | ||
9bd4517d SE |
869 | if (t && t->speed_hz) |
870 | speed_hz = t->speed_hz; | |
871 | ||
57d9c10d | 872 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
873 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
874 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
875 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
876 | clkg = 0; | |
877 | } else { | |
878 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
879 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
880 | clkd = (div - 1) & 0xf; | |
881 | extclk = (div - 1) >> 4; | |
882 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
883 | } | |
ccdc7bf9 | 884 | |
a41ae1ad | 885 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
886 | |
887 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
888 | * REVISIT: this controller could support SPI_3WIRE mode. | |
889 | */ | |
2cd45179 | 890 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
891 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
892 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
893 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
894 | } else { | |
895 | l |= OMAP2_MCSPI_CHCONF_IS; | |
896 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
897 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
898 | } | |
ccdc7bf9 SO |
899 | |
900 | /* wordlength */ | |
901 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
902 | l |= (word_len - 1) << 7; | |
903 | ||
904 | /* set chipselect polarity; manage with FORCE */ | |
905 | if (!(spi->mode & SPI_CS_HIGH)) | |
906 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
907 | else | |
908 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
909 | ||
910 | /* set clock divisor */ | |
911 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
912 | l |= clkd << 2; |
913 | ||
914 | /* set clock granularity */ | |
915 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
916 | l |= clkg; | |
917 | if (clkg) { | |
918 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
919 | cs->chctrl0 |= extclk << 8; | |
920 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
921 | } | |
ccdc7bf9 SO |
922 | |
923 | /* set SPI mode 0..3 */ | |
924 | if (spi->mode & SPI_CPOL) | |
925 | l |= OMAP2_MCSPI_CHCONF_POL; | |
926 | else | |
927 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
928 | if (spi->mode & SPI_CPHA) | |
929 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
930 | else | |
931 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
932 | ||
a41ae1ad | 933 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 934 | |
97ca0d6c MG |
935 | cs->mode = spi->mode; |
936 | ||
ccdc7bf9 | 937 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 938 | speed_hz, |
ccdc7bf9 SO |
939 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
940 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
ddc5cdf1 TL |
945 | /* |
946 | * Note that we currently allow DMA only if we get a channel | |
947 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
948 | */ | |
ccdc7bf9 SO |
949 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
950 | { | |
951 | struct spi_master *master = spi->master; | |
952 | struct omap2_mcspi *mcspi; | |
953 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
954 | dma_cap_mask_t mask; |
955 | unsigned sig; | |
ccdc7bf9 SO |
956 | |
957 | mcspi = spi_master_get_devdata(master); | |
958 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
959 | ||
53741ed8 RK |
960 | init_completion(&mcspi_dma->dma_rx_completion); |
961 | init_completion(&mcspi_dma->dma_tx_completion); | |
962 | ||
963 | dma_cap_zero(mask); | |
964 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 965 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
966 | |
967 | mcspi_dma->dma_rx = | |
968 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
969 | &sig, &master->dev, | |
970 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
971 | if (!mcspi_dma->dma_rx) |
972 | goto no_dma; | |
ccdc7bf9 | 973 | |
53741ed8 | 974 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
975 | mcspi_dma->dma_tx = |
976 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
977 | &sig, &master->dev, | |
978 | mcspi_dma->dma_tx_ch_name); | |
979 | ||
53741ed8 | 980 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
981 | dma_release_channel(mcspi_dma->dma_rx); |
982 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 983 | goto no_dma; |
ccdc7bf9 SO |
984 | } |
985 | ||
ccdc7bf9 | 986 | return 0; |
ddc5cdf1 TL |
987 | |
988 | no_dma: | |
989 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
990 | return -EAGAIN; | |
ccdc7bf9 SO |
991 | } |
992 | ||
ccdc7bf9 SO |
993 | static int omap2_mcspi_setup(struct spi_device *spi) |
994 | { | |
995 | int ret; | |
1bd897f8 BC |
996 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
997 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
998 | struct omap2_mcspi_dma *mcspi_dma; |
999 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
1000 | ||
ccdc7bf9 SO |
1001 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
1002 | ||
1003 | if (!cs) { | |
10aa5a35 | 1004 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
1005 | if (!cs) |
1006 | return -ENOMEM; | |
1007 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1008 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1009 | cs->mode = 0; |
a41ae1ad | 1010 | cs->chconf0 = 0; |
faee9b05 | 1011 | cs->chctrl0 = 0; |
ccdc7bf9 | 1012 | spi->controller_state = cs; |
89c05372 | 1013 | /* Link this to context save list */ |
1bd897f8 | 1014 | list_add_tail(&cs->node, &ctx->cs); |
2f538c01 MW |
1015 | |
1016 | if (gpio_is_valid(spi->cs_gpio)) { | |
1017 | ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); | |
1018 | if (ret) { | |
1019 | dev_err(&spi->dev, "failed to request gpio\n"); | |
1020 | return ret; | |
1021 | } | |
1022 | gpio_direction_output(spi->cs_gpio, | |
1023 | !(spi->mode & SPI_CS_HIGH)); | |
1024 | } | |
ccdc7bf9 SO |
1025 | } |
1026 | ||
8c7494a5 | 1027 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1028 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1029 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1030 | return ret; |
1031 | } | |
1032 | ||
034d3dc9 | 1033 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1034 | if (ret < 0) |
1035 | return ret; | |
a41ae1ad | 1036 | |
86eeb6fe | 1037 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1038 | pm_runtime_mark_last_busy(mcspi->dev); |
1039 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1040 | |
1041 | return ret; | |
1042 | } | |
1043 | ||
1044 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1045 | { | |
1046 | struct omap2_mcspi *mcspi; | |
1047 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1048 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1049 | |
1050 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1051 | |
5e774943 SE |
1052 | if (spi->controller_state) { |
1053 | /* Unlink controller state from context save list */ | |
1054 | cs = spi->controller_state; | |
1055 | list_del(&cs->node); | |
89c05372 | 1056 | |
10aa5a35 | 1057 | kfree(cs); |
5e774943 | 1058 | } |
ccdc7bf9 | 1059 | |
99f1a43f SE |
1060 | if (spi->chip_select < spi->master->num_chipselect) { |
1061 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1062 | ||
53741ed8 RK |
1063 | if (mcspi_dma->dma_rx) { |
1064 | dma_release_channel(mcspi_dma->dma_rx); | |
1065 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1066 | } |
53741ed8 RK |
1067 | if (mcspi_dma->dma_tx) { |
1068 | dma_release_channel(mcspi_dma->dma_tx); | |
1069 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1070 | } |
ccdc7bf9 | 1071 | } |
bc7f9bbc MW |
1072 | |
1073 | if (gpio_is_valid(spi->cs_gpio)) | |
1074 | gpio_free(spi->cs_gpio); | |
ccdc7bf9 SO |
1075 | } |
1076 | ||
3525e0aa AM |
1077 | static bool omap2_mcspi_can_dma(struct spi_master *master, |
1078 | struct spi_device *spi, | |
1079 | struct spi_transfer *xfer) | |
1080 | { | |
1081 | if (xfer->len < DMA_MIN_BYTES) | |
1082 | return false; | |
1083 | ||
1084 | return true; | |
1085 | } | |
1086 | ||
b28cb941 MW |
1087 | static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, |
1088 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 | 1089 | { |
ccdc7bf9 SO |
1090 | |
1091 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1092 | * -- although this controller would gladly |
ccdc7bf9 SO |
1093 | * arbitrate among multiple channels. This corresponds to "single |
1094 | * channel" master mode. As a side effect, we need to manage the | |
1095 | * chipselect with the FORCE bit ... CS != channel enable. | |
1096 | */ | |
ccdc7bf9 | 1097 | |
5cbc7ca9 | 1098 | struct spi_master *master; |
ddc5cdf1 | 1099 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1100 | struct omap2_mcspi_cs *cs; |
1101 | struct omap2_mcspi_device_config *cd; | |
1102 | int par_override = 0; | |
1103 | int status = 0; | |
1104 | u32 chconf; | |
ccdc7bf9 | 1105 | |
5cbc7ca9 | 1106 | master = spi->master; |
ddc5cdf1 | 1107 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1108 | cs = spi->controller_state; |
1109 | cd = spi->controller_data; | |
ccdc7bf9 | 1110 | |
97ca0d6c MG |
1111 | /* |
1112 | * The slave driver could have changed spi->mode in which case | |
1113 | * it will be different from cs->mode (the current hardware setup). | |
1114 | * If so, set par_override (even though its not a parity issue) so | |
1115 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1116 | * with the correct mode on the first iteration of the loop below. | |
1117 | */ | |
1118 | if (spi->mode != cs->mode) | |
1119 | par_override = 1; | |
1120 | ||
d33f473d | 1121 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 1122 | |
a06b430f MW |
1123 | if (gpio_is_valid(spi->cs_gpio)) |
1124 | omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); | |
1125 | ||
b28cb941 MW |
1126 | if (par_override || |
1127 | (t->speed_hz != spi->max_speed_hz) || | |
1128 | (t->bits_per_word != spi->bits_per_word)) { | |
1129 | par_override = 1; | |
1130 | status = omap2_mcspi_setup_transfer(spi, t); | |
1131 | if (status < 0) | |
1132 | goto out; | |
1133 | if (t->speed_hz == spi->max_speed_hz && | |
1134 | t->bits_per_word == spi->bits_per_word) | |
1135 | par_override = 0; | |
1136 | } | |
1137 | if (cd && cd->cs_per_word) { | |
1138 | chconf = mcspi->ctx.modulctrl; | |
1139 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1140 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1141 | mcspi->ctx.modulctrl = | |
1142 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1143 | } | |
4743a0f8 | 1144 | |
b28cb941 MW |
1145 | chconf = mcspi_cached_chconf0(spi); |
1146 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1147 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
1148 | ||
1149 | if (t->tx_buf == NULL) | |
1150 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1151 | else if (t->rx_buf == NULL) | |
1152 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
1153 | ||
1154 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
1155 | /* Turbo mode is for more than one word */ | |
1156 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1157 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1158 | } | |
ccdc7bf9 | 1159 | |
b28cb941 | 1160 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1161 | |
b28cb941 MW |
1162 | if (t->len) { |
1163 | unsigned count; | |
5fda88f5 | 1164 | |
b28cb941 MW |
1165 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1166 | (t->len >= DMA_MIN_BYTES)) | |
1167 | omap2_mcspi_set_fifo(spi, t, 1); | |
d33f473d | 1168 | |
b28cb941 | 1169 | omap2_mcspi_set_enable(spi, 1); |
d33f473d | 1170 | |
b28cb941 MW |
1171 | /* RX_ONLY mode needs dummy data in TX reg */ |
1172 | if (t->tx_buf == NULL) | |
1173 | writel_relaxed(0, cs->base | |
1174 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1175 | |
b28cb941 MW |
1176 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1177 | (t->len >= DMA_MIN_BYTES)) | |
1178 | count = omap2_mcspi_txrx_dma(spi, t); | |
1179 | else | |
1180 | count = omap2_mcspi_txrx_pio(spi, t); | |
ccdc7bf9 | 1181 | |
b28cb941 MW |
1182 | if (count != t->len) { |
1183 | status = -EIO; | |
1184 | goto out; | |
ccdc7bf9 | 1185 | } |
b28cb941 | 1186 | } |
ccdc7bf9 | 1187 | |
b28cb941 | 1188 | omap2_mcspi_set_enable(spi, 0); |
d33f473d | 1189 | |
b28cb941 MW |
1190 | if (mcspi->fifo_depth > 0) |
1191 | omap2_mcspi_set_fifo(spi, t, 0); | |
1192 | ||
1193 | out: | |
5fda88f5 S |
1194 | /* Restore defaults if they were overriden */ |
1195 | if (par_override) { | |
1196 | par_override = 0; | |
1197 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1198 | } | |
ccdc7bf9 | 1199 | |
5cbc7ca9 MB |
1200 | if (cd && cd->cs_per_word) { |
1201 | chconf = mcspi->ctx.modulctrl; | |
1202 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1203 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1204 | mcspi->ctx.modulctrl = | |
1205 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1206 | } | |
1207 | ||
5fda88f5 | 1208 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1209 | |
a06b430f MW |
1210 | if (gpio_is_valid(spi->cs_gpio)) |
1211 | omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); | |
1212 | ||
d33f473d IS |
1213 | if (mcspi->fifo_depth > 0 && t) |
1214 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1215 | |
b28cb941 | 1216 | return status; |
ccdc7bf9 SO |
1217 | } |
1218 | ||
468a3208 NA |
1219 | static int omap2_mcspi_prepare_message(struct spi_master *master, |
1220 | struct spi_message *msg) | |
1221 | { | |
1222 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1223 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
1224 | struct omap2_mcspi_cs *cs; | |
1225 | ||
1226 | /* Only a single channel can have the FORCE bit enabled | |
1227 | * in its chconf0 register. | |
1228 | * Scan all channels and disable them except the current one. | |
1229 | * A FORCE can remain from a last transfer having cs_change enabled | |
1230 | */ | |
1231 | list_for_each_entry(cs, &ctx->cs, node) { | |
1232 | if (msg->spi->controller_state == cs) | |
1233 | continue; | |
1234 | ||
1235 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { | |
1236 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
1237 | writel_relaxed(cs->chconf0, | |
1238 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1239 | readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
b28cb941 MW |
1246 | static int omap2_mcspi_transfer_one(struct spi_master *master, |
1247 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 SO |
1248 | { |
1249 | struct omap2_mcspi *mcspi; | |
ddc5cdf1 | 1250 | struct omap2_mcspi_dma *mcspi_dma; |
b28cb941 MW |
1251 | const void *tx_buf = t->tx_buf; |
1252 | void *rx_buf = t->rx_buf; | |
1253 | unsigned len = t->len; | |
ccdc7bf9 | 1254 | |
5fda88f5 | 1255 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1256 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 | 1257 | |
b28cb941 MW |
1258 | if ((len && !(rx_buf || tx_buf))) { |
1259 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | |
1260 | t->speed_hz, | |
1261 | len, | |
1262 | tx_buf ? "tx" : "", | |
1263 | rx_buf ? "rx" : "", | |
1264 | t->bits_per_word); | |
1265 | return -EINVAL; | |
1266 | } | |
1267 | ||
b28cb941 | 1268 | return omap2_mcspi_work_one(mcspi, spi, t); |
ccdc7bf9 SO |
1269 | } |
1270 | ||
fd4a319b | 1271 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1272 | { |
1273 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1274 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1275 | int ret = 0; |
ccdc7bf9 | 1276 | |
034d3dc9 | 1277 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1278 | if (ret < 0) |
1279 | return ret; | |
ddb22195 | 1280 | |
39f8052d | 1281 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1282 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1283 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1284 | |
1285 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1286 | pm_runtime_mark_last_busy(mcspi->dev); |
1287 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1288 | return 0; |
1289 | } | |
1290 | ||
1f1a4384 G |
1291 | static int omap_mcspi_runtime_resume(struct device *dev) |
1292 | { | |
1293 | struct omap2_mcspi *mcspi; | |
1294 | struct spi_master *master; | |
1295 | ||
1296 | master = dev_get_drvdata(dev); | |
1297 | mcspi = spi_master_get_devdata(master); | |
1298 | omap2_mcspi_restore_ctx(mcspi); | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
d5a80031 BC |
1303 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1304 | .regs_offset = 0, | |
1305 | }; | |
1306 | ||
1307 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1308 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1309 | }; | |
1310 | ||
1311 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1312 | { | |
1313 | .compatible = "ti,omap2-mcspi", | |
1314 | .data = &omap2_pdata, | |
1315 | }, | |
1316 | { | |
1317 | .compatible = "ti,omap4-mcspi", | |
1318 | .data = &omap4_pdata, | |
1319 | }, | |
1320 | { }, | |
1321 | }; | |
1322 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1323 | |
fd4a319b | 1324 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1325 | { |
1326 | struct spi_master *master; | |
83a01e72 | 1327 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1328 | struct omap2_mcspi *mcspi; |
1329 | struct resource *r; | |
1330 | int status = 0, i; | |
d5a80031 BC |
1331 | u32 regs_offset = 0; |
1332 | static int bus_num = 1; | |
1333 | struct device_node *node = pdev->dev.of_node; | |
1334 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1335 | |
1336 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1337 | if (master == NULL) { | |
1338 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1339 | return -ENOMEM; | |
1340 | } | |
1341 | ||
e7db06b5 DB |
1342 | /* the spi->mode bits understood by this driver: */ |
1343 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1344 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1345 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1346 | master->auto_runtime_pm = true; |
468a3208 | 1347 | master->prepare_message = omap2_mcspi_prepare_message; |
b28cb941 | 1348 | master->transfer_one = omap2_mcspi_transfer_one; |
ddcad7e9 | 1349 | master->set_cs = omap2_mcspi_set_cs; |
ccdc7bf9 | 1350 | master->cleanup = omap2_mcspi_cleanup; |
3525e0aa | 1351 | master->can_dma = omap2_mcspi_can_dma; |
d5a80031 | 1352 | master->dev.of_node = node; |
aca0924b AL |
1353 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1354 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1355 | |
24b5a82c | 1356 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1357 | |
1358 | mcspi = spi_master_get_devdata(master); | |
1359 | mcspi->master = master; | |
1360 | ||
d5a80031 BC |
1361 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1362 | if (match) { | |
1363 | u32 num_cs = 1; /* default number of chipselect */ | |
1364 | pdata = match->data; | |
1365 | ||
1366 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1367 | master->num_chipselect = num_cs; | |
1368 | master->bus_num = bus_num++; | |
2cd45179 DM |
1369 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1370 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1371 | } else { |
8074cf06 | 1372 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1373 | master->num_chipselect = pdata->num_cs; |
1374 | if (pdev->id != -1) | |
1375 | master->bus_num = pdev->id; | |
0384e90b | 1376 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1377 | } |
1378 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1379 | |
ccdc7bf9 SO |
1380 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1381 | if (r == NULL) { | |
1382 | status = -ENODEV; | |
39f1b565 | 1383 | goto free_master; |
ccdc7bf9 | 1384 | } |
1458d160 | 1385 | |
d5a80031 BC |
1386 | r->start += regs_offset; |
1387 | r->end += regs_offset; | |
1458d160 | 1388 | mcspi->phys = r->start; |
ccdc7bf9 | 1389 | |
b0ee5605 TR |
1390 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1391 | if (IS_ERR(mcspi->base)) { | |
1392 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1393 | goto free_master; |
55c381e4 | 1394 | } |
ccdc7bf9 | 1395 | |
1f1a4384 | 1396 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1397 | |
1bd897f8 | 1398 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1399 | |
a6f936db AL |
1400 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1401 | sizeof(struct omap2_mcspi_dma), | |
1402 | GFP_KERNEL); | |
1403 | if (mcspi->dma_channels == NULL) { | |
1404 | status = -ENOMEM; | |
1a77b127 | 1405 | goto free_master; |
a6f936db | 1406 | } |
ccdc7bf9 | 1407 | |
1a5d8190 | 1408 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1409 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1410 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1411 | struct resource *dma_res; |
1412 | ||
74f3aaad MP |
1413 | sprintf(dma_rx_ch_name, "rx%d", i); |
1414 | if (!pdev->dev.of_node) { | |
1415 | dma_res = | |
1416 | platform_get_resource_byname(pdev, | |
1417 | IORESOURCE_DMA, | |
1418 | dma_rx_ch_name); | |
1419 | if (!dma_res) { | |
1420 | dev_dbg(&pdev->dev, | |
1421 | "cannot get DMA RX channel\n"); | |
1422 | status = -ENODEV; | |
1423 | break; | |
1424 | } | |
1a5d8190 | 1425 | |
74f3aaad MP |
1426 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1427 | dma_res->start; | |
1a5d8190 | 1428 | } |
74f3aaad MP |
1429 | sprintf(dma_tx_ch_name, "tx%d", i); |
1430 | if (!pdev->dev.of_node) { | |
1431 | dma_res = | |
1432 | platform_get_resource_byname(pdev, | |
1433 | IORESOURCE_DMA, | |
1434 | dma_tx_ch_name); | |
1435 | if (!dma_res) { | |
1436 | dev_dbg(&pdev->dev, | |
1437 | "cannot get DMA TX channel\n"); | |
1438 | status = -ENODEV; | |
1439 | break; | |
1440 | } | |
1a5d8190 | 1441 | |
74f3aaad MP |
1442 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1443 | dma_res->start; | |
1444 | } | |
ccdc7bf9 SO |
1445 | } |
1446 | ||
39f1b565 | 1447 | if (status < 0) |
a6f936db | 1448 | goto free_master; |
39f1b565 | 1449 | |
27b5284c S |
1450 | pm_runtime_use_autosuspend(&pdev->dev); |
1451 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1452 | pm_runtime_enable(&pdev->dev); |
1453 | ||
142e07be WY |
1454 | status = omap2_mcspi_master_setup(mcspi); |
1455 | if (status < 0) | |
39f1b565 | 1456 | goto disable_pm; |
ccdc7bf9 | 1457 | |
b95e02b7 | 1458 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1459 | if (status < 0) |
37a2d84a | 1460 | goto disable_pm; |
ccdc7bf9 SO |
1461 | |
1462 | return status; | |
1463 | ||
39f1b565 | 1464 | disable_pm: |
0e6f357a TL |
1465 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1466 | pm_runtime_put_sync(&pdev->dev); | |
751c925c | 1467 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1468 | free_master: |
37a2d84a | 1469 | spi_master_put(master); |
ccdc7bf9 SO |
1470 | return status; |
1471 | } | |
1472 | ||
fd4a319b | 1473 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1474 | { |
a6f936db AL |
1475 | struct spi_master *master = platform_get_drvdata(pdev); |
1476 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1477 | |
0e6f357a | 1478 | pm_runtime_dont_use_autosuspend(mcspi->dev); |
a93a2029 | 1479 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1480 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1481 | |
ccdc7bf9 SO |
1482 | return 0; |
1483 | } | |
1484 | ||
7e38c3c4 KS |
1485 | /* work with hotplug and coldplug */ |
1486 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1487 | ||
42ce7fd6 GC |
1488 | #ifdef CONFIG_SUSPEND |
1489 | /* | |
1490 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1491 | * unactive state when driver was suspend, then force it to unactive state at | |
1492 | * wake up. | |
1493 | */ | |
1494 | static int omap2_mcspi_resume(struct device *dev) | |
1495 | { | |
1496 | struct spi_master *master = dev_get_drvdata(dev); | |
1497 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1498 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1499 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1500 | |
034d3dc9 | 1501 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1502 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1503 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1504 | /* |
1505 | * We need to toggle CS state for OMAP take this | |
1506 | * change in account. | |
1507 | */ | |
af4e944d | 1508 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1509 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1510 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1511 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1512 | } |
1513 | } | |
034d3dc9 S |
1514 | pm_runtime_mark_last_busy(mcspi->dev); |
1515 | pm_runtime_put_autosuspend(mcspi->dev); | |
beca3655 PH |
1516 | |
1517 | return pinctrl_pm_select_default_state(dev); | |
1518 | } | |
1519 | ||
1520 | static int omap2_mcspi_suspend(struct device *dev) | |
1521 | { | |
1522 | return pinctrl_pm_select_sleep_state(dev); | |
42ce7fd6 | 1523 | } |
beca3655 | 1524 | |
42ce7fd6 | 1525 | #else |
beca3655 | 1526 | #define omap2_mcspi_suspend NULL |
42ce7fd6 GC |
1527 | #define omap2_mcspi_resume NULL |
1528 | #endif | |
1529 | ||
1530 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1531 | .resume = omap2_mcspi_resume, | |
beca3655 | 1532 | .suspend = omap2_mcspi_suspend, |
1f1a4384 | 1533 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1534 | }; |
1535 | ||
ccdc7bf9 SO |
1536 | static struct platform_driver omap2_mcspi_driver = { |
1537 | .driver = { | |
1538 | .name = "omap2_mcspi", | |
d5a80031 BC |
1539 | .pm = &omap2_mcspi_pm_ops, |
1540 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1541 | }, |
7d6b6d83 | 1542 | .probe = omap2_mcspi_probe, |
fd4a319b | 1543 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1544 | }; |
1545 | ||
9fdca9df | 1546 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1547 | MODULE_LICENSE("GPL"); |