Commit | Line | Data |
---|---|---|
ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
25 | #include <linux/interrupt.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
30 | #include <linux/dmaengine.h> |
31 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
32 | #include <linux/platform_device.h> |
33 | #include <linux/err.h> | |
34 | #include <linux/clk.h> | |
35 | #include <linux/io.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1f1a4384 | 37 | #include <linux/pm_runtime.h> |
d5a80031 BC |
38 | #include <linux/of.h> |
39 | #include <linux/of_device.h> | |
d33f473d | 40 | #include <linux/gcd.h> |
ccdc7bf9 SO |
41 | |
42 | #include <linux/spi/spi.h> | |
43 | ||
2203747c | 44 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
45 | |
46 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 47 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
48 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
49 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 50 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
51 | |
52 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
53 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
54 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
55 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
56 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
57 | #define OMAP2_MCSPI_SYST 0x24 | |
58 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 59 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
60 | |
61 | /* per-channel banks, 0x14 bytes each, first is: */ | |
62 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
63 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
64 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
65 | #define OMAP2_MCSPI_TX0 0x38 | |
66 | #define OMAP2_MCSPI_RX0 0x3c | |
67 | ||
68 | /* per-register bitmasks: */ | |
d33f473d | 69 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
72 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
73 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 74 | |
7a8fa725 JH |
75 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
76 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 77 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 78 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
81 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 82 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
83 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
84 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
85 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
86 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
87 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
88 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
89 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
90 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
91 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 92 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 93 | |
7a8fa725 JH |
94 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
95 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
96 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 97 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 98 | |
7a8fa725 | 99 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 100 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 101 | |
7a8fa725 | 102 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
103 | |
104 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
105 | struct omap2_mcspi_dma { | |
53741ed8 RK |
106 | struct dma_chan *dma_tx; |
107 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
108 | |
109 | int dma_tx_sync_dev; | |
110 | int dma_rx_sync_dev; | |
111 | ||
112 | struct completion dma_tx_completion; | |
113 | struct completion dma_rx_completion; | |
74f3aaad MP |
114 | |
115 | char dma_rx_ch_name[14]; | |
116 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
117 | }; |
118 | ||
119 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
120 | * cache operations; better heuristics consider wordsize and bitrate. | |
121 | */ | |
8b66c134 | 122 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
123 | |
124 | ||
1bd897f8 BC |
125 | /* |
126 | * Used for context save and restore, structure members to be updated whenever | |
127 | * corresponding registers are modified. | |
128 | */ | |
129 | struct omap2_mcspi_regs { | |
130 | u32 modulctrl; | |
131 | u32 wakeupenable; | |
132 | struct list_head cs; | |
133 | }; | |
134 | ||
ccdc7bf9 | 135 | struct omap2_mcspi { |
ccdc7bf9 | 136 | struct spi_master *master; |
ccdc7bf9 SO |
137 | /* Virtual base address of the controller */ |
138 | void __iomem *base; | |
e5480b73 | 139 | unsigned long phys; |
ccdc7bf9 SO |
140 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
141 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 142 | struct device *dev; |
1bd897f8 | 143 | struct omap2_mcspi_regs ctx; |
d33f473d | 144 | int fifo_depth; |
0384e90b | 145 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
146 | }; |
147 | ||
148 | struct omap2_mcspi_cs { | |
149 | void __iomem *base; | |
e5480b73 | 150 | unsigned long phys; |
ccdc7bf9 | 151 | int word_len; |
89c05372 | 152 | struct list_head node; |
a41ae1ad | 153 | /* Context save and restore shadow register */ |
faee9b05 | 154 | u32 chconf0, chctrl0; |
a41ae1ad H |
155 | }; |
156 | ||
ccdc7bf9 SO |
157 | static inline void mcspi_write_reg(struct spi_master *master, |
158 | int idx, u32 val) | |
159 | { | |
160 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
161 | ||
21b2ce5e | 162 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
163 | } |
164 | ||
165 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
166 | { | |
167 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
168 | ||
21b2ce5e | 169 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
170 | } |
171 | ||
172 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
173 | int idx, u32 val) | |
174 | { | |
175 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
176 | ||
21b2ce5e | 177 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
178 | } |
179 | ||
180 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
181 | { | |
182 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
183 | ||
21b2ce5e | 184 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
185 | } |
186 | ||
a41ae1ad H |
187 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
188 | { | |
189 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
190 | ||
191 | return cs->chconf0; | |
192 | } | |
193 | ||
194 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
195 | { | |
196 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
197 | ||
198 | cs->chconf0 = val; | |
199 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 200 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
201 | } |
202 | ||
56cd5c15 IS |
203 | static inline int mcspi_bytes_per_word(int word_len) |
204 | { | |
205 | if (word_len <= 8) | |
206 | return 1; | |
207 | else if (word_len <= 16) | |
208 | return 2; | |
209 | else /* word_len <= 32 */ | |
210 | return 4; | |
211 | } | |
212 | ||
ccdc7bf9 SO |
213 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
214 | int is_read, int enable) | |
215 | { | |
216 | u32 l, rw; | |
217 | ||
a41ae1ad | 218 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
219 | |
220 | if (is_read) /* 1 is read, 0 write */ | |
221 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
222 | else | |
223 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
224 | ||
af4e944d S |
225 | if (enable) |
226 | l |= rw; | |
227 | else | |
228 | l &= ~rw; | |
229 | ||
a41ae1ad | 230 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
231 | } |
232 | ||
233 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
234 | { | |
faee9b05 | 235 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
236 | u32 l; |
237 | ||
faee9b05 SS |
238 | l = cs->chctrl0; |
239 | if (enable) | |
240 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
241 | else | |
242 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
243 | cs->chctrl0 = l; | |
244 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
245 | /* Flash post-writes */ |
246 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
247 | } |
248 | ||
249 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
250 | { | |
251 | u32 l; | |
252 | ||
a41ae1ad | 253 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
254 | if (cs_active) |
255 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
256 | else | |
257 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
258 | ||
a41ae1ad | 259 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
260 | } |
261 | ||
262 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
263 | { | |
1bd897f8 BC |
264 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
265 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
266 | u32 l; |
267 | ||
1bd897f8 BC |
268 | /* |
269 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
270 | * to single-channel master mode |
271 | */ | |
272 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
273 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
274 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 275 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 276 | |
1bd897f8 | 277 | ctx->modulctrl = l; |
a41ae1ad H |
278 | } |
279 | ||
d33f473d IS |
280 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
281 | struct spi_transfer *t, int enable) | |
282 | { | |
283 | struct spi_master *master = spi->master; | |
284 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
285 | struct omap2_mcspi *mcspi; | |
286 | unsigned int wcnt; | |
5db542ed | 287 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
288 | u32 chconf, xferlevel; |
289 | ||
290 | mcspi = spi_master_get_devdata(master); | |
291 | ||
292 | chconf = mcspi_cached_chconf0(spi); | |
293 | if (enable) { | |
294 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
295 | if (t->len % bytes_per_word != 0) | |
296 | goto disable_fifo; | |
297 | ||
5db542ed IS |
298 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
299 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
300 | else | |
301 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
302 | ||
303 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
304 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
305 | goto disable_fifo; | |
306 | ||
307 | wcnt = t->len / bytes_per_word; | |
308 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
309 | goto disable_fifo; | |
310 | ||
311 | xferlevel = wcnt << 16; | |
312 | if (t->rx_buf != NULL) { | |
313 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
314 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
315 | } |
316 | if (t->tx_buf != NULL) { | |
d33f473d IS |
317 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
318 | xferlevel |= fifo_depth - 1; | |
319 | } | |
320 | ||
321 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
322 | mcspi_write_chconf0(spi, chconf); | |
323 | mcspi->fifo_depth = fifo_depth; | |
324 | ||
325 | return; | |
326 | } | |
327 | ||
328 | disable_fifo: | |
329 | if (t->rx_buf != NULL) | |
330 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
331 | else | |
332 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; | |
333 | ||
334 | mcspi_write_chconf0(spi, chconf); | |
335 | mcspi->fifo_depth = 0; | |
336 | } | |
337 | ||
a41ae1ad H |
338 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
339 | { | |
1bd897f8 BC |
340 | struct spi_master *spi_cntrl = mcspi->master; |
341 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
342 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
343 | |
344 | /* McSPI: context restore */ | |
1bd897f8 BC |
345 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
346 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 347 | |
1bd897f8 | 348 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 349 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 350 | } |
ccdc7bf9 | 351 | |
2764c500 IK |
352 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
353 | { | |
354 | unsigned long timeout; | |
355 | ||
356 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 357 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 358 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 359 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
360 | return -ETIMEDOUT; |
361 | else | |
362 | return 0; | |
363 | } | |
2764c500 IK |
364 | cpu_relax(); |
365 | } | |
366 | return 0; | |
367 | } | |
368 | ||
53741ed8 RK |
369 | static void omap2_mcspi_rx_callback(void *data) |
370 | { | |
371 | struct spi_device *spi = data; | |
372 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
373 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
374 | ||
53741ed8 RK |
375 | /* We must disable the DMA RX request */ |
376 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
377 | |
378 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
379 | } |
380 | ||
381 | static void omap2_mcspi_tx_callback(void *data) | |
382 | { | |
383 | struct spi_device *spi = data; | |
384 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
385 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
386 | ||
53741ed8 RK |
387 | /* We must disable the DMA TX request */ |
388 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
389 | |
390 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
391 | } |
392 | ||
d7b4394e S |
393 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
394 | struct spi_transfer *xfer, | |
395 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
396 | { |
397 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 398 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 399 | unsigned int count; |
ccdc7bf9 SO |
400 | |
401 | mcspi = spi_master_get_devdata(spi->master); | |
402 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 403 | count = xfer->len; |
ccdc7bf9 | 404 | |
d7b4394e | 405 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
406 | struct dma_async_tx_descriptor *tx; |
407 | struct scatterlist sg; | |
408 | ||
409 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
410 | ||
411 | sg_init_table(&sg, 1); | |
412 | sg_dma_address(&sg) = xfer->tx_dma; | |
413 | sg_dma_len(&sg) = xfer->len; | |
414 | ||
415 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 416 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
417 | if (tx) { |
418 | tx->callback = omap2_mcspi_tx_callback; | |
419 | tx->callback_param = spi; | |
420 | dmaengine_submit(tx); | |
421 | } else { | |
422 | /* FIXME: fall back to PIO? */ | |
423 | } | |
424 | } | |
d7b4394e S |
425 | dma_async_issue_pending(mcspi_dma->dma_tx); |
426 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
427 | ||
d7b4394e | 428 | } |
53741ed8 | 429 | |
d7b4394e S |
430 | static unsigned |
431 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
432 | struct dma_slave_config cfg, | |
433 | unsigned es) | |
434 | { | |
435 | struct omap2_mcspi *mcspi; | |
436 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 437 | unsigned int count, dma_count; |
d7b4394e S |
438 | u32 l; |
439 | int elements = 0; | |
440 | int word_len, element_count; | |
441 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
442 | mcspi = spi_master_get_devdata(spi->master); | |
443 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
444 | count = xfer->len; | |
d33f473d IS |
445 | dma_count = xfer->len; |
446 | ||
447 | if (mcspi->fifo_depth == 0) | |
448 | dma_count -= es; | |
449 | ||
d7b4394e S |
450 | word_len = cs->word_len; |
451 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 452 | |
d7b4394e S |
453 | if (word_len <= 8) |
454 | element_count = count; | |
455 | else if (word_len <= 16) | |
456 | element_count = count >> 1; | |
457 | else /* word_len <= 32 */ | |
458 | element_count = count >> 2; | |
459 | ||
460 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
461 | struct dma_async_tx_descriptor *tx; |
462 | struct scatterlist sg; | |
53741ed8 RK |
463 | |
464 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
465 | ||
d33f473d IS |
466 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
467 | dma_count -= es; | |
53741ed8 RK |
468 | |
469 | sg_init_table(&sg, 1); | |
470 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 471 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
472 | |
473 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
474 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
475 | DMA_CTRL_ACK); | |
53741ed8 RK |
476 | if (tx) { |
477 | tx->callback = omap2_mcspi_rx_callback; | |
478 | tx->callback_param = spi; | |
479 | dmaengine_submit(tx); | |
480 | } else { | |
d7b4394e | 481 | /* FIXME: fall back to PIO? */ |
2764c500 | 482 | } |
ccdc7bf9 SO |
483 | } |
484 | ||
d7b4394e S |
485 | dma_async_issue_pending(mcspi_dma->dma_rx); |
486 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 487 | |
d7b4394e S |
488 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
489 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
490 | DMA_FROM_DEVICE); | |
d33f473d IS |
491 | |
492 | if (mcspi->fifo_depth > 0) | |
493 | return count; | |
494 | ||
d7b4394e | 495 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 496 | |
d7b4394e | 497 | elements = element_count - 1; |
4743a0f8 | 498 | |
d7b4394e S |
499 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
500 | elements--; | |
4743a0f8 | 501 | |
57c5c28d | 502 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 503 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
504 | u32 w; |
505 | ||
506 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
507 | if (word_len <= 8) | |
d7b4394e | 508 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 509 | else if (word_len <= 16) |
d7b4394e | 510 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 511 | else /* word_len <= 32 */ |
d7b4394e | 512 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 513 | } else { |
56cd5c15 | 514 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 515 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 516 | count -= (bytes_per_word << 1); |
d7b4394e S |
517 | omap2_mcspi_set_enable(spi, 1); |
518 | return count; | |
57c5c28d | 519 | } |
ccdc7bf9 | 520 | } |
d7b4394e S |
521 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
522 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
523 | u32 w; | |
524 | ||
525 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
526 | if (word_len <= 8) | |
527 | ((u8 *)xfer->rx_buf)[elements] = w; | |
528 | else if (word_len <= 16) | |
529 | ((u16 *)xfer->rx_buf)[elements] = w; | |
530 | else /* word_len <= 32 */ | |
531 | ((u32 *)xfer->rx_buf)[elements] = w; | |
532 | } else { | |
a1829d2b | 533 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 534 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
535 | } |
536 | omap2_mcspi_set_enable(spi, 1); | |
537 | return count; | |
538 | } | |
539 | ||
540 | static unsigned | |
541 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
542 | { | |
543 | struct omap2_mcspi *mcspi; | |
544 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
545 | struct omap2_mcspi_dma *mcspi_dma; | |
546 | unsigned int count; | |
547 | u32 l; | |
548 | u8 *rx; | |
549 | const u8 *tx; | |
550 | struct dma_slave_config cfg; | |
551 | enum dma_slave_buswidth width; | |
552 | unsigned es; | |
d33f473d | 553 | u32 burst; |
e47a682a | 554 | void __iomem *chstat_reg; |
d33f473d IS |
555 | void __iomem *irqstat_reg; |
556 | int wait_res; | |
d7b4394e S |
557 | |
558 | mcspi = spi_master_get_devdata(spi->master); | |
559 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
560 | l = mcspi_cached_chconf0(spi); | |
561 | ||
562 | ||
563 | if (cs->word_len <= 8) { | |
564 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
565 | es = 1; | |
566 | } else if (cs->word_len <= 16) { | |
567 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
568 | es = 2; | |
569 | } else { | |
570 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
571 | es = 4; | |
572 | } | |
573 | ||
d33f473d IS |
574 | count = xfer->len; |
575 | burst = 1; | |
576 | ||
577 | if (mcspi->fifo_depth > 0) { | |
578 | if (count > mcspi->fifo_depth) | |
579 | burst = mcspi->fifo_depth / es; | |
580 | else | |
581 | burst = count / es; | |
582 | } | |
583 | ||
d7b4394e S |
584 | memset(&cfg, 0, sizeof(cfg)); |
585 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
586 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
587 | cfg.src_addr_width = width; | |
588 | cfg.dst_addr_width = width; | |
d33f473d IS |
589 | cfg.src_maxburst = burst; |
590 | cfg.dst_maxburst = burst; | |
d7b4394e S |
591 | |
592 | rx = xfer->rx_buf; | |
593 | tx = xfer->tx_buf; | |
594 | ||
d7b4394e S |
595 | if (tx != NULL) |
596 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
597 | ||
598 | if (rx != NULL) | |
e47a682a S |
599 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
600 | ||
601 | if (tx != NULL) { | |
e47a682a S |
602 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
603 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
604 | DMA_TO_DEVICE); | |
605 | ||
d33f473d IS |
606 | if (mcspi->fifo_depth > 0) { |
607 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
608 | ||
609 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
610 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
611 | dev_err(&spi->dev, "EOW timed out\n"); | |
612 | ||
613 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
614 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
615 | } | |
616 | ||
e47a682a S |
617 | /* for TX_ONLY mode, be sure all words have shifted out */ |
618 | if (rx == NULL) { | |
d33f473d IS |
619 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
620 | if (mcspi->fifo_depth > 0) { | |
621 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
622 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
623 | if (wait_res < 0) | |
624 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
625 | } else { | |
626 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
627 | OMAP2_MCSPI_CHSTAT_TXS); | |
628 | if (wait_res < 0) | |
629 | dev_err(&spi->dev, "TXS timed out\n"); | |
630 | } | |
631 | if (wait_res >= 0 && | |
632 | (mcspi_wait_for_reg_bit(chstat_reg, | |
633 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
634 | dev_err(&spi->dev, "EOT timed out\n"); |
635 | } | |
636 | } | |
ccdc7bf9 SO |
637 | return count; |
638 | } | |
639 | ||
ccdc7bf9 SO |
640 | static unsigned |
641 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
642 | { | |
643 | struct omap2_mcspi *mcspi; | |
644 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
645 | unsigned int count, c; | |
646 | u32 l; | |
647 | void __iomem *base = cs->base; | |
648 | void __iomem *tx_reg; | |
649 | void __iomem *rx_reg; | |
650 | void __iomem *chstat_reg; | |
651 | int word_len; | |
652 | ||
653 | mcspi = spi_master_get_devdata(spi->master); | |
654 | count = xfer->len; | |
655 | c = count; | |
656 | word_len = cs->word_len; | |
657 | ||
a41ae1ad | 658 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
659 | |
660 | /* We store the pre-calculated register addresses on stack to speed | |
661 | * up the transfer loop. */ | |
662 | tx_reg = base + OMAP2_MCSPI_TX0; | |
663 | rx_reg = base + OMAP2_MCSPI_RX0; | |
664 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
665 | ||
adef658d MJ |
666 | if (c < (word_len>>3)) |
667 | return 0; | |
668 | ||
ccdc7bf9 SO |
669 | if (word_len <= 8) { |
670 | u8 *rx; | |
671 | const u8 *tx; | |
672 | ||
673 | rx = xfer->rx_buf; | |
674 | tx = xfer->tx_buf; | |
675 | ||
676 | do { | |
feed9bab | 677 | c -= 1; |
ccdc7bf9 SO |
678 | if (tx != NULL) { |
679 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
680 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
681 | dev_err(&spi->dev, "TXS timed out\n"); | |
682 | goto out; | |
683 | } | |
079a176d | 684 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 685 | word_len, *tx); |
21b2ce5e | 686 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
687 | } |
688 | if (rx != NULL) { | |
689 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
690 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
691 | dev_err(&spi->dev, "RXS timed out\n"); | |
692 | goto out; | |
693 | } | |
4743a0f8 RT |
694 | |
695 | if (c == 1 && tx == NULL && | |
696 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
697 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 698 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 699 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 700 | word_len, *(rx - 1)); |
4743a0f8 RT |
701 | if (mcspi_wait_for_reg_bit(chstat_reg, |
702 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
703 | dev_err(&spi->dev, | |
704 | "RXS timed out\n"); | |
705 | goto out; | |
706 | } | |
707 | c = 0; | |
708 | } else if (c == 0 && tx == NULL) { | |
709 | omap2_mcspi_set_enable(spi, 0); | |
710 | } | |
711 | ||
21b2ce5e | 712 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 713 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 714 | word_len, *(rx - 1)); |
ccdc7bf9 | 715 | } |
95c5c3ab | 716 | } while (c); |
ccdc7bf9 SO |
717 | } else if (word_len <= 16) { |
718 | u16 *rx; | |
719 | const u16 *tx; | |
720 | ||
721 | rx = xfer->rx_buf; | |
722 | tx = xfer->tx_buf; | |
723 | do { | |
feed9bab | 724 | c -= 2; |
ccdc7bf9 SO |
725 | if (tx != NULL) { |
726 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
727 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
728 | dev_err(&spi->dev, "TXS timed out\n"); | |
729 | goto out; | |
730 | } | |
079a176d | 731 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 732 | word_len, *tx); |
21b2ce5e | 733 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
734 | } |
735 | if (rx != NULL) { | |
736 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
737 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
738 | dev_err(&spi->dev, "RXS timed out\n"); | |
739 | goto out; | |
740 | } | |
4743a0f8 RT |
741 | |
742 | if (c == 2 && tx == NULL && | |
743 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
744 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 745 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 746 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 747 | word_len, *(rx - 1)); |
4743a0f8 RT |
748 | if (mcspi_wait_for_reg_bit(chstat_reg, |
749 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
750 | dev_err(&spi->dev, | |
751 | "RXS timed out\n"); | |
752 | goto out; | |
753 | } | |
754 | c = 0; | |
755 | } else if (c == 0 && tx == NULL) { | |
756 | omap2_mcspi_set_enable(spi, 0); | |
757 | } | |
758 | ||
21b2ce5e | 759 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 760 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 761 | word_len, *(rx - 1)); |
ccdc7bf9 | 762 | } |
95c5c3ab | 763 | } while (c >= 2); |
ccdc7bf9 SO |
764 | } else if (word_len <= 32) { |
765 | u32 *rx; | |
766 | const u32 *tx; | |
767 | ||
768 | rx = xfer->rx_buf; | |
769 | tx = xfer->tx_buf; | |
770 | do { | |
feed9bab | 771 | c -= 4; |
ccdc7bf9 SO |
772 | if (tx != NULL) { |
773 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
774 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
775 | dev_err(&spi->dev, "TXS timed out\n"); | |
776 | goto out; | |
777 | } | |
079a176d | 778 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 779 | word_len, *tx); |
21b2ce5e | 780 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
781 | } |
782 | if (rx != NULL) { | |
783 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
784 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
785 | dev_err(&spi->dev, "RXS timed out\n"); | |
786 | goto out; | |
787 | } | |
4743a0f8 RT |
788 | |
789 | if (c == 4 && tx == NULL && | |
790 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
791 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 792 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 793 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 794 | word_len, *(rx - 1)); |
4743a0f8 RT |
795 | if (mcspi_wait_for_reg_bit(chstat_reg, |
796 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
797 | dev_err(&spi->dev, | |
798 | "RXS timed out\n"); | |
799 | goto out; | |
800 | } | |
801 | c = 0; | |
802 | } else if (c == 0 && tx == NULL) { | |
803 | omap2_mcspi_set_enable(spi, 0); | |
804 | } | |
805 | ||
21b2ce5e | 806 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 807 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 808 | word_len, *(rx - 1)); |
ccdc7bf9 | 809 | } |
95c5c3ab | 810 | } while (c >= 4); |
ccdc7bf9 SO |
811 | } |
812 | ||
813 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
814 | if (xfer->rx_buf == NULL) { | |
815 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
816 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
817 | dev_err(&spi->dev, "TXS timed out\n"); | |
818 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
819 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
820 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
821 | |
822 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
823 | * otherwise these rx datas will affect the direct following | |
824 | * RX_ONLY transfer. | |
825 | */ | |
826 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
827 | } |
828 | out: | |
4743a0f8 | 829 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
830 | return count - c; |
831 | } | |
832 | ||
57d9c10d HH |
833 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
834 | { | |
835 | u32 div; | |
836 | ||
837 | for (div = 0; div < 15; div++) | |
838 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
839 | return div; | |
840 | ||
841 | return 15; | |
842 | } | |
843 | ||
ccdc7bf9 SO |
844 | /* called only when no transfer is active to this device */ |
845 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
846 | struct spi_transfer *t) | |
847 | { | |
848 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
849 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 850 | struct spi_master *spi_cntrl; |
faee9b05 | 851 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 852 | u8 word_len = spi->bits_per_word; |
9bd4517d | 853 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
854 | |
855 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 856 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
857 | |
858 | if (t != NULL && t->bits_per_word) | |
859 | word_len = t->bits_per_word; | |
860 | ||
861 | cs->word_len = word_len; | |
862 | ||
9bd4517d SE |
863 | if (t && t->speed_hz) |
864 | speed_hz = t->speed_hz; | |
865 | ||
57d9c10d | 866 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
867 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
868 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
869 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
870 | clkg = 0; | |
871 | } else { | |
872 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
873 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
874 | clkd = (div - 1) & 0xf; | |
875 | extclk = (div - 1) >> 4; | |
876 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
877 | } | |
ccdc7bf9 | 878 | |
a41ae1ad | 879 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
880 | |
881 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
882 | * REVISIT: this controller could support SPI_3WIRE mode. | |
883 | */ | |
2cd45179 | 884 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
885 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
886 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
887 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
888 | } else { | |
889 | l |= OMAP2_MCSPI_CHCONF_IS; | |
890 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
891 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
892 | } | |
ccdc7bf9 SO |
893 | |
894 | /* wordlength */ | |
895 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
896 | l |= (word_len - 1) << 7; | |
897 | ||
898 | /* set chipselect polarity; manage with FORCE */ | |
899 | if (!(spi->mode & SPI_CS_HIGH)) | |
900 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
901 | else | |
902 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
903 | ||
904 | /* set clock divisor */ | |
905 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
906 | l |= clkd << 2; |
907 | ||
908 | /* set clock granularity */ | |
909 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
910 | l |= clkg; | |
911 | if (clkg) { | |
912 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
913 | cs->chctrl0 |= extclk << 8; | |
914 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
915 | } | |
ccdc7bf9 SO |
916 | |
917 | /* set SPI mode 0..3 */ | |
918 | if (spi->mode & SPI_CPOL) | |
919 | l |= OMAP2_MCSPI_CHCONF_POL; | |
920 | else | |
921 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
922 | if (spi->mode & SPI_CPHA) | |
923 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
924 | else | |
925 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
926 | ||
a41ae1ad | 927 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
928 | |
929 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
faee9b05 | 930 | speed_hz, |
ccdc7bf9 SO |
931 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
932 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
ddc5cdf1 TL |
937 | /* |
938 | * Note that we currently allow DMA only if we get a channel | |
939 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
940 | */ | |
ccdc7bf9 SO |
941 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
942 | { | |
943 | struct spi_master *master = spi->master; | |
944 | struct omap2_mcspi *mcspi; | |
945 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
946 | dma_cap_mask_t mask; |
947 | unsigned sig; | |
ccdc7bf9 SO |
948 | |
949 | mcspi = spi_master_get_devdata(master); | |
950 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
951 | ||
53741ed8 RK |
952 | init_completion(&mcspi_dma->dma_rx_completion); |
953 | init_completion(&mcspi_dma->dma_tx_completion); | |
954 | ||
955 | dma_cap_zero(mask); | |
956 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 957 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
958 | |
959 | mcspi_dma->dma_rx = | |
960 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
961 | &sig, &master->dev, | |
962 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
963 | if (!mcspi_dma->dma_rx) |
964 | goto no_dma; | |
ccdc7bf9 | 965 | |
53741ed8 | 966 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
967 | mcspi_dma->dma_tx = |
968 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
969 | &sig, &master->dev, | |
970 | mcspi_dma->dma_tx_ch_name); | |
971 | ||
53741ed8 | 972 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
973 | dma_release_channel(mcspi_dma->dma_rx); |
974 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 975 | goto no_dma; |
ccdc7bf9 SO |
976 | } |
977 | ||
ccdc7bf9 | 978 | return 0; |
ddc5cdf1 TL |
979 | |
980 | no_dma: | |
981 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
982 | return -EAGAIN; | |
ccdc7bf9 SO |
983 | } |
984 | ||
ccdc7bf9 SO |
985 | static int omap2_mcspi_setup(struct spi_device *spi) |
986 | { | |
987 | int ret; | |
1bd897f8 BC |
988 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
989 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
990 | struct omap2_mcspi_dma *mcspi_dma; |
991 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
992 | ||
ccdc7bf9 SO |
993 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
994 | ||
995 | if (!cs) { | |
10aa5a35 | 996 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
997 | if (!cs) |
998 | return -ENOMEM; | |
999 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1000 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 1001 | cs->chconf0 = 0; |
faee9b05 | 1002 | cs->chctrl0 = 0; |
ccdc7bf9 | 1003 | spi->controller_state = cs; |
89c05372 | 1004 | /* Link this to context save list */ |
1bd897f8 | 1005 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
1006 | } |
1007 | ||
8c7494a5 | 1008 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1009 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1010 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1011 | return ret; |
1012 | } | |
1013 | ||
034d3dc9 | 1014 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1015 | if (ret < 0) |
1016 | return ret; | |
a41ae1ad | 1017 | |
86eeb6fe | 1018 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1019 | pm_runtime_mark_last_busy(mcspi->dev); |
1020 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1021 | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1026 | { | |
1027 | struct omap2_mcspi *mcspi; | |
1028 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1029 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1030 | |
1031 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1032 | |
5e774943 SE |
1033 | if (spi->controller_state) { |
1034 | /* Unlink controller state from context save list */ | |
1035 | cs = spi->controller_state; | |
1036 | list_del(&cs->node); | |
89c05372 | 1037 | |
10aa5a35 | 1038 | kfree(cs); |
5e774943 | 1039 | } |
ccdc7bf9 | 1040 | |
99f1a43f SE |
1041 | if (spi->chip_select < spi->master->num_chipselect) { |
1042 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1043 | ||
53741ed8 RK |
1044 | if (mcspi_dma->dma_rx) { |
1045 | dma_release_channel(mcspi_dma->dma_rx); | |
1046 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1047 | } |
53741ed8 RK |
1048 | if (mcspi_dma->dma_tx) { |
1049 | dma_release_channel(mcspi_dma->dma_tx); | |
1050 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1051 | } |
ccdc7bf9 SO |
1052 | } |
1053 | } | |
1054 | ||
5fda88f5 | 1055 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 1056 | { |
ccdc7bf9 SO |
1057 | |
1058 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1059 | * -- although this controller would gladly |
ccdc7bf9 SO |
1060 | * arbitrate among multiple channels. This corresponds to "single |
1061 | * channel" master mode. As a side effect, we need to manage the | |
1062 | * chipselect with the FORCE bit ... CS != channel enable. | |
1063 | */ | |
ccdc7bf9 | 1064 | |
5fda88f5 S |
1065 | struct spi_device *spi; |
1066 | struct spi_transfer *t = NULL; | |
5cbc7ca9 | 1067 | struct spi_master *master; |
ddc5cdf1 | 1068 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1069 | int cs_active = 0; |
1070 | struct omap2_mcspi_cs *cs; | |
1071 | struct omap2_mcspi_device_config *cd; | |
1072 | int par_override = 0; | |
1073 | int status = 0; | |
1074 | u32 chconf; | |
ccdc7bf9 | 1075 | |
5fda88f5 | 1076 | spi = m->spi; |
5cbc7ca9 | 1077 | master = spi->master; |
ddc5cdf1 | 1078 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1079 | cs = spi->controller_state; |
1080 | cd = spi->controller_data; | |
ccdc7bf9 | 1081 | |
d33f473d | 1082 | omap2_mcspi_set_enable(spi, 0); |
5fda88f5 S |
1083 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1084 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
1085 | status = -EINVAL; | |
1086 | break; | |
1087 | } | |
2bd16e3e SS |
1088 | if (par_override || |
1089 | (t->speed_hz != spi->max_speed_hz) || | |
1090 | (t->bits_per_word != spi->bits_per_word)) { | |
5fda88f5 S |
1091 | par_override = 1; |
1092 | status = omap2_mcspi_setup_transfer(spi, t); | |
1093 | if (status < 0) | |
1094 | break; | |
2bd16e3e SS |
1095 | if (t->speed_hz == spi->max_speed_hz && |
1096 | t->bits_per_word == spi->bits_per_word) | |
5fda88f5 S |
1097 | par_override = 0; |
1098 | } | |
5cbc7ca9 MB |
1099 | if (cd && cd->cs_per_word) { |
1100 | chconf = mcspi->ctx.modulctrl; | |
1101 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1102 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1103 | mcspi->ctx.modulctrl = | |
1104 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1105 | } | |
1106 | ||
4743a0f8 | 1107 | |
5fda88f5 S |
1108 | if (!cs_active) { |
1109 | omap2_mcspi_force_cs(spi, 1); | |
1110 | cs_active = 1; | |
1111 | } | |
4743a0f8 | 1112 | |
5fda88f5 S |
1113 | chconf = mcspi_cached_chconf0(spi); |
1114 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1115 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 1116 | |
5fda88f5 S |
1117 | if (t->tx_buf == NULL) |
1118 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1119 | else if (t->rx_buf == NULL) | |
1120 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 1121 | |
5fda88f5 S |
1122 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
1123 | /* Turbo mode is for more than one word */ | |
1124 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1125 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1126 | } | |
ccdc7bf9 | 1127 | |
5fda88f5 | 1128 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1129 | |
5fda88f5 S |
1130 | if (t->len) { |
1131 | unsigned count; | |
1132 | ||
d33f473d IS |
1133 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1134 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
1135 | omap2_mcspi_set_fifo(spi, t, 1); | |
1136 | ||
1137 | omap2_mcspi_set_enable(spi, 1); | |
1138 | ||
5fda88f5 S |
1139 | /* RX_ONLY mode needs dummy data in TX reg */ |
1140 | if (t->tx_buf == NULL) | |
21b2ce5e | 1141 | writel_relaxed(0, cs->base |
5fda88f5 | 1142 | + OMAP2_MCSPI_TX0); |
ccdc7bf9 | 1143 | |
ddc5cdf1 TL |
1144 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1145 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
5fda88f5 S |
1146 | count = omap2_mcspi_txrx_dma(spi, t); |
1147 | else | |
1148 | count = omap2_mcspi_txrx_pio(spi, t); | |
1149 | m->actual_length += count; | |
ccdc7bf9 | 1150 | |
5fda88f5 S |
1151 | if (count != t->len) { |
1152 | status = -EIO; | |
1153 | break; | |
ccdc7bf9 SO |
1154 | } |
1155 | } | |
1156 | ||
5fda88f5 S |
1157 | if (t->delay_usecs) |
1158 | udelay(t->delay_usecs); | |
ccdc7bf9 | 1159 | |
5fda88f5 S |
1160 | /* ignore the "leave it on after last xfer" hint */ |
1161 | if (t->cs_change) { | |
ccdc7bf9 | 1162 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1163 | cs_active = 0; |
1164 | } | |
d33f473d IS |
1165 | |
1166 | omap2_mcspi_set_enable(spi, 0); | |
1167 | ||
1168 | if (mcspi->fifo_depth > 0) | |
1169 | omap2_mcspi_set_fifo(spi, t, 0); | |
5fda88f5 S |
1170 | } |
1171 | /* Restore defaults if they were overriden */ | |
1172 | if (par_override) { | |
1173 | par_override = 0; | |
1174 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1175 | } | |
ccdc7bf9 | 1176 | |
5fda88f5 S |
1177 | if (cs_active) |
1178 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1179 | |
5cbc7ca9 MB |
1180 | if (cd && cd->cs_per_word) { |
1181 | chconf = mcspi->ctx.modulctrl; | |
1182 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1183 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1184 | mcspi->ctx.modulctrl = | |
1185 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1186 | } | |
1187 | ||
5fda88f5 | 1188 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1189 | |
d33f473d IS |
1190 | if (mcspi->fifo_depth > 0 && t) |
1191 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1192 | |
d33f473d | 1193 | m->status = status; |
ccdc7bf9 SO |
1194 | } |
1195 | ||
5fda88f5 | 1196 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
18dd6199 | 1197 | struct spi_message *m) |
ccdc7bf9 | 1198 | { |
ddc5cdf1 | 1199 | struct spi_device *spi; |
ccdc7bf9 | 1200 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1201 | struct omap2_mcspi_dma *mcspi_dma; |
ccdc7bf9 SO |
1202 | struct spi_transfer *t; |
1203 | ||
ddc5cdf1 | 1204 | spi = m->spi; |
5fda88f5 | 1205 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1206 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 SO |
1207 | m->actual_length = 0; |
1208 | m->status = 0; | |
1209 | ||
ccdc7bf9 SO |
1210 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1211 | const void *tx_buf = t->tx_buf; | |
1212 | void *rx_buf = t->rx_buf; | |
1213 | unsigned len = t->len; | |
1214 | ||
aca0924b | 1215 | if ((len && !(rx_buf || tx_buf))) { |
5fda88f5 | 1216 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1217 | t->speed_hz, |
1218 | len, | |
1219 | tx_buf ? "tx" : "", | |
1220 | rx_buf ? "rx" : "", | |
1221 | t->bits_per_word); | |
1222 | return -EINVAL; | |
1223 | } | |
ccdc7bf9 SO |
1224 | |
1225 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1226 | continue; | |
1227 | ||
ddc5cdf1 | 1228 | if (mcspi_dma->dma_tx && tx_buf != NULL) { |
5fda88f5 | 1229 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1230 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1231 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1232 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1233 | 'T', len); |
1234 | return -EINVAL; | |
1235 | } | |
1236 | } | |
ddc5cdf1 | 1237 | if (mcspi_dma->dma_rx && rx_buf != NULL) { |
5fda88f5 | 1238 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1239 | DMA_FROM_DEVICE); |
5fda88f5 S |
1240 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1241 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1242 | 'R', len); |
1243 | if (tx_buf != NULL) | |
5fda88f5 | 1244 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1245 | len, DMA_TO_DEVICE); |
1246 | return -EINVAL; | |
1247 | } | |
1248 | } | |
1249 | } | |
1250 | ||
5fda88f5 S |
1251 | omap2_mcspi_work(mcspi, m); |
1252 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1253 | return 0; |
1254 | } | |
1255 | ||
fd4a319b | 1256 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1257 | { |
1258 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1259 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1260 | int ret = 0; |
ccdc7bf9 | 1261 | |
034d3dc9 | 1262 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1263 | if (ret < 0) |
1264 | return ret; | |
ddb22195 | 1265 | |
39f8052d | 1266 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1267 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1268 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1269 | |
1270 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1271 | pm_runtime_mark_last_busy(mcspi->dev); |
1272 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1273 | return 0; |
1274 | } | |
1275 | ||
1f1a4384 G |
1276 | static int omap_mcspi_runtime_resume(struct device *dev) |
1277 | { | |
1278 | struct omap2_mcspi *mcspi; | |
1279 | struct spi_master *master; | |
1280 | ||
1281 | master = dev_get_drvdata(dev); | |
1282 | mcspi = spi_master_get_devdata(master); | |
1283 | omap2_mcspi_restore_ctx(mcspi); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
d5a80031 BC |
1288 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1289 | .regs_offset = 0, | |
1290 | }; | |
1291 | ||
1292 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1293 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1294 | }; | |
1295 | ||
1296 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1297 | { | |
1298 | .compatible = "ti,omap2-mcspi", | |
1299 | .data = &omap2_pdata, | |
1300 | }, | |
1301 | { | |
1302 | .compatible = "ti,omap4-mcspi", | |
1303 | .data = &omap4_pdata, | |
1304 | }, | |
1305 | { }, | |
1306 | }; | |
1307 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1308 | |
fd4a319b | 1309 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1310 | { |
1311 | struct spi_master *master; | |
83a01e72 | 1312 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1313 | struct omap2_mcspi *mcspi; |
1314 | struct resource *r; | |
1315 | int status = 0, i; | |
d5a80031 BC |
1316 | u32 regs_offset = 0; |
1317 | static int bus_num = 1; | |
1318 | struct device_node *node = pdev->dev.of_node; | |
1319 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1320 | |
1321 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1322 | if (master == NULL) { | |
1323 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1324 | return -ENOMEM; | |
1325 | } | |
1326 | ||
e7db06b5 DB |
1327 | /* the spi->mode bits understood by this driver: */ |
1328 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1329 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1330 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1331 | master->auto_runtime_pm = true; |
5fda88f5 | 1332 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
ccdc7bf9 | 1333 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1334 | master->dev.of_node = node; |
aca0924b AL |
1335 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1336 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1337 | |
24b5a82c | 1338 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1339 | |
1340 | mcspi = spi_master_get_devdata(master); | |
1341 | mcspi->master = master; | |
1342 | ||
d5a80031 BC |
1343 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1344 | if (match) { | |
1345 | u32 num_cs = 1; /* default number of chipselect */ | |
1346 | pdata = match->data; | |
1347 | ||
1348 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1349 | master->num_chipselect = num_cs; | |
1350 | master->bus_num = bus_num++; | |
2cd45179 DM |
1351 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1352 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1353 | } else { |
8074cf06 | 1354 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1355 | master->num_chipselect = pdata->num_cs; |
1356 | if (pdev->id != -1) | |
1357 | master->bus_num = pdev->id; | |
0384e90b | 1358 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1359 | } |
1360 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1361 | |
ccdc7bf9 SO |
1362 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1363 | if (r == NULL) { | |
1364 | status = -ENODEV; | |
39f1b565 | 1365 | goto free_master; |
ccdc7bf9 | 1366 | } |
1458d160 | 1367 | |
d5a80031 BC |
1368 | r->start += regs_offset; |
1369 | r->end += regs_offset; | |
1458d160 | 1370 | mcspi->phys = r->start; |
ccdc7bf9 | 1371 | |
b0ee5605 TR |
1372 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1373 | if (IS_ERR(mcspi->base)) { | |
1374 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1375 | goto free_master; |
55c381e4 | 1376 | } |
ccdc7bf9 | 1377 | |
1f1a4384 | 1378 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1379 | |
1bd897f8 | 1380 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1381 | |
a6f936db AL |
1382 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1383 | sizeof(struct omap2_mcspi_dma), | |
1384 | GFP_KERNEL); | |
1385 | if (mcspi->dma_channels == NULL) { | |
1386 | status = -ENOMEM; | |
1a77b127 | 1387 | goto free_master; |
a6f936db | 1388 | } |
ccdc7bf9 | 1389 | |
1a5d8190 | 1390 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1391 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1392 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1393 | struct resource *dma_res; |
1394 | ||
74f3aaad MP |
1395 | sprintf(dma_rx_ch_name, "rx%d", i); |
1396 | if (!pdev->dev.of_node) { | |
1397 | dma_res = | |
1398 | platform_get_resource_byname(pdev, | |
1399 | IORESOURCE_DMA, | |
1400 | dma_rx_ch_name); | |
1401 | if (!dma_res) { | |
1402 | dev_dbg(&pdev->dev, | |
1403 | "cannot get DMA RX channel\n"); | |
1404 | status = -ENODEV; | |
1405 | break; | |
1406 | } | |
1a5d8190 | 1407 | |
74f3aaad MP |
1408 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1409 | dma_res->start; | |
1a5d8190 | 1410 | } |
74f3aaad MP |
1411 | sprintf(dma_tx_ch_name, "tx%d", i); |
1412 | if (!pdev->dev.of_node) { | |
1413 | dma_res = | |
1414 | platform_get_resource_byname(pdev, | |
1415 | IORESOURCE_DMA, | |
1416 | dma_tx_ch_name); | |
1417 | if (!dma_res) { | |
1418 | dev_dbg(&pdev->dev, | |
1419 | "cannot get DMA TX channel\n"); | |
1420 | status = -ENODEV; | |
1421 | break; | |
1422 | } | |
1a5d8190 | 1423 | |
74f3aaad MP |
1424 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1425 | dma_res->start; | |
1426 | } | |
ccdc7bf9 SO |
1427 | } |
1428 | ||
39f1b565 | 1429 | if (status < 0) |
a6f936db | 1430 | goto free_master; |
39f1b565 | 1431 | |
27b5284c S |
1432 | pm_runtime_use_autosuspend(&pdev->dev); |
1433 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1434 | pm_runtime_enable(&pdev->dev); |
1435 | ||
142e07be WY |
1436 | status = omap2_mcspi_master_setup(mcspi); |
1437 | if (status < 0) | |
39f1b565 | 1438 | goto disable_pm; |
ccdc7bf9 | 1439 | |
b95e02b7 | 1440 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1441 | if (status < 0) |
37a2d84a | 1442 | goto disable_pm; |
ccdc7bf9 SO |
1443 | |
1444 | return status; | |
1445 | ||
39f1b565 | 1446 | disable_pm: |
751c925c | 1447 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1448 | free_master: |
37a2d84a | 1449 | spi_master_put(master); |
ccdc7bf9 SO |
1450 | return status; |
1451 | } | |
1452 | ||
fd4a319b | 1453 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1454 | { |
a6f936db AL |
1455 | struct spi_master *master = platform_get_drvdata(pdev); |
1456 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1457 | |
a93a2029 | 1458 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1459 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1460 | |
ccdc7bf9 SO |
1461 | return 0; |
1462 | } | |
1463 | ||
7e38c3c4 KS |
1464 | /* work with hotplug and coldplug */ |
1465 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1466 | ||
42ce7fd6 GC |
1467 | #ifdef CONFIG_SUSPEND |
1468 | /* | |
1469 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1470 | * unactive state when driver was suspend, then force it to unactive state at | |
1471 | * wake up. | |
1472 | */ | |
1473 | static int omap2_mcspi_resume(struct device *dev) | |
1474 | { | |
1475 | struct spi_master *master = dev_get_drvdata(dev); | |
1476 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1477 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1478 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1479 | |
034d3dc9 | 1480 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1481 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1482 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1483 | /* |
1484 | * We need to toggle CS state for OMAP take this | |
1485 | * change in account. | |
1486 | */ | |
af4e944d | 1487 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1488 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1489 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1490 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1491 | } |
1492 | } | |
034d3dc9 S |
1493 | pm_runtime_mark_last_busy(mcspi->dev); |
1494 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1495 | return 0; |
1496 | } | |
1497 | #else | |
1498 | #define omap2_mcspi_resume NULL | |
1499 | #endif | |
1500 | ||
1501 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1502 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1503 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1504 | }; |
1505 | ||
ccdc7bf9 SO |
1506 | static struct platform_driver omap2_mcspi_driver = { |
1507 | .driver = { | |
1508 | .name = "omap2_mcspi", | |
1509 | .owner = THIS_MODULE, | |
d5a80031 BC |
1510 | .pm = &omap2_mcspi_pm_ops, |
1511 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1512 | }, |
7d6b6d83 | 1513 | .probe = omap2_mcspi_probe, |
fd4a319b | 1514 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1515 | }; |
1516 | ||
9fdca9df | 1517 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1518 | MODULE_LICENSE("GPL"); |