Commit | Line | Data |
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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 | 25 | #include <linux/dmaengine.h> |
beca3655 | 26 | #include <linux/pinctrl/consumer.h> |
ccdc7bf9 SO |
27 | #include <linux/platform_device.h> |
28 | #include <linux/err.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
1f1a4384 | 32 | #include <linux/pm_runtime.h> |
d5a80031 BC |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
d33f473d | 35 | #include <linux/gcd.h> |
ccdc7bf9 SO |
36 | |
37 | #include <linux/spi/spi.h> | |
bc7f9bbc | 38 | #include <linux/gpio.h> |
ccdc7bf9 | 39 | |
2203747c | 40 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
41 | |
42 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 43 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
44 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
45 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 46 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
49 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
50 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
51 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
52 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
53 | #define OMAP2_MCSPI_SYST 0x24 | |
54 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 55 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
56 | |
57 | /* per-channel banks, 0x14 bytes each, first is: */ | |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
61 | #define OMAP2_MCSPI_TX0 0x38 | |
62 | #define OMAP2_MCSPI_RX0 0x3c | |
63 | ||
64 | /* per-register bitmasks: */ | |
d33f473d | 65 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 66 | |
7a8fa725 JH |
67 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
68 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
69 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
72 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 73 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 74 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 75 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
76 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
77 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 78 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
79 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
80 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
81 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
83 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
84 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
85 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
86 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
87 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 88 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 89 | |
7a8fa725 JH |
90 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
91 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
92 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 93 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 94 | |
7a8fa725 | 95 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 96 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 97 | |
7a8fa725 | 98 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
99 | |
100 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
101 | struct omap2_mcspi_dma { | |
53741ed8 RK |
102 | struct dma_chan *dma_tx; |
103 | struct dma_chan *dma_rx; | |
ccdc7bf9 | 104 | |
ccdc7bf9 SO |
105 | struct completion dma_tx_completion; |
106 | struct completion dma_rx_completion; | |
74f3aaad MP |
107 | |
108 | char dma_rx_ch_name[14]; | |
109 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
110 | }; |
111 | ||
112 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
113 | * cache operations; better heuristics consider wordsize and bitrate. | |
114 | */ | |
8b66c134 | 115 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
116 | |
117 | ||
1bd897f8 BC |
118 | /* |
119 | * Used for context save and restore, structure members to be updated whenever | |
120 | * corresponding registers are modified. | |
121 | */ | |
122 | struct omap2_mcspi_regs { | |
123 | u32 modulctrl; | |
124 | u32 wakeupenable; | |
125 | struct list_head cs; | |
126 | }; | |
127 | ||
ccdc7bf9 | 128 | struct omap2_mcspi { |
ccdc7bf9 | 129 | struct spi_master *master; |
ccdc7bf9 SO |
130 | /* Virtual base address of the controller */ |
131 | void __iomem *base; | |
e5480b73 | 132 | unsigned long phys; |
ccdc7bf9 SO |
133 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
134 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 135 | struct device *dev; |
1bd897f8 | 136 | struct omap2_mcspi_regs ctx; |
d33f473d | 137 | int fifo_depth; |
0384e90b | 138 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
139 | }; |
140 | ||
141 | struct omap2_mcspi_cs { | |
142 | void __iomem *base; | |
e5480b73 | 143 | unsigned long phys; |
ccdc7bf9 | 144 | int word_len; |
97ca0d6c | 145 | u16 mode; |
89c05372 | 146 | struct list_head node; |
a41ae1ad | 147 | /* Context save and restore shadow register */ |
faee9b05 | 148 | u32 chconf0, chctrl0; |
a41ae1ad H |
149 | }; |
150 | ||
ccdc7bf9 SO |
151 | static inline void mcspi_write_reg(struct spi_master *master, |
152 | int idx, u32 val) | |
153 | { | |
154 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
155 | ||
21b2ce5e | 156 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
157 | } |
158 | ||
159 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
160 | { | |
161 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
162 | ||
21b2ce5e | 163 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
164 | } |
165 | ||
166 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
167 | int idx, u32 val) | |
168 | { | |
169 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
170 | ||
21b2ce5e | 171 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
172 | } |
173 | ||
174 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
175 | { | |
176 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
177 | ||
21b2ce5e | 178 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
179 | } |
180 | ||
a41ae1ad H |
181 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
182 | { | |
183 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
184 | ||
185 | return cs->chconf0; | |
186 | } | |
187 | ||
188 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
189 | { | |
190 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
191 | ||
192 | cs->chconf0 = val; | |
193 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 194 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
195 | } |
196 | ||
56cd5c15 IS |
197 | static inline int mcspi_bytes_per_word(int word_len) |
198 | { | |
199 | if (word_len <= 8) | |
200 | return 1; | |
201 | else if (word_len <= 16) | |
202 | return 2; | |
203 | else /* word_len <= 32 */ | |
204 | return 4; | |
205 | } | |
206 | ||
ccdc7bf9 SO |
207 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
208 | int is_read, int enable) | |
209 | { | |
210 | u32 l, rw; | |
211 | ||
a41ae1ad | 212 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
213 | |
214 | if (is_read) /* 1 is read, 0 write */ | |
215 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
216 | else | |
217 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
218 | ||
af4e944d S |
219 | if (enable) |
220 | l |= rw; | |
221 | else | |
222 | l &= ~rw; | |
223 | ||
a41ae1ad | 224 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
225 | } |
226 | ||
227 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
228 | { | |
faee9b05 | 229 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
230 | u32 l; |
231 | ||
faee9b05 SS |
232 | l = cs->chctrl0; |
233 | if (enable) | |
234 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
235 | else | |
236 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
237 | cs->chctrl0 = l; | |
238 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
239 | /* Flash post-writes */ |
240 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
241 | } |
242 | ||
ddcad7e9 | 243 | static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) |
ccdc7bf9 | 244 | { |
5f74db10 | 245 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
ccdc7bf9 SO |
246 | u32 l; |
247 | ||
4373f8b6 MW |
248 | /* The controller handles the inverted chip selects |
249 | * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert | |
250 | * the inversion from the core spi_set_cs function. | |
251 | */ | |
252 | if (spi->mode & SPI_CS_HIGH) | |
253 | enable = !enable; | |
254 | ||
ddcad7e9 | 255 | if (spi->controller_state) { |
5f74db10 SR |
256 | int err = pm_runtime_get_sync(mcspi->dev); |
257 | if (err < 0) { | |
258 | dev_err(mcspi->dev, "failed to get sync: %d\n", err); | |
259 | return; | |
260 | } | |
261 | ||
ddcad7e9 | 262 | l = mcspi_cached_chconf0(spi); |
af4e944d | 263 | |
ddcad7e9 MW |
264 | if (enable) |
265 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
266 | else | |
267 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
268 | ||
269 | mcspi_write_chconf0(spi, l); | |
5f74db10 SR |
270 | |
271 | pm_runtime_mark_last_busy(mcspi->dev); | |
272 | pm_runtime_put_autosuspend(mcspi->dev); | |
ddcad7e9 | 273 | } |
ccdc7bf9 SO |
274 | } |
275 | ||
276 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
277 | { | |
1bd897f8 BC |
278 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
279 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
280 | u32 l; |
281 | ||
1bd897f8 BC |
282 | /* |
283 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
284 | * to single-channel master mode |
285 | */ | |
286 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
287 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
288 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 289 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 290 | |
1bd897f8 | 291 | ctx->modulctrl = l; |
a41ae1ad H |
292 | } |
293 | ||
d33f473d IS |
294 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
295 | struct spi_transfer *t, int enable) | |
296 | { | |
297 | struct spi_master *master = spi->master; | |
298 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
299 | struct omap2_mcspi *mcspi; | |
300 | unsigned int wcnt; | |
5db542ed | 301 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
302 | u32 chconf, xferlevel; |
303 | ||
304 | mcspi = spi_master_get_devdata(master); | |
305 | ||
306 | chconf = mcspi_cached_chconf0(spi); | |
307 | if (enable) { | |
308 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
309 | if (t->len % bytes_per_word != 0) | |
310 | goto disable_fifo; | |
311 | ||
5db542ed IS |
312 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
313 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
314 | else | |
315 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
316 | ||
317 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
318 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
319 | goto disable_fifo; | |
320 | ||
321 | wcnt = t->len / bytes_per_word; | |
322 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
323 | goto disable_fifo; | |
324 | ||
325 | xferlevel = wcnt << 16; | |
326 | if (t->rx_buf != NULL) { | |
327 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
328 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
329 | } |
330 | if (t->tx_buf != NULL) { | |
d33f473d IS |
331 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
332 | xferlevel |= fifo_depth - 1; | |
333 | } | |
334 | ||
335 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
336 | mcspi_write_chconf0(spi, chconf); | |
337 | mcspi->fifo_depth = fifo_depth; | |
338 | ||
339 | return; | |
340 | } | |
341 | ||
342 | disable_fifo: | |
343 | if (t->rx_buf != NULL) | |
344 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
345 | |
346 | if (t->tx_buf != NULL) | |
d33f473d IS |
347 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
348 | ||
349 | mcspi_write_chconf0(spi, chconf); | |
350 | mcspi->fifo_depth = 0; | |
351 | } | |
352 | ||
a41ae1ad H |
353 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
354 | { | |
1bd897f8 BC |
355 | struct spi_master *spi_cntrl = mcspi->master; |
356 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
357 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
358 | |
359 | /* McSPI: context restore */ | |
1bd897f8 BC |
360 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
361 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 362 | |
1bd897f8 | 363 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 364 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 365 | } |
ccdc7bf9 | 366 | |
2764c500 IK |
367 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
368 | { | |
369 | unsigned long timeout; | |
370 | ||
371 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 372 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 373 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 374 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
375 | return -ETIMEDOUT; |
376 | else | |
377 | return 0; | |
378 | } | |
2764c500 IK |
379 | cpu_relax(); |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
53741ed8 RK |
384 | static void omap2_mcspi_rx_callback(void *data) |
385 | { | |
386 | struct spi_device *spi = data; | |
387 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
388 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
389 | ||
53741ed8 RK |
390 | /* We must disable the DMA RX request */ |
391 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
392 | |
393 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
394 | } |
395 | ||
396 | static void omap2_mcspi_tx_callback(void *data) | |
397 | { | |
398 | struct spi_device *spi = data; | |
399 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
400 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
401 | ||
53741ed8 RK |
402 | /* We must disable the DMA TX request */ |
403 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
404 | |
405 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
406 | } |
407 | ||
d7b4394e S |
408 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
409 | struct spi_transfer *xfer, | |
410 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
411 | { |
412 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 413 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 414 | unsigned int count; |
ccdc7bf9 SO |
415 | |
416 | mcspi = spi_master_get_devdata(spi->master); | |
417 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 418 | count = xfer->len; |
ccdc7bf9 | 419 | |
d7b4394e | 420 | if (mcspi_dma->dma_tx) { |
53741ed8 | 421 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
422 | |
423 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
424 | ||
0ba1870f FCJ |
425 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, |
426 | xfer->tx_sg.nents, | |
427 | DMA_MEM_TO_DEV, | |
428 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
429 | if (tx) { |
430 | tx->callback = omap2_mcspi_tx_callback; | |
431 | tx->callback_param = spi; | |
432 | dmaengine_submit(tx); | |
433 | } else { | |
434 | /* FIXME: fall back to PIO? */ | |
435 | } | |
436 | } | |
d7b4394e S |
437 | dma_async_issue_pending(mcspi_dma->dma_tx); |
438 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
439 | ||
d7b4394e | 440 | } |
53741ed8 | 441 | |
d7b4394e S |
442 | static unsigned |
443 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
444 | struct dma_slave_config cfg, | |
445 | unsigned es) | |
446 | { | |
447 | struct omap2_mcspi *mcspi; | |
448 | struct omap2_mcspi_dma *mcspi_dma; | |
0ba1870f FCJ |
449 | unsigned int count, transfer_reduction = 0; |
450 | struct scatterlist *sg_out[2]; | |
451 | int nb_sizes = 0, out_mapped_nents[2], ret, x; | |
452 | size_t sizes[2]; | |
d7b4394e S |
453 | u32 l; |
454 | int elements = 0; | |
455 | int word_len, element_count; | |
456 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
457 | mcspi = spi_master_get_devdata(spi->master); | |
458 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
459 | count = xfer->len; | |
d33f473d | 460 | |
4bd00413 FCJ |
461 | /* |
462 | * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM | |
463 | * it mentions reducing DMA transfer length by one element in master | |
464 | * normal mode. | |
465 | */ | |
d33f473d | 466 | if (mcspi->fifo_depth == 0) |
0ba1870f | 467 | transfer_reduction = es; |
d33f473d | 468 | |
d7b4394e S |
469 | word_len = cs->word_len; |
470 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 471 | |
d7b4394e S |
472 | if (word_len <= 8) |
473 | element_count = count; | |
474 | else if (word_len <= 16) | |
475 | element_count = count >> 1; | |
476 | else /* word_len <= 32 */ | |
477 | element_count = count >> 2; | |
478 | ||
479 | if (mcspi_dma->dma_rx) { | |
53741ed8 | 480 | struct dma_async_tx_descriptor *tx; |
53741ed8 RK |
481 | |
482 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
483 | ||
4bd00413 FCJ |
484 | /* |
485 | * Reduce DMA transfer length by one more if McSPI is | |
486 | * configured in turbo mode. | |
487 | */ | |
d33f473d | 488 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
0ba1870f FCJ |
489 | transfer_reduction += es; |
490 | ||
491 | if (transfer_reduction) { | |
492 | /* Split sgl into two. The second sgl won't be used. */ | |
493 | sizes[0] = count - transfer_reduction; | |
494 | sizes[1] = transfer_reduction; | |
495 | nb_sizes = 2; | |
496 | } else { | |
497 | /* | |
498 | * Don't bother splitting the sgl. This essentially | |
499 | * clones the original sgl. | |
500 | */ | |
501 | sizes[0] = count; | |
502 | nb_sizes = 1; | |
503 | } | |
504 | ||
505 | ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, | |
506 | 0, nb_sizes, | |
507 | sizes, | |
508 | sg_out, out_mapped_nents, | |
509 | GFP_KERNEL); | |
53741ed8 | 510 | |
0ba1870f FCJ |
511 | if (ret < 0) { |
512 | dev_err(&spi->dev, "sg_split failed\n"); | |
513 | return 0; | |
514 | } | |
53741ed8 | 515 | |
0ba1870f FCJ |
516 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, |
517 | sg_out[0], | |
518 | out_mapped_nents[0], | |
519 | DMA_DEV_TO_MEM, | |
520 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
53741ed8 RK |
521 | if (tx) { |
522 | tx->callback = omap2_mcspi_rx_callback; | |
523 | tx->callback_param = spi; | |
524 | dmaengine_submit(tx); | |
525 | } else { | |
d7b4394e | 526 | /* FIXME: fall back to PIO? */ |
2764c500 | 527 | } |
ccdc7bf9 SO |
528 | } |
529 | ||
d7b4394e S |
530 | dma_async_issue_pending(mcspi_dma->dma_rx); |
531 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 532 | |
d7b4394e | 533 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
0ba1870f FCJ |
534 | |
535 | for (x = 0; x < nb_sizes; x++) | |
536 | kfree(sg_out[x]); | |
d33f473d IS |
537 | |
538 | if (mcspi->fifo_depth > 0) | |
539 | return count; | |
540 | ||
4bd00413 FCJ |
541 | /* |
542 | * Due to the DMA transfer length reduction the missing bytes must | |
543 | * be read manually to receive all of the expected data. | |
544 | */ | |
d7b4394e | 545 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 546 | |
d7b4394e | 547 | elements = element_count - 1; |
4743a0f8 | 548 | |
d7b4394e S |
549 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
550 | elements--; | |
4743a0f8 | 551 | |
57c5c28d | 552 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 553 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
554 | u32 w; |
555 | ||
556 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
557 | if (word_len <= 8) | |
d7b4394e | 558 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 559 | else if (word_len <= 16) |
d7b4394e | 560 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 561 | else /* word_len <= 32 */ |
d7b4394e | 562 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 563 | } else { |
56cd5c15 | 564 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 565 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 566 | count -= (bytes_per_word << 1); |
d7b4394e S |
567 | omap2_mcspi_set_enable(spi, 1); |
568 | return count; | |
57c5c28d | 569 | } |
ccdc7bf9 | 570 | } |
d7b4394e S |
571 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
572 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
573 | u32 w; | |
574 | ||
575 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
576 | if (word_len <= 8) | |
577 | ((u8 *)xfer->rx_buf)[elements] = w; | |
578 | else if (word_len <= 16) | |
579 | ((u16 *)xfer->rx_buf)[elements] = w; | |
580 | else /* word_len <= 32 */ | |
581 | ((u32 *)xfer->rx_buf)[elements] = w; | |
582 | } else { | |
a1829d2b | 583 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 584 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
585 | } |
586 | omap2_mcspi_set_enable(spi, 1); | |
587 | return count; | |
588 | } | |
589 | ||
590 | static unsigned | |
591 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
592 | { | |
593 | struct omap2_mcspi *mcspi; | |
594 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
595 | struct omap2_mcspi_dma *mcspi_dma; | |
596 | unsigned int count; | |
597 | u32 l; | |
598 | u8 *rx; | |
599 | const u8 *tx; | |
600 | struct dma_slave_config cfg; | |
601 | enum dma_slave_buswidth width; | |
602 | unsigned es; | |
d33f473d | 603 | u32 burst; |
e47a682a | 604 | void __iomem *chstat_reg; |
d33f473d IS |
605 | void __iomem *irqstat_reg; |
606 | int wait_res; | |
d7b4394e S |
607 | |
608 | mcspi = spi_master_get_devdata(spi->master); | |
609 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
610 | l = mcspi_cached_chconf0(spi); | |
611 | ||
612 | ||
613 | if (cs->word_len <= 8) { | |
614 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
615 | es = 1; | |
616 | } else if (cs->word_len <= 16) { | |
617 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
618 | es = 2; | |
619 | } else { | |
620 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
621 | es = 4; | |
622 | } | |
623 | ||
d33f473d IS |
624 | count = xfer->len; |
625 | burst = 1; | |
626 | ||
627 | if (mcspi->fifo_depth > 0) { | |
628 | if (count > mcspi->fifo_depth) | |
629 | burst = mcspi->fifo_depth / es; | |
630 | else | |
631 | burst = count / es; | |
632 | } | |
633 | ||
d7b4394e S |
634 | memset(&cfg, 0, sizeof(cfg)); |
635 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
636 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
637 | cfg.src_addr_width = width; | |
638 | cfg.dst_addr_width = width; | |
d33f473d IS |
639 | cfg.src_maxburst = burst; |
640 | cfg.dst_maxburst = burst; | |
d7b4394e S |
641 | |
642 | rx = xfer->rx_buf; | |
643 | tx = xfer->tx_buf; | |
644 | ||
d7b4394e S |
645 | if (tx != NULL) |
646 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
647 | ||
648 | if (rx != NULL) | |
e47a682a S |
649 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
650 | ||
651 | if (tx != NULL) { | |
e47a682a | 652 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
e47a682a | 653 | |
d33f473d IS |
654 | if (mcspi->fifo_depth > 0) { |
655 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
656 | ||
657 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
658 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
659 | dev_err(&spi->dev, "EOW timed out\n"); | |
660 | ||
661 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
662 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
663 | } | |
664 | ||
e47a682a S |
665 | /* for TX_ONLY mode, be sure all words have shifted out */ |
666 | if (rx == NULL) { | |
d33f473d IS |
667 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
668 | if (mcspi->fifo_depth > 0) { | |
669 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
670 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
671 | if (wait_res < 0) | |
672 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
673 | } else { | |
674 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
675 | OMAP2_MCSPI_CHSTAT_TXS); | |
676 | if (wait_res < 0) | |
677 | dev_err(&spi->dev, "TXS timed out\n"); | |
678 | } | |
679 | if (wait_res >= 0 && | |
680 | (mcspi_wait_for_reg_bit(chstat_reg, | |
681 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
682 | dev_err(&spi->dev, "EOT timed out\n"); |
683 | } | |
684 | } | |
ccdc7bf9 SO |
685 | return count; |
686 | } | |
687 | ||
ccdc7bf9 SO |
688 | static unsigned |
689 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
690 | { | |
691 | struct omap2_mcspi *mcspi; | |
692 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
693 | unsigned int count, c; | |
694 | u32 l; | |
695 | void __iomem *base = cs->base; | |
696 | void __iomem *tx_reg; | |
697 | void __iomem *rx_reg; | |
698 | void __iomem *chstat_reg; | |
699 | int word_len; | |
700 | ||
701 | mcspi = spi_master_get_devdata(spi->master); | |
702 | count = xfer->len; | |
703 | c = count; | |
704 | word_len = cs->word_len; | |
705 | ||
a41ae1ad | 706 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
707 | |
708 | /* We store the pre-calculated register addresses on stack to speed | |
709 | * up the transfer loop. */ | |
710 | tx_reg = base + OMAP2_MCSPI_TX0; | |
711 | rx_reg = base + OMAP2_MCSPI_RX0; | |
712 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
713 | ||
adef658d MJ |
714 | if (c < (word_len>>3)) |
715 | return 0; | |
716 | ||
ccdc7bf9 SO |
717 | if (word_len <= 8) { |
718 | u8 *rx; | |
719 | const u8 *tx; | |
720 | ||
721 | rx = xfer->rx_buf; | |
722 | tx = xfer->tx_buf; | |
723 | ||
724 | do { | |
feed9bab | 725 | c -= 1; |
ccdc7bf9 SO |
726 | if (tx != NULL) { |
727 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
728 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
729 | dev_err(&spi->dev, "TXS timed out\n"); | |
730 | goto out; | |
731 | } | |
079a176d | 732 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 733 | word_len, *tx); |
21b2ce5e | 734 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
735 | } |
736 | if (rx != NULL) { | |
737 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
738 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
739 | dev_err(&spi->dev, "RXS timed out\n"); | |
740 | goto out; | |
741 | } | |
4743a0f8 RT |
742 | |
743 | if (c == 1 && tx == NULL && | |
744 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
745 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 746 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 747 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 748 | word_len, *(rx - 1)); |
4743a0f8 RT |
749 | if (mcspi_wait_for_reg_bit(chstat_reg, |
750 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
751 | dev_err(&spi->dev, | |
752 | "RXS timed out\n"); | |
753 | goto out; | |
754 | } | |
755 | c = 0; | |
756 | } else if (c == 0 && tx == NULL) { | |
757 | omap2_mcspi_set_enable(spi, 0); | |
758 | } | |
759 | ||
21b2ce5e | 760 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 761 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 762 | word_len, *(rx - 1)); |
ccdc7bf9 | 763 | } |
95c5c3ab | 764 | } while (c); |
ccdc7bf9 SO |
765 | } else if (word_len <= 16) { |
766 | u16 *rx; | |
767 | const u16 *tx; | |
768 | ||
769 | rx = xfer->rx_buf; | |
770 | tx = xfer->tx_buf; | |
771 | do { | |
feed9bab | 772 | c -= 2; |
ccdc7bf9 SO |
773 | if (tx != NULL) { |
774 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
775 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
776 | dev_err(&spi->dev, "TXS timed out\n"); | |
777 | goto out; | |
778 | } | |
079a176d | 779 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 780 | word_len, *tx); |
21b2ce5e | 781 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
782 | } |
783 | if (rx != NULL) { | |
784 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
785 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
786 | dev_err(&spi->dev, "RXS timed out\n"); | |
787 | goto out; | |
788 | } | |
4743a0f8 RT |
789 | |
790 | if (c == 2 && tx == NULL && | |
791 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
792 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 793 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 794 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 795 | word_len, *(rx - 1)); |
4743a0f8 RT |
796 | if (mcspi_wait_for_reg_bit(chstat_reg, |
797 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
798 | dev_err(&spi->dev, | |
799 | "RXS timed out\n"); | |
800 | goto out; | |
801 | } | |
802 | c = 0; | |
803 | } else if (c == 0 && tx == NULL) { | |
804 | omap2_mcspi_set_enable(spi, 0); | |
805 | } | |
806 | ||
21b2ce5e | 807 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 808 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 809 | word_len, *(rx - 1)); |
ccdc7bf9 | 810 | } |
95c5c3ab | 811 | } while (c >= 2); |
ccdc7bf9 SO |
812 | } else if (word_len <= 32) { |
813 | u32 *rx; | |
814 | const u32 *tx; | |
815 | ||
816 | rx = xfer->rx_buf; | |
817 | tx = xfer->tx_buf; | |
818 | do { | |
feed9bab | 819 | c -= 4; |
ccdc7bf9 SO |
820 | if (tx != NULL) { |
821 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
822 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
823 | dev_err(&spi->dev, "TXS timed out\n"); | |
824 | goto out; | |
825 | } | |
079a176d | 826 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 827 | word_len, *tx); |
21b2ce5e | 828 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
829 | } |
830 | if (rx != NULL) { | |
831 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
832 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
833 | dev_err(&spi->dev, "RXS timed out\n"); | |
834 | goto out; | |
835 | } | |
4743a0f8 RT |
836 | |
837 | if (c == 4 && tx == NULL && | |
838 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
839 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 840 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 841 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 842 | word_len, *(rx - 1)); |
4743a0f8 RT |
843 | if (mcspi_wait_for_reg_bit(chstat_reg, |
844 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
845 | dev_err(&spi->dev, | |
846 | "RXS timed out\n"); | |
847 | goto out; | |
848 | } | |
849 | c = 0; | |
850 | } else if (c == 0 && tx == NULL) { | |
851 | omap2_mcspi_set_enable(spi, 0); | |
852 | } | |
853 | ||
21b2ce5e | 854 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 855 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 856 | word_len, *(rx - 1)); |
ccdc7bf9 | 857 | } |
95c5c3ab | 858 | } while (c >= 4); |
ccdc7bf9 SO |
859 | } |
860 | ||
861 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
862 | if (xfer->rx_buf == NULL) { | |
863 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
864 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
865 | dev_err(&spi->dev, "TXS timed out\n"); | |
866 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
867 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
868 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
869 | |
870 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
871 | * otherwise these rx datas will affect the direct following | |
872 | * RX_ONLY transfer. | |
873 | */ | |
874 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
875 | } |
876 | out: | |
4743a0f8 | 877 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
878 | return count - c; |
879 | } | |
880 | ||
57d9c10d HH |
881 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
882 | { | |
883 | u32 div; | |
884 | ||
885 | for (div = 0; div < 15; div++) | |
886 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
887 | return div; | |
888 | ||
889 | return 15; | |
890 | } | |
891 | ||
ccdc7bf9 SO |
892 | /* called only when no transfer is active to this device */ |
893 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
894 | struct spi_transfer *t) | |
895 | { | |
896 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
897 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 898 | struct spi_master *spi_cntrl; |
faee9b05 | 899 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 900 | u8 word_len = spi->bits_per_word; |
9bd4517d | 901 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
902 | |
903 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 904 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
905 | |
906 | if (t != NULL && t->bits_per_word) | |
907 | word_len = t->bits_per_word; | |
908 | ||
909 | cs->word_len = word_len; | |
910 | ||
9bd4517d SE |
911 | if (t && t->speed_hz) |
912 | speed_hz = t->speed_hz; | |
913 | ||
57d9c10d | 914 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
915 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
916 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
917 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
918 | clkg = 0; | |
919 | } else { | |
920 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
921 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
922 | clkd = (div - 1) & 0xf; | |
923 | extclk = (div - 1) >> 4; | |
924 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
925 | } | |
ccdc7bf9 | 926 | |
a41ae1ad | 927 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
928 | |
929 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
930 | * REVISIT: this controller could support SPI_3WIRE mode. | |
931 | */ | |
2cd45179 | 932 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
933 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
934 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
935 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
936 | } else { | |
937 | l |= OMAP2_MCSPI_CHCONF_IS; | |
938 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
939 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
940 | } | |
ccdc7bf9 SO |
941 | |
942 | /* wordlength */ | |
943 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
944 | l |= (word_len - 1) << 7; | |
945 | ||
946 | /* set chipselect polarity; manage with FORCE */ | |
947 | if (!(spi->mode & SPI_CS_HIGH)) | |
948 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
949 | else | |
950 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
951 | ||
952 | /* set clock divisor */ | |
953 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
954 | l |= clkd << 2; |
955 | ||
956 | /* set clock granularity */ | |
957 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
958 | l |= clkg; | |
959 | if (clkg) { | |
960 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
961 | cs->chctrl0 |= extclk << 8; | |
962 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
963 | } | |
ccdc7bf9 SO |
964 | |
965 | /* set SPI mode 0..3 */ | |
966 | if (spi->mode & SPI_CPOL) | |
967 | l |= OMAP2_MCSPI_CHCONF_POL; | |
968 | else | |
969 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
970 | if (spi->mode & SPI_CPHA) | |
971 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
972 | else | |
973 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
974 | ||
a41ae1ad | 975 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 976 | |
97ca0d6c MG |
977 | cs->mode = spi->mode; |
978 | ||
ccdc7bf9 | 979 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 980 | speed_hz, |
ccdc7bf9 SO |
981 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
982 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
ddc5cdf1 TL |
987 | /* |
988 | * Note that we currently allow DMA only if we get a channel | |
989 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
990 | */ | |
ccdc7bf9 SO |
991 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
992 | { | |
993 | struct spi_master *master = spi->master; | |
994 | struct omap2_mcspi *mcspi; | |
995 | struct omap2_mcspi_dma *mcspi_dma; | |
b085c612 | 996 | int ret = 0; |
ccdc7bf9 SO |
997 | |
998 | mcspi = spi_master_get_devdata(master); | |
999 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
1000 | ||
53741ed8 RK |
1001 | init_completion(&mcspi_dma->dma_rx_completion); |
1002 | init_completion(&mcspi_dma->dma_tx_completion); | |
1003 | ||
b085c612 PU |
1004 | mcspi_dma->dma_rx = dma_request_chan(&master->dev, |
1005 | mcspi_dma->dma_rx_ch_name); | |
1006 | if (IS_ERR(mcspi_dma->dma_rx)) { | |
1007 | ret = PTR_ERR(mcspi_dma->dma_rx); | |
1008 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 1009 | goto no_dma; |
b085c612 | 1010 | } |
ccdc7bf9 | 1011 | |
b085c612 PU |
1012 | mcspi_dma->dma_tx = dma_request_chan(&master->dev, |
1013 | mcspi_dma->dma_tx_ch_name); | |
1014 | if (IS_ERR(mcspi_dma->dma_tx)) { | |
1015 | ret = PTR_ERR(mcspi_dma->dma_tx); | |
1016 | mcspi_dma->dma_tx = NULL; | |
53741ed8 RK |
1017 | dma_release_channel(mcspi_dma->dma_rx); |
1018 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
1019 | } |
1020 | ||
ddc5cdf1 | 1021 | no_dma: |
b085c612 | 1022 | return ret; |
ccdc7bf9 SO |
1023 | } |
1024 | ||
ccdc7bf9 SO |
1025 | static int omap2_mcspi_setup(struct spi_device *spi) |
1026 | { | |
1027 | int ret; | |
1bd897f8 BC |
1028 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
1029 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
1030 | struct omap2_mcspi_dma *mcspi_dma; |
1031 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
1032 | ||
ccdc7bf9 SO |
1033 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
1034 | ||
1035 | if (!cs) { | |
10aa5a35 | 1036 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
1037 | if (!cs) |
1038 | return -ENOMEM; | |
1039 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1040 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1041 | cs->mode = 0; |
a41ae1ad | 1042 | cs->chconf0 = 0; |
faee9b05 | 1043 | cs->chctrl0 = 0; |
ccdc7bf9 | 1044 | spi->controller_state = cs; |
89c05372 | 1045 | /* Link this to context save list */ |
1bd897f8 | 1046 | list_add_tail(&cs->node, &ctx->cs); |
2f538c01 MW |
1047 | |
1048 | if (gpio_is_valid(spi->cs_gpio)) { | |
1049 | ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); | |
1050 | if (ret) { | |
1051 | dev_err(&spi->dev, "failed to request gpio\n"); | |
1052 | return ret; | |
1053 | } | |
1054 | gpio_direction_output(spi->cs_gpio, | |
1055 | !(spi->mode & SPI_CS_HIGH)); | |
1056 | } | |
ccdc7bf9 SO |
1057 | } |
1058 | ||
8c7494a5 | 1059 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1060 | ret = omap2_mcspi_request_dma(spi); |
b085c612 PU |
1061 | if (ret) |
1062 | dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", | |
1063 | ret); | |
ccdc7bf9 SO |
1064 | } |
1065 | ||
034d3dc9 | 1066 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1067 | if (ret < 0) |
1068 | return ret; | |
a41ae1ad | 1069 | |
86eeb6fe | 1070 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1071 | pm_runtime_mark_last_busy(mcspi->dev); |
1072 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1073 | |
1074 | return ret; | |
1075 | } | |
1076 | ||
1077 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1078 | { | |
1079 | struct omap2_mcspi *mcspi; | |
1080 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1081 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1082 | |
1083 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1084 | |
5e774943 SE |
1085 | if (spi->controller_state) { |
1086 | /* Unlink controller state from context save list */ | |
1087 | cs = spi->controller_state; | |
1088 | list_del(&cs->node); | |
89c05372 | 1089 | |
10aa5a35 | 1090 | kfree(cs); |
5e774943 | 1091 | } |
ccdc7bf9 | 1092 | |
99f1a43f SE |
1093 | if (spi->chip_select < spi->master->num_chipselect) { |
1094 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1095 | ||
53741ed8 RK |
1096 | if (mcspi_dma->dma_rx) { |
1097 | dma_release_channel(mcspi_dma->dma_rx); | |
1098 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1099 | } |
53741ed8 RK |
1100 | if (mcspi_dma->dma_tx) { |
1101 | dma_release_channel(mcspi_dma->dma_tx); | |
1102 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1103 | } |
ccdc7bf9 | 1104 | } |
bc7f9bbc MW |
1105 | |
1106 | if (gpio_is_valid(spi->cs_gpio)) | |
1107 | gpio_free(spi->cs_gpio); | |
ccdc7bf9 SO |
1108 | } |
1109 | ||
0ba1870f FCJ |
1110 | static int omap2_mcspi_transfer_one(struct spi_master *master, |
1111 | struct spi_device *spi, | |
1112 | struct spi_transfer *t) | |
ccdc7bf9 | 1113 | { |
ccdc7bf9 SO |
1114 | |
1115 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1116 | * -- although this controller would gladly |
ccdc7bf9 SO |
1117 | * arbitrate among multiple channels. This corresponds to "single |
1118 | * channel" master mode. As a side effect, we need to manage the | |
1119 | * chipselect with the FORCE bit ... CS != channel enable. | |
1120 | */ | |
ccdc7bf9 | 1121 | |
0ba1870f | 1122 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1123 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1124 | struct omap2_mcspi_cs *cs; |
1125 | struct omap2_mcspi_device_config *cd; | |
1126 | int par_override = 0; | |
1127 | int status = 0; | |
1128 | u32 chconf; | |
ccdc7bf9 | 1129 | |
0ba1870f | 1130 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1131 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1132 | cs = spi->controller_state; |
1133 | cd = spi->controller_data; | |
ccdc7bf9 | 1134 | |
97ca0d6c MG |
1135 | /* |
1136 | * The slave driver could have changed spi->mode in which case | |
1137 | * it will be different from cs->mode (the current hardware setup). | |
1138 | * If so, set par_override (even though its not a parity issue) so | |
1139 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1140 | * with the correct mode on the first iteration of the loop below. | |
1141 | */ | |
1142 | if (spi->mode != cs->mode) | |
1143 | par_override = 1; | |
1144 | ||
d33f473d | 1145 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 1146 | |
a06b430f MW |
1147 | if (gpio_is_valid(spi->cs_gpio)) |
1148 | omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); | |
1149 | ||
b28cb941 MW |
1150 | if (par_override || |
1151 | (t->speed_hz != spi->max_speed_hz) || | |
1152 | (t->bits_per_word != spi->bits_per_word)) { | |
1153 | par_override = 1; | |
1154 | status = omap2_mcspi_setup_transfer(spi, t); | |
1155 | if (status < 0) | |
1156 | goto out; | |
1157 | if (t->speed_hz == spi->max_speed_hz && | |
1158 | t->bits_per_word == spi->bits_per_word) | |
1159 | par_override = 0; | |
1160 | } | |
1161 | if (cd && cd->cs_per_word) { | |
1162 | chconf = mcspi->ctx.modulctrl; | |
1163 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1164 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1165 | mcspi->ctx.modulctrl = | |
1166 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1167 | } | |
4743a0f8 | 1168 | |
b28cb941 MW |
1169 | chconf = mcspi_cached_chconf0(spi); |
1170 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1171 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
1172 | ||
1173 | if (t->tx_buf == NULL) | |
1174 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1175 | else if (t->rx_buf == NULL) | |
1176 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
1177 | ||
1178 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
1179 | /* Turbo mode is for more than one word */ | |
1180 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1181 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1182 | } | |
ccdc7bf9 | 1183 | |
b28cb941 | 1184 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1185 | |
b28cb941 MW |
1186 | if (t->len) { |
1187 | unsigned count; | |
5fda88f5 | 1188 | |
b28cb941 | 1189 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
0ba1870f FCJ |
1190 | master->cur_msg_mapped && |
1191 | master->can_dma(master, spi, t)) | |
b28cb941 | 1192 | omap2_mcspi_set_fifo(spi, t, 1); |
d33f473d | 1193 | |
b28cb941 | 1194 | omap2_mcspi_set_enable(spi, 1); |
d33f473d | 1195 | |
b28cb941 MW |
1196 | /* RX_ONLY mode needs dummy data in TX reg */ |
1197 | if (t->tx_buf == NULL) | |
1198 | writel_relaxed(0, cs->base | |
1199 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1200 | |
b28cb941 | 1201 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
0ba1870f FCJ |
1202 | master->cur_msg_mapped && |
1203 | master->can_dma(master, spi, t)) | |
b28cb941 MW |
1204 | count = omap2_mcspi_txrx_dma(spi, t); |
1205 | else | |
1206 | count = omap2_mcspi_txrx_pio(spi, t); | |
ccdc7bf9 | 1207 | |
b28cb941 MW |
1208 | if (count != t->len) { |
1209 | status = -EIO; | |
1210 | goto out; | |
ccdc7bf9 | 1211 | } |
b28cb941 | 1212 | } |
ccdc7bf9 | 1213 | |
b28cb941 | 1214 | omap2_mcspi_set_enable(spi, 0); |
d33f473d | 1215 | |
b28cb941 MW |
1216 | if (mcspi->fifo_depth > 0) |
1217 | omap2_mcspi_set_fifo(spi, t, 0); | |
1218 | ||
1219 | out: | |
5fda88f5 S |
1220 | /* Restore defaults if they were overriden */ |
1221 | if (par_override) { | |
1222 | par_override = 0; | |
1223 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1224 | } | |
ccdc7bf9 | 1225 | |
5cbc7ca9 MB |
1226 | if (cd && cd->cs_per_word) { |
1227 | chconf = mcspi->ctx.modulctrl; | |
1228 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1229 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1230 | mcspi->ctx.modulctrl = | |
1231 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1232 | } | |
1233 | ||
5fda88f5 | 1234 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1235 | |
a06b430f MW |
1236 | if (gpio_is_valid(spi->cs_gpio)) |
1237 | omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); | |
1238 | ||
d33f473d IS |
1239 | if (mcspi->fifo_depth > 0 && t) |
1240 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1241 | |
b28cb941 | 1242 | return status; |
ccdc7bf9 SO |
1243 | } |
1244 | ||
468a3208 NA |
1245 | static int omap2_mcspi_prepare_message(struct spi_master *master, |
1246 | struct spi_message *msg) | |
1247 | { | |
1248 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1249 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
1250 | struct omap2_mcspi_cs *cs; | |
1251 | ||
1252 | /* Only a single channel can have the FORCE bit enabled | |
1253 | * in its chconf0 register. | |
1254 | * Scan all channels and disable them except the current one. | |
1255 | * A FORCE can remain from a last transfer having cs_change enabled | |
1256 | */ | |
1257 | list_for_each_entry(cs, &ctx->cs, node) { | |
1258 | if (msg->spi->controller_state == cs) | |
1259 | continue; | |
1260 | ||
1261 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { | |
1262 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
1263 | writel_relaxed(cs->chconf0, | |
1264 | cs->base + OMAP2_MCSPI_CHCONF0); | |
1265 | readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
0ba1870f FCJ |
1272 | static bool omap2_mcspi_can_dma(struct spi_master *master, |
1273 | struct spi_device *spi, | |
1274 | struct spi_transfer *xfer) | |
ccdc7bf9 | 1275 | { |
0ba1870f | 1276 | return (xfer->len >= DMA_MIN_BYTES); |
ccdc7bf9 SO |
1277 | } |
1278 | ||
fd4a319b | 1279 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1280 | { |
1281 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1282 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1283 | int ret = 0; |
ccdc7bf9 | 1284 | |
034d3dc9 | 1285 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1286 | if (ret < 0) |
1287 | return ret; | |
ddb22195 | 1288 | |
39f8052d | 1289 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1290 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1291 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1292 | |
1293 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1294 | pm_runtime_mark_last_busy(mcspi->dev); |
1295 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1296 | return 0; |
1297 | } | |
1298 | ||
1f1a4384 G |
1299 | static int omap_mcspi_runtime_resume(struct device *dev) |
1300 | { | |
1301 | struct omap2_mcspi *mcspi; | |
1302 | struct spi_master *master; | |
1303 | ||
1304 | master = dev_get_drvdata(dev); | |
1305 | mcspi = spi_master_get_devdata(master); | |
1306 | omap2_mcspi_restore_ctx(mcspi); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
d5a80031 BC |
1311 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1312 | .regs_offset = 0, | |
1313 | }; | |
1314 | ||
1315 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1316 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1317 | }; | |
1318 | ||
1319 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1320 | { | |
1321 | .compatible = "ti,omap2-mcspi", | |
1322 | .data = &omap2_pdata, | |
1323 | }, | |
1324 | { | |
1325 | .compatible = "ti,omap4-mcspi", | |
1326 | .data = &omap4_pdata, | |
1327 | }, | |
1328 | { }, | |
1329 | }; | |
1330 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1331 | |
fd4a319b | 1332 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1333 | { |
1334 | struct spi_master *master; | |
83a01e72 | 1335 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1336 | struct omap2_mcspi *mcspi; |
1337 | struct resource *r; | |
1338 | int status = 0, i; | |
d5a80031 BC |
1339 | u32 regs_offset = 0; |
1340 | static int bus_num = 1; | |
1341 | struct device_node *node = pdev->dev.of_node; | |
1342 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1343 | |
1344 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1345 | if (master == NULL) { | |
1346 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1347 | return -ENOMEM; | |
1348 | } | |
1349 | ||
e7db06b5 DB |
1350 | /* the spi->mode bits understood by this driver: */ |
1351 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1352 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1353 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1354 | master->auto_runtime_pm = true; |
468a3208 | 1355 | master->prepare_message = omap2_mcspi_prepare_message; |
0ba1870f | 1356 | master->can_dma = omap2_mcspi_can_dma; |
b28cb941 | 1357 | master->transfer_one = omap2_mcspi_transfer_one; |
ddcad7e9 | 1358 | master->set_cs = omap2_mcspi_set_cs; |
ccdc7bf9 | 1359 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1360 | master->dev.of_node = node; |
aca0924b AL |
1361 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1362 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1363 | |
24b5a82c | 1364 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1365 | |
1366 | mcspi = spi_master_get_devdata(master); | |
1367 | mcspi->master = master; | |
1368 | ||
d5a80031 BC |
1369 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1370 | if (match) { | |
1371 | u32 num_cs = 1; /* default number of chipselect */ | |
1372 | pdata = match->data; | |
1373 | ||
1374 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1375 | master->num_chipselect = num_cs; | |
1376 | master->bus_num = bus_num++; | |
2cd45179 DM |
1377 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1378 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1379 | } else { |
8074cf06 | 1380 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1381 | master->num_chipselect = pdata->num_cs; |
1382 | if (pdev->id != -1) | |
1383 | master->bus_num = pdev->id; | |
0384e90b | 1384 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1385 | } |
1386 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1387 | |
ccdc7bf9 SO |
1388 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1389 | if (r == NULL) { | |
1390 | status = -ENODEV; | |
39f1b565 | 1391 | goto free_master; |
ccdc7bf9 | 1392 | } |
1458d160 | 1393 | |
d5a80031 BC |
1394 | r->start += regs_offset; |
1395 | r->end += regs_offset; | |
1458d160 | 1396 | mcspi->phys = r->start; |
ccdc7bf9 | 1397 | |
b0ee5605 TR |
1398 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1399 | if (IS_ERR(mcspi->base)) { | |
1400 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1401 | goto free_master; |
55c381e4 | 1402 | } |
ccdc7bf9 | 1403 | |
1f1a4384 | 1404 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1405 | |
1bd897f8 | 1406 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1407 | |
a6f936db AL |
1408 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1409 | sizeof(struct omap2_mcspi_dma), | |
1410 | GFP_KERNEL); | |
1411 | if (mcspi->dma_channels == NULL) { | |
1412 | status = -ENOMEM; | |
1a77b127 | 1413 | goto free_master; |
a6f936db | 1414 | } |
ccdc7bf9 | 1415 | |
1a5d8190 | 1416 | for (i = 0; i < master->num_chipselect; i++) { |
b085c612 PU |
1417 | sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); |
1418 | sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); | |
ccdc7bf9 SO |
1419 | } |
1420 | ||
39f1b565 | 1421 | if (status < 0) |
a6f936db | 1422 | goto free_master; |
39f1b565 | 1423 | |
27b5284c S |
1424 | pm_runtime_use_autosuspend(&pdev->dev); |
1425 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1426 | pm_runtime_enable(&pdev->dev); |
1427 | ||
142e07be WY |
1428 | status = omap2_mcspi_master_setup(mcspi); |
1429 | if (status < 0) | |
39f1b565 | 1430 | goto disable_pm; |
ccdc7bf9 | 1431 | |
b95e02b7 | 1432 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1433 | if (status < 0) |
37a2d84a | 1434 | goto disable_pm; |
ccdc7bf9 SO |
1435 | |
1436 | return status; | |
1437 | ||
39f1b565 | 1438 | disable_pm: |
0e6f357a TL |
1439 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1440 | pm_runtime_put_sync(&pdev->dev); | |
751c925c | 1441 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1442 | free_master: |
37a2d84a | 1443 | spi_master_put(master); |
ccdc7bf9 SO |
1444 | return status; |
1445 | } | |
1446 | ||
fd4a319b | 1447 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1448 | { |
a6f936db AL |
1449 | struct spi_master *master = platform_get_drvdata(pdev); |
1450 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1451 | |
0e6f357a | 1452 | pm_runtime_dont_use_autosuspend(mcspi->dev); |
a93a2029 | 1453 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1454 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1455 | |
ccdc7bf9 SO |
1456 | return 0; |
1457 | } | |
1458 | ||
7e38c3c4 KS |
1459 | /* work with hotplug and coldplug */ |
1460 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1461 | ||
42ce7fd6 GC |
1462 | #ifdef CONFIG_SUSPEND |
1463 | /* | |
1464 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1465 | * unactive state when driver was suspend, then force it to unactive state at | |
1466 | * wake up. | |
1467 | */ | |
1468 | static int omap2_mcspi_resume(struct device *dev) | |
1469 | { | |
1470 | struct spi_master *master = dev_get_drvdata(dev); | |
1471 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1472 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1473 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1474 | |
034d3dc9 | 1475 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1476 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1477 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1478 | /* |
1479 | * We need to toggle CS state for OMAP take this | |
1480 | * change in account. | |
1481 | */ | |
af4e944d | 1482 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1483 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1484 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1485 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1486 | } |
1487 | } | |
034d3dc9 S |
1488 | pm_runtime_mark_last_busy(mcspi->dev); |
1489 | pm_runtime_put_autosuspend(mcspi->dev); | |
beca3655 PH |
1490 | |
1491 | return pinctrl_pm_select_default_state(dev); | |
1492 | } | |
1493 | ||
1494 | static int omap2_mcspi_suspend(struct device *dev) | |
1495 | { | |
1496 | return pinctrl_pm_select_sleep_state(dev); | |
42ce7fd6 | 1497 | } |
beca3655 | 1498 | |
42ce7fd6 | 1499 | #else |
beca3655 | 1500 | #define omap2_mcspi_suspend NULL |
42ce7fd6 GC |
1501 | #define omap2_mcspi_resume NULL |
1502 | #endif | |
1503 | ||
1504 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1505 | .resume = omap2_mcspi_resume, | |
beca3655 | 1506 | .suspend = omap2_mcspi_suspend, |
1f1a4384 | 1507 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1508 | }; |
1509 | ||
ccdc7bf9 SO |
1510 | static struct platform_driver omap2_mcspi_driver = { |
1511 | .driver = { | |
1512 | .name = "omap2_mcspi", | |
d5a80031 BC |
1513 | .pm = &omap2_mcspi_pm_ops, |
1514 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1515 | }, |
7d6b6d83 | 1516 | .probe = omap2_mcspi_probe, |
fd4a319b | 1517 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1518 | }; |
1519 | ||
9fdca9df | 1520 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1521 | MODULE_LICENSE("GPL"); |