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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
27 | #include <linux/platform_device.h> |
28 | #include <linux/err.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
1f1a4384 | 32 | #include <linux/pm_runtime.h> |
d5a80031 BC |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
d33f473d | 35 | #include <linux/gcd.h> |
ccdc7bf9 SO |
36 | |
37 | #include <linux/spi/spi.h> | |
bc7f9bbc | 38 | #include <linux/gpio.h> |
ccdc7bf9 | 39 | |
2203747c | 40 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
41 | |
42 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 43 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
44 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
45 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 46 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
49 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
50 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
51 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
52 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
53 | #define OMAP2_MCSPI_SYST 0x24 | |
54 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 55 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
56 | |
57 | /* per-channel banks, 0x14 bytes each, first is: */ | |
58 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
59 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
60 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
61 | #define OMAP2_MCSPI_TX0 0x38 | |
62 | #define OMAP2_MCSPI_RX0 0x3c | |
63 | ||
64 | /* per-register bitmasks: */ | |
d33f473d | 65 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 66 | |
7a8fa725 JH |
67 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
68 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
69 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
72 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 73 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 74 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 75 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
76 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
77 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 78 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
79 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
80 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
81 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
83 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
84 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
85 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
86 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
87 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 88 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 89 | |
7a8fa725 JH |
90 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
91 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
92 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 93 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 94 | |
7a8fa725 | 95 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 96 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 97 | |
7a8fa725 | 98 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
99 | |
100 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
101 | struct omap2_mcspi_dma { | |
53741ed8 RK |
102 | struct dma_chan *dma_tx; |
103 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
104 | |
105 | int dma_tx_sync_dev; | |
106 | int dma_rx_sync_dev; | |
107 | ||
108 | struct completion dma_tx_completion; | |
109 | struct completion dma_rx_completion; | |
74f3aaad MP |
110 | |
111 | char dma_rx_ch_name[14]; | |
112 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
113 | }; |
114 | ||
115 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
116 | * cache operations; better heuristics consider wordsize and bitrate. | |
117 | */ | |
8b66c134 | 118 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
119 | |
120 | ||
1bd897f8 BC |
121 | /* |
122 | * Used for context save and restore, structure members to be updated whenever | |
123 | * corresponding registers are modified. | |
124 | */ | |
125 | struct omap2_mcspi_regs { | |
126 | u32 modulctrl; | |
127 | u32 wakeupenable; | |
128 | struct list_head cs; | |
129 | }; | |
130 | ||
ccdc7bf9 | 131 | struct omap2_mcspi { |
ccdc7bf9 | 132 | struct spi_master *master; |
ccdc7bf9 SO |
133 | /* Virtual base address of the controller */ |
134 | void __iomem *base; | |
e5480b73 | 135 | unsigned long phys; |
ccdc7bf9 SO |
136 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
137 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 138 | struct device *dev; |
1bd897f8 | 139 | struct omap2_mcspi_regs ctx; |
d33f473d | 140 | int fifo_depth; |
0384e90b | 141 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
142 | }; |
143 | ||
144 | struct omap2_mcspi_cs { | |
145 | void __iomem *base; | |
e5480b73 | 146 | unsigned long phys; |
ccdc7bf9 | 147 | int word_len; |
97ca0d6c | 148 | u16 mode; |
89c05372 | 149 | struct list_head node; |
a41ae1ad | 150 | /* Context save and restore shadow register */ |
faee9b05 | 151 | u32 chconf0, chctrl0; |
a41ae1ad H |
152 | }; |
153 | ||
ccdc7bf9 SO |
154 | static inline void mcspi_write_reg(struct spi_master *master, |
155 | int idx, u32 val) | |
156 | { | |
157 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
158 | ||
21b2ce5e | 159 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
160 | } |
161 | ||
162 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
163 | { | |
164 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
165 | ||
21b2ce5e | 166 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
167 | } |
168 | ||
169 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
170 | int idx, u32 val) | |
171 | { | |
172 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
173 | ||
21b2ce5e | 174 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
175 | } |
176 | ||
177 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
178 | { | |
179 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
180 | ||
21b2ce5e | 181 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
182 | } |
183 | ||
a41ae1ad H |
184 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
185 | { | |
186 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
187 | ||
188 | return cs->chconf0; | |
189 | } | |
190 | ||
191 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
192 | { | |
193 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
194 | ||
195 | cs->chconf0 = val; | |
196 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 197 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
198 | } |
199 | ||
56cd5c15 IS |
200 | static inline int mcspi_bytes_per_word(int word_len) |
201 | { | |
202 | if (word_len <= 8) | |
203 | return 1; | |
204 | else if (word_len <= 16) | |
205 | return 2; | |
206 | else /* word_len <= 32 */ | |
207 | return 4; | |
208 | } | |
209 | ||
ccdc7bf9 SO |
210 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
211 | int is_read, int enable) | |
212 | { | |
213 | u32 l, rw; | |
214 | ||
a41ae1ad | 215 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
216 | |
217 | if (is_read) /* 1 is read, 0 write */ | |
218 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
219 | else | |
220 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
221 | ||
af4e944d S |
222 | if (enable) |
223 | l |= rw; | |
224 | else | |
225 | l &= ~rw; | |
226 | ||
a41ae1ad | 227 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
228 | } |
229 | ||
230 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
231 | { | |
faee9b05 | 232 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
233 | u32 l; |
234 | ||
faee9b05 SS |
235 | l = cs->chctrl0; |
236 | if (enable) | |
237 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
238 | else | |
239 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
240 | cs->chctrl0 = l; | |
241 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
242 | /* Flash post-writes */ |
243 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
244 | } |
245 | ||
ddcad7e9 | 246 | static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) |
ccdc7bf9 SO |
247 | { |
248 | u32 l; | |
249 | ||
4373f8b6 MW |
250 | /* The controller handles the inverted chip selects |
251 | * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert | |
252 | * the inversion from the core spi_set_cs function. | |
253 | */ | |
254 | if (spi->mode & SPI_CS_HIGH) | |
255 | enable = !enable; | |
256 | ||
ddcad7e9 MW |
257 | if (spi->controller_state) { |
258 | l = mcspi_cached_chconf0(spi); | |
af4e944d | 259 | |
ddcad7e9 MW |
260 | if (enable) |
261 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
262 | else | |
263 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
264 | ||
265 | mcspi_write_chconf0(spi, l); | |
266 | } | |
ccdc7bf9 SO |
267 | } |
268 | ||
269 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
270 | { | |
1bd897f8 BC |
271 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
272 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
273 | u32 l; |
274 | ||
1bd897f8 BC |
275 | /* |
276 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
277 | * to single-channel master mode |
278 | */ | |
279 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
280 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
281 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 282 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 283 | |
1bd897f8 | 284 | ctx->modulctrl = l; |
a41ae1ad H |
285 | } |
286 | ||
d33f473d IS |
287 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
288 | struct spi_transfer *t, int enable) | |
289 | { | |
290 | struct spi_master *master = spi->master; | |
291 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
292 | struct omap2_mcspi *mcspi; | |
293 | unsigned int wcnt; | |
5db542ed | 294 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
295 | u32 chconf, xferlevel; |
296 | ||
297 | mcspi = spi_master_get_devdata(master); | |
298 | ||
299 | chconf = mcspi_cached_chconf0(spi); | |
300 | if (enable) { | |
301 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
302 | if (t->len % bytes_per_word != 0) | |
303 | goto disable_fifo; | |
304 | ||
5db542ed IS |
305 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
306 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
307 | else | |
308 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
309 | ||
310 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
311 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
312 | goto disable_fifo; | |
313 | ||
314 | wcnt = t->len / bytes_per_word; | |
315 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
316 | goto disable_fifo; | |
317 | ||
318 | xferlevel = wcnt << 16; | |
319 | if (t->rx_buf != NULL) { | |
320 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
321 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
322 | } |
323 | if (t->tx_buf != NULL) { | |
d33f473d IS |
324 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
325 | xferlevel |= fifo_depth - 1; | |
326 | } | |
327 | ||
328 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
329 | mcspi_write_chconf0(spi, chconf); | |
330 | mcspi->fifo_depth = fifo_depth; | |
331 | ||
332 | return; | |
333 | } | |
334 | ||
335 | disable_fifo: | |
336 | if (t->rx_buf != NULL) | |
337 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
338 | |
339 | if (t->tx_buf != NULL) | |
d33f473d IS |
340 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
341 | ||
342 | mcspi_write_chconf0(spi, chconf); | |
343 | mcspi->fifo_depth = 0; | |
344 | } | |
345 | ||
a41ae1ad H |
346 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
347 | { | |
1bd897f8 BC |
348 | struct spi_master *spi_cntrl = mcspi->master; |
349 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
350 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
351 | |
352 | /* McSPI: context restore */ | |
1bd897f8 BC |
353 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
354 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 355 | |
1bd897f8 | 356 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 357 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 358 | } |
ccdc7bf9 | 359 | |
2764c500 IK |
360 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
361 | { | |
362 | unsigned long timeout; | |
363 | ||
364 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 365 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 366 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 367 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
368 | return -ETIMEDOUT; |
369 | else | |
370 | return 0; | |
371 | } | |
2764c500 IK |
372 | cpu_relax(); |
373 | } | |
374 | return 0; | |
375 | } | |
376 | ||
53741ed8 RK |
377 | static void omap2_mcspi_rx_callback(void *data) |
378 | { | |
379 | struct spi_device *spi = data; | |
380 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
381 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
382 | ||
53741ed8 RK |
383 | /* We must disable the DMA RX request */ |
384 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
385 | |
386 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
387 | } |
388 | ||
389 | static void omap2_mcspi_tx_callback(void *data) | |
390 | { | |
391 | struct spi_device *spi = data; | |
392 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
393 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
394 | ||
53741ed8 RK |
395 | /* We must disable the DMA TX request */ |
396 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
397 | |
398 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
399 | } |
400 | ||
d7b4394e S |
401 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
402 | struct spi_transfer *xfer, | |
403 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
404 | { |
405 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 406 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 407 | unsigned int count; |
ccdc7bf9 SO |
408 | |
409 | mcspi = spi_master_get_devdata(spi->master); | |
410 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 411 | count = xfer->len; |
ccdc7bf9 | 412 | |
d7b4394e | 413 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
414 | struct dma_async_tx_descriptor *tx; |
415 | struct scatterlist sg; | |
416 | ||
417 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
418 | ||
419 | sg_init_table(&sg, 1); | |
420 | sg_dma_address(&sg) = xfer->tx_dma; | |
421 | sg_dma_len(&sg) = xfer->len; | |
422 | ||
423 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 424 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
425 | if (tx) { |
426 | tx->callback = omap2_mcspi_tx_callback; | |
427 | tx->callback_param = spi; | |
428 | dmaengine_submit(tx); | |
429 | } else { | |
430 | /* FIXME: fall back to PIO? */ | |
431 | } | |
432 | } | |
d7b4394e S |
433 | dma_async_issue_pending(mcspi_dma->dma_tx); |
434 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
435 | ||
d7b4394e | 436 | } |
53741ed8 | 437 | |
d7b4394e S |
438 | static unsigned |
439 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
440 | struct dma_slave_config cfg, | |
441 | unsigned es) | |
442 | { | |
443 | struct omap2_mcspi *mcspi; | |
444 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 445 | unsigned int count, dma_count; |
d7b4394e S |
446 | u32 l; |
447 | int elements = 0; | |
448 | int word_len, element_count; | |
449 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
450 | mcspi = spi_master_get_devdata(spi->master); | |
451 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
452 | count = xfer->len; | |
d33f473d IS |
453 | dma_count = xfer->len; |
454 | ||
455 | if (mcspi->fifo_depth == 0) | |
456 | dma_count -= es; | |
457 | ||
d7b4394e S |
458 | word_len = cs->word_len; |
459 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 460 | |
d7b4394e S |
461 | if (word_len <= 8) |
462 | element_count = count; | |
463 | else if (word_len <= 16) | |
464 | element_count = count >> 1; | |
465 | else /* word_len <= 32 */ | |
466 | element_count = count >> 2; | |
467 | ||
468 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
469 | struct dma_async_tx_descriptor *tx; |
470 | struct scatterlist sg; | |
53741ed8 RK |
471 | |
472 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
473 | ||
d33f473d IS |
474 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
475 | dma_count -= es; | |
53741ed8 RK |
476 | |
477 | sg_init_table(&sg, 1); | |
478 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 479 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
480 | |
481 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
482 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
483 | DMA_CTRL_ACK); | |
53741ed8 RK |
484 | if (tx) { |
485 | tx->callback = omap2_mcspi_rx_callback; | |
486 | tx->callback_param = spi; | |
487 | dmaengine_submit(tx); | |
488 | } else { | |
d7b4394e | 489 | /* FIXME: fall back to PIO? */ |
2764c500 | 490 | } |
ccdc7bf9 SO |
491 | } |
492 | ||
d7b4394e S |
493 | dma_async_issue_pending(mcspi_dma->dma_rx); |
494 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 495 | |
d7b4394e S |
496 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
497 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
498 | DMA_FROM_DEVICE); | |
d33f473d IS |
499 | |
500 | if (mcspi->fifo_depth > 0) | |
501 | return count; | |
502 | ||
d7b4394e | 503 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 504 | |
d7b4394e | 505 | elements = element_count - 1; |
4743a0f8 | 506 | |
d7b4394e S |
507 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
508 | elements--; | |
4743a0f8 | 509 | |
57c5c28d | 510 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 511 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
512 | u32 w; |
513 | ||
514 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
515 | if (word_len <= 8) | |
d7b4394e | 516 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 517 | else if (word_len <= 16) |
d7b4394e | 518 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 519 | else /* word_len <= 32 */ |
d7b4394e | 520 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 521 | } else { |
56cd5c15 | 522 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 523 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 524 | count -= (bytes_per_word << 1); |
d7b4394e S |
525 | omap2_mcspi_set_enable(spi, 1); |
526 | return count; | |
57c5c28d | 527 | } |
ccdc7bf9 | 528 | } |
d7b4394e S |
529 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
530 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
531 | u32 w; | |
532 | ||
533 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
534 | if (word_len <= 8) | |
535 | ((u8 *)xfer->rx_buf)[elements] = w; | |
536 | else if (word_len <= 16) | |
537 | ((u16 *)xfer->rx_buf)[elements] = w; | |
538 | else /* word_len <= 32 */ | |
539 | ((u32 *)xfer->rx_buf)[elements] = w; | |
540 | } else { | |
a1829d2b | 541 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 542 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
543 | } |
544 | omap2_mcspi_set_enable(spi, 1); | |
545 | return count; | |
546 | } | |
547 | ||
548 | static unsigned | |
549 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
550 | { | |
551 | struct omap2_mcspi *mcspi; | |
552 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
553 | struct omap2_mcspi_dma *mcspi_dma; | |
554 | unsigned int count; | |
555 | u32 l; | |
556 | u8 *rx; | |
557 | const u8 *tx; | |
558 | struct dma_slave_config cfg; | |
559 | enum dma_slave_buswidth width; | |
560 | unsigned es; | |
d33f473d | 561 | u32 burst; |
e47a682a | 562 | void __iomem *chstat_reg; |
d33f473d IS |
563 | void __iomem *irqstat_reg; |
564 | int wait_res; | |
d7b4394e S |
565 | |
566 | mcspi = spi_master_get_devdata(spi->master); | |
567 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
568 | l = mcspi_cached_chconf0(spi); | |
569 | ||
570 | ||
571 | if (cs->word_len <= 8) { | |
572 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
573 | es = 1; | |
574 | } else if (cs->word_len <= 16) { | |
575 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
576 | es = 2; | |
577 | } else { | |
578 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
579 | es = 4; | |
580 | } | |
581 | ||
d33f473d IS |
582 | count = xfer->len; |
583 | burst = 1; | |
584 | ||
585 | if (mcspi->fifo_depth > 0) { | |
586 | if (count > mcspi->fifo_depth) | |
587 | burst = mcspi->fifo_depth / es; | |
588 | else | |
589 | burst = count / es; | |
590 | } | |
591 | ||
d7b4394e S |
592 | memset(&cfg, 0, sizeof(cfg)); |
593 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
594 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
595 | cfg.src_addr_width = width; | |
596 | cfg.dst_addr_width = width; | |
d33f473d IS |
597 | cfg.src_maxburst = burst; |
598 | cfg.dst_maxburst = burst; | |
d7b4394e S |
599 | |
600 | rx = xfer->rx_buf; | |
601 | tx = xfer->tx_buf; | |
602 | ||
d7b4394e S |
603 | if (tx != NULL) |
604 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
605 | ||
606 | if (rx != NULL) | |
e47a682a S |
607 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
608 | ||
609 | if (tx != NULL) { | |
e47a682a S |
610 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
611 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
612 | DMA_TO_DEVICE); | |
613 | ||
d33f473d IS |
614 | if (mcspi->fifo_depth > 0) { |
615 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
616 | ||
617 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
618 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
619 | dev_err(&spi->dev, "EOW timed out\n"); | |
620 | ||
621 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
622 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
623 | } | |
624 | ||
e47a682a S |
625 | /* for TX_ONLY mode, be sure all words have shifted out */ |
626 | if (rx == NULL) { | |
d33f473d IS |
627 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
628 | if (mcspi->fifo_depth > 0) { | |
629 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
630 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
631 | if (wait_res < 0) | |
632 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
633 | } else { | |
634 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
635 | OMAP2_MCSPI_CHSTAT_TXS); | |
636 | if (wait_res < 0) | |
637 | dev_err(&spi->dev, "TXS timed out\n"); | |
638 | } | |
639 | if (wait_res >= 0 && | |
640 | (mcspi_wait_for_reg_bit(chstat_reg, | |
641 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
642 | dev_err(&spi->dev, "EOT timed out\n"); |
643 | } | |
644 | } | |
ccdc7bf9 SO |
645 | return count; |
646 | } | |
647 | ||
ccdc7bf9 SO |
648 | static unsigned |
649 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
650 | { | |
651 | struct omap2_mcspi *mcspi; | |
652 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
653 | unsigned int count, c; | |
654 | u32 l; | |
655 | void __iomem *base = cs->base; | |
656 | void __iomem *tx_reg; | |
657 | void __iomem *rx_reg; | |
658 | void __iomem *chstat_reg; | |
659 | int word_len; | |
660 | ||
661 | mcspi = spi_master_get_devdata(spi->master); | |
662 | count = xfer->len; | |
663 | c = count; | |
664 | word_len = cs->word_len; | |
665 | ||
a41ae1ad | 666 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
667 | |
668 | /* We store the pre-calculated register addresses on stack to speed | |
669 | * up the transfer loop. */ | |
670 | tx_reg = base + OMAP2_MCSPI_TX0; | |
671 | rx_reg = base + OMAP2_MCSPI_RX0; | |
672 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
673 | ||
adef658d MJ |
674 | if (c < (word_len>>3)) |
675 | return 0; | |
676 | ||
ccdc7bf9 SO |
677 | if (word_len <= 8) { |
678 | u8 *rx; | |
679 | const u8 *tx; | |
680 | ||
681 | rx = xfer->rx_buf; | |
682 | tx = xfer->tx_buf; | |
683 | ||
684 | do { | |
feed9bab | 685 | c -= 1; |
ccdc7bf9 SO |
686 | if (tx != NULL) { |
687 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
688 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
689 | dev_err(&spi->dev, "TXS timed out\n"); | |
690 | goto out; | |
691 | } | |
079a176d | 692 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 693 | word_len, *tx); |
21b2ce5e | 694 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
695 | } |
696 | if (rx != NULL) { | |
697 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
698 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
699 | dev_err(&spi->dev, "RXS timed out\n"); | |
700 | goto out; | |
701 | } | |
4743a0f8 RT |
702 | |
703 | if (c == 1 && tx == NULL && | |
704 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
705 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 706 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 707 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 708 | word_len, *(rx - 1)); |
4743a0f8 RT |
709 | if (mcspi_wait_for_reg_bit(chstat_reg, |
710 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
711 | dev_err(&spi->dev, | |
712 | "RXS timed out\n"); | |
713 | goto out; | |
714 | } | |
715 | c = 0; | |
716 | } else if (c == 0 && tx == NULL) { | |
717 | omap2_mcspi_set_enable(spi, 0); | |
718 | } | |
719 | ||
21b2ce5e | 720 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 721 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 722 | word_len, *(rx - 1)); |
ccdc7bf9 | 723 | } |
95c5c3ab | 724 | } while (c); |
ccdc7bf9 SO |
725 | } else if (word_len <= 16) { |
726 | u16 *rx; | |
727 | const u16 *tx; | |
728 | ||
729 | rx = xfer->rx_buf; | |
730 | tx = xfer->tx_buf; | |
731 | do { | |
feed9bab | 732 | c -= 2; |
ccdc7bf9 SO |
733 | if (tx != NULL) { |
734 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
735 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
736 | dev_err(&spi->dev, "TXS timed out\n"); | |
737 | goto out; | |
738 | } | |
079a176d | 739 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 740 | word_len, *tx); |
21b2ce5e | 741 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
742 | } |
743 | if (rx != NULL) { | |
744 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
745 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
746 | dev_err(&spi->dev, "RXS timed out\n"); | |
747 | goto out; | |
748 | } | |
4743a0f8 RT |
749 | |
750 | if (c == 2 && tx == NULL && | |
751 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
752 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 753 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 754 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 755 | word_len, *(rx - 1)); |
4743a0f8 RT |
756 | if (mcspi_wait_for_reg_bit(chstat_reg, |
757 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
758 | dev_err(&spi->dev, | |
759 | "RXS timed out\n"); | |
760 | goto out; | |
761 | } | |
762 | c = 0; | |
763 | } else if (c == 0 && tx == NULL) { | |
764 | omap2_mcspi_set_enable(spi, 0); | |
765 | } | |
766 | ||
21b2ce5e | 767 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 768 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 769 | word_len, *(rx - 1)); |
ccdc7bf9 | 770 | } |
95c5c3ab | 771 | } while (c >= 2); |
ccdc7bf9 SO |
772 | } else if (word_len <= 32) { |
773 | u32 *rx; | |
774 | const u32 *tx; | |
775 | ||
776 | rx = xfer->rx_buf; | |
777 | tx = xfer->tx_buf; | |
778 | do { | |
feed9bab | 779 | c -= 4; |
ccdc7bf9 SO |
780 | if (tx != NULL) { |
781 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
782 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
783 | dev_err(&spi->dev, "TXS timed out\n"); | |
784 | goto out; | |
785 | } | |
079a176d | 786 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 787 | word_len, *tx); |
21b2ce5e | 788 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
789 | } |
790 | if (rx != NULL) { | |
791 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
792 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
793 | dev_err(&spi->dev, "RXS timed out\n"); | |
794 | goto out; | |
795 | } | |
4743a0f8 RT |
796 | |
797 | if (c == 4 && tx == NULL && | |
798 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
799 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 800 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 801 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 802 | word_len, *(rx - 1)); |
4743a0f8 RT |
803 | if (mcspi_wait_for_reg_bit(chstat_reg, |
804 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
805 | dev_err(&spi->dev, | |
806 | "RXS timed out\n"); | |
807 | goto out; | |
808 | } | |
809 | c = 0; | |
810 | } else if (c == 0 && tx == NULL) { | |
811 | omap2_mcspi_set_enable(spi, 0); | |
812 | } | |
813 | ||
21b2ce5e | 814 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 815 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 816 | word_len, *(rx - 1)); |
ccdc7bf9 | 817 | } |
95c5c3ab | 818 | } while (c >= 4); |
ccdc7bf9 SO |
819 | } |
820 | ||
821 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
822 | if (xfer->rx_buf == NULL) { | |
823 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
824 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
825 | dev_err(&spi->dev, "TXS timed out\n"); | |
826 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
827 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
828 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
829 | |
830 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
831 | * otherwise these rx datas will affect the direct following | |
832 | * RX_ONLY transfer. | |
833 | */ | |
834 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
835 | } |
836 | out: | |
4743a0f8 | 837 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
838 | return count - c; |
839 | } | |
840 | ||
57d9c10d HH |
841 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
842 | { | |
843 | u32 div; | |
844 | ||
845 | for (div = 0; div < 15; div++) | |
846 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
847 | return div; | |
848 | ||
849 | return 15; | |
850 | } | |
851 | ||
ccdc7bf9 SO |
852 | /* called only when no transfer is active to this device */ |
853 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
854 | struct spi_transfer *t) | |
855 | { | |
856 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
857 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 858 | struct spi_master *spi_cntrl; |
faee9b05 | 859 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 860 | u8 word_len = spi->bits_per_word; |
9bd4517d | 861 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
862 | |
863 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 864 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
865 | |
866 | if (t != NULL && t->bits_per_word) | |
867 | word_len = t->bits_per_word; | |
868 | ||
869 | cs->word_len = word_len; | |
870 | ||
9bd4517d SE |
871 | if (t && t->speed_hz) |
872 | speed_hz = t->speed_hz; | |
873 | ||
57d9c10d | 874 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
875 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
876 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
877 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
878 | clkg = 0; | |
879 | } else { | |
880 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
881 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
882 | clkd = (div - 1) & 0xf; | |
883 | extclk = (div - 1) >> 4; | |
884 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
885 | } | |
ccdc7bf9 | 886 | |
a41ae1ad | 887 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
888 | |
889 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
890 | * REVISIT: this controller could support SPI_3WIRE mode. | |
891 | */ | |
2cd45179 | 892 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
893 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
894 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
895 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
896 | } else { | |
897 | l |= OMAP2_MCSPI_CHCONF_IS; | |
898 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
899 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
900 | } | |
ccdc7bf9 SO |
901 | |
902 | /* wordlength */ | |
903 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
904 | l |= (word_len - 1) << 7; | |
905 | ||
906 | /* set chipselect polarity; manage with FORCE */ | |
907 | if (!(spi->mode & SPI_CS_HIGH)) | |
908 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
909 | else | |
910 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
911 | ||
912 | /* set clock divisor */ | |
913 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
914 | l |= clkd << 2; |
915 | ||
916 | /* set clock granularity */ | |
917 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
918 | l |= clkg; | |
919 | if (clkg) { | |
920 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
921 | cs->chctrl0 |= extclk << 8; | |
922 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
923 | } | |
ccdc7bf9 SO |
924 | |
925 | /* set SPI mode 0..3 */ | |
926 | if (spi->mode & SPI_CPOL) | |
927 | l |= OMAP2_MCSPI_CHCONF_POL; | |
928 | else | |
929 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
930 | if (spi->mode & SPI_CPHA) | |
931 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
932 | else | |
933 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
934 | ||
a41ae1ad | 935 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 936 | |
97ca0d6c MG |
937 | cs->mode = spi->mode; |
938 | ||
ccdc7bf9 | 939 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 940 | speed_hz, |
ccdc7bf9 SO |
941 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
942 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
ddc5cdf1 TL |
947 | /* |
948 | * Note that we currently allow DMA only if we get a channel | |
949 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
950 | */ | |
ccdc7bf9 SO |
951 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
952 | { | |
953 | struct spi_master *master = spi->master; | |
954 | struct omap2_mcspi *mcspi; | |
955 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
956 | dma_cap_mask_t mask; |
957 | unsigned sig; | |
ccdc7bf9 SO |
958 | |
959 | mcspi = spi_master_get_devdata(master); | |
960 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
961 | ||
53741ed8 RK |
962 | init_completion(&mcspi_dma->dma_rx_completion); |
963 | init_completion(&mcspi_dma->dma_tx_completion); | |
964 | ||
965 | dma_cap_zero(mask); | |
966 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 967 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
968 | |
969 | mcspi_dma->dma_rx = | |
970 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
971 | &sig, &master->dev, | |
972 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
973 | if (!mcspi_dma->dma_rx) |
974 | goto no_dma; | |
ccdc7bf9 | 975 | |
53741ed8 | 976 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
977 | mcspi_dma->dma_tx = |
978 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
979 | &sig, &master->dev, | |
980 | mcspi_dma->dma_tx_ch_name); | |
981 | ||
53741ed8 | 982 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
983 | dma_release_channel(mcspi_dma->dma_rx); |
984 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 985 | goto no_dma; |
ccdc7bf9 SO |
986 | } |
987 | ||
ccdc7bf9 | 988 | return 0; |
ddc5cdf1 TL |
989 | |
990 | no_dma: | |
991 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
992 | return -EAGAIN; | |
ccdc7bf9 SO |
993 | } |
994 | ||
ccdc7bf9 SO |
995 | static int omap2_mcspi_setup(struct spi_device *spi) |
996 | { | |
997 | int ret; | |
1bd897f8 BC |
998 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
999 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
1000 | struct omap2_mcspi_dma *mcspi_dma; |
1001 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
1002 | ||
ccdc7bf9 SO |
1003 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
1004 | ||
1005 | if (!cs) { | |
10aa5a35 | 1006 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
1007 | if (!cs) |
1008 | return -ENOMEM; | |
1009 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 1010 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1011 | cs->mode = 0; |
a41ae1ad | 1012 | cs->chconf0 = 0; |
faee9b05 | 1013 | cs->chctrl0 = 0; |
ccdc7bf9 | 1014 | spi->controller_state = cs; |
89c05372 | 1015 | /* Link this to context save list */ |
1bd897f8 | 1016 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
1017 | } |
1018 | ||
8c7494a5 | 1019 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1020 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1021 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1022 | return ret; |
1023 | } | |
1024 | ||
bc7f9bbc MW |
1025 | if (gpio_is_valid(spi->cs_gpio)) { |
1026 | if (gpio_request(spi->cs_gpio, dev_name(&spi->dev)) == 0) | |
1027 | gpio_direction_output(spi->cs_gpio, | |
1028 | !(spi->mode & SPI_CS_HIGH)); | |
1029 | } | |
1030 | ||
034d3dc9 | 1031 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1032 | if (ret < 0) |
1033 | return ret; | |
a41ae1ad | 1034 | |
86eeb6fe | 1035 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1036 | pm_runtime_mark_last_busy(mcspi->dev); |
1037 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1038 | |
1039 | return ret; | |
1040 | } | |
1041 | ||
1042 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1043 | { | |
1044 | struct omap2_mcspi *mcspi; | |
1045 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1046 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1047 | |
1048 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1049 | |
5e774943 SE |
1050 | if (spi->controller_state) { |
1051 | /* Unlink controller state from context save list */ | |
1052 | cs = spi->controller_state; | |
1053 | list_del(&cs->node); | |
89c05372 | 1054 | |
10aa5a35 | 1055 | kfree(cs); |
5e774943 | 1056 | } |
ccdc7bf9 | 1057 | |
99f1a43f SE |
1058 | if (spi->chip_select < spi->master->num_chipselect) { |
1059 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1060 | ||
53741ed8 RK |
1061 | if (mcspi_dma->dma_rx) { |
1062 | dma_release_channel(mcspi_dma->dma_rx); | |
1063 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1064 | } |
53741ed8 RK |
1065 | if (mcspi_dma->dma_tx) { |
1066 | dma_release_channel(mcspi_dma->dma_tx); | |
1067 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1068 | } |
ccdc7bf9 | 1069 | } |
bc7f9bbc MW |
1070 | |
1071 | if (gpio_is_valid(spi->cs_gpio)) | |
1072 | gpio_free(spi->cs_gpio); | |
ccdc7bf9 SO |
1073 | } |
1074 | ||
b28cb941 MW |
1075 | static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, |
1076 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 | 1077 | { |
ccdc7bf9 SO |
1078 | |
1079 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1080 | * -- although this controller would gladly |
ccdc7bf9 SO |
1081 | * arbitrate among multiple channels. This corresponds to "single |
1082 | * channel" master mode. As a side effect, we need to manage the | |
1083 | * chipselect with the FORCE bit ... CS != channel enable. | |
1084 | */ | |
ccdc7bf9 | 1085 | |
5cbc7ca9 | 1086 | struct spi_master *master; |
ddc5cdf1 | 1087 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1088 | struct omap2_mcspi_cs *cs; |
1089 | struct omap2_mcspi_device_config *cd; | |
1090 | int par_override = 0; | |
1091 | int status = 0; | |
1092 | u32 chconf; | |
ccdc7bf9 | 1093 | |
5cbc7ca9 | 1094 | master = spi->master; |
ddc5cdf1 | 1095 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1096 | cs = spi->controller_state; |
1097 | cd = spi->controller_data; | |
ccdc7bf9 | 1098 | |
97ca0d6c MG |
1099 | /* |
1100 | * The slave driver could have changed spi->mode in which case | |
1101 | * it will be different from cs->mode (the current hardware setup). | |
1102 | * If so, set par_override (even though its not a parity issue) so | |
1103 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1104 | * with the correct mode on the first iteration of the loop below. | |
1105 | */ | |
1106 | if (spi->mode != cs->mode) | |
1107 | par_override = 1; | |
1108 | ||
d33f473d | 1109 | omap2_mcspi_set_enable(spi, 0); |
4743a0f8 | 1110 | |
b28cb941 MW |
1111 | if (par_override || |
1112 | (t->speed_hz != spi->max_speed_hz) || | |
1113 | (t->bits_per_word != spi->bits_per_word)) { | |
1114 | par_override = 1; | |
1115 | status = omap2_mcspi_setup_transfer(spi, t); | |
1116 | if (status < 0) | |
1117 | goto out; | |
1118 | if (t->speed_hz == spi->max_speed_hz && | |
1119 | t->bits_per_word == spi->bits_per_word) | |
1120 | par_override = 0; | |
1121 | } | |
1122 | if (cd && cd->cs_per_word) { | |
1123 | chconf = mcspi->ctx.modulctrl; | |
1124 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1125 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1126 | mcspi->ctx.modulctrl = | |
1127 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1128 | } | |
4743a0f8 | 1129 | |
b28cb941 MW |
1130 | chconf = mcspi_cached_chconf0(spi); |
1131 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1132 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
1133 | ||
1134 | if (t->tx_buf == NULL) | |
1135 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1136 | else if (t->rx_buf == NULL) | |
1137 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
1138 | ||
1139 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { | |
1140 | /* Turbo mode is for more than one word */ | |
1141 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1142 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1143 | } | |
ccdc7bf9 | 1144 | |
b28cb941 | 1145 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1146 | |
b28cb941 MW |
1147 | if (t->len) { |
1148 | unsigned count; | |
5fda88f5 | 1149 | |
b28cb941 MW |
1150 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1151 | (t->len >= DMA_MIN_BYTES)) | |
1152 | omap2_mcspi_set_fifo(spi, t, 1); | |
d33f473d | 1153 | |
b28cb941 | 1154 | omap2_mcspi_set_enable(spi, 1); |
d33f473d | 1155 | |
b28cb941 MW |
1156 | /* RX_ONLY mode needs dummy data in TX reg */ |
1157 | if (t->tx_buf == NULL) | |
1158 | writel_relaxed(0, cs->base | |
1159 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1160 | |
b28cb941 MW |
1161 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1162 | (t->len >= DMA_MIN_BYTES)) | |
1163 | count = omap2_mcspi_txrx_dma(spi, t); | |
1164 | else | |
1165 | count = omap2_mcspi_txrx_pio(spi, t); | |
ccdc7bf9 | 1166 | |
b28cb941 MW |
1167 | if (count != t->len) { |
1168 | status = -EIO; | |
1169 | goto out; | |
ccdc7bf9 | 1170 | } |
b28cb941 | 1171 | } |
ccdc7bf9 | 1172 | |
b28cb941 | 1173 | omap2_mcspi_set_enable(spi, 0); |
d33f473d | 1174 | |
b28cb941 MW |
1175 | if (mcspi->fifo_depth > 0) |
1176 | omap2_mcspi_set_fifo(spi, t, 0); | |
1177 | ||
1178 | out: | |
5fda88f5 S |
1179 | /* Restore defaults if they were overriden */ |
1180 | if (par_override) { | |
1181 | par_override = 0; | |
1182 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1183 | } | |
ccdc7bf9 | 1184 | |
5cbc7ca9 MB |
1185 | if (cd && cd->cs_per_word) { |
1186 | chconf = mcspi->ctx.modulctrl; | |
1187 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1188 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1189 | mcspi->ctx.modulctrl = | |
1190 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1191 | } | |
1192 | ||
5fda88f5 | 1193 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1194 | |
d33f473d IS |
1195 | if (mcspi->fifo_depth > 0 && t) |
1196 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1197 | |
b28cb941 | 1198 | return status; |
ccdc7bf9 SO |
1199 | } |
1200 | ||
b28cb941 MW |
1201 | static int omap2_mcspi_transfer_one(struct spi_master *master, |
1202 | struct spi_device *spi, struct spi_transfer *t) | |
ccdc7bf9 SO |
1203 | { |
1204 | struct omap2_mcspi *mcspi; | |
ddc5cdf1 | 1205 | struct omap2_mcspi_dma *mcspi_dma; |
b28cb941 MW |
1206 | const void *tx_buf = t->tx_buf; |
1207 | void *rx_buf = t->rx_buf; | |
1208 | unsigned len = t->len; | |
ccdc7bf9 | 1209 | |
5fda88f5 | 1210 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1211 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 | 1212 | |
b28cb941 MW |
1213 | if ((len && !(rx_buf || tx_buf))) { |
1214 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", | |
1215 | t->speed_hz, | |
1216 | len, | |
1217 | tx_buf ? "tx" : "", | |
1218 | rx_buf ? "rx" : "", | |
1219 | t->bits_per_word); | |
1220 | return -EINVAL; | |
1221 | } | |
1222 | ||
1223 | if (len < DMA_MIN_BYTES) | |
1224 | goto skip_dma_map; | |
1225 | ||
1226 | if (mcspi_dma->dma_tx && tx_buf != NULL) { | |
1227 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, | |
1228 | len, DMA_TO_DEVICE); | |
1229 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { | |
1230 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
1231 | 'T', len); | |
1232 | return -EINVAL; | |
ccdc7bf9 | 1233 | } |
b28cb941 MW |
1234 | } |
1235 | if (mcspi_dma->dma_rx && rx_buf != NULL) { | |
1236 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, | |
1237 | DMA_FROM_DEVICE); | |
1238 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { | |
1239 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
1240 | 'R', len); | |
1241 | if (tx_buf != NULL) | |
1242 | dma_unmap_single(mcspi->dev, t->tx_dma, | |
1243 | len, DMA_TO_DEVICE); | |
1244 | return -EINVAL; | |
ccdc7bf9 SO |
1245 | } |
1246 | } | |
1247 | ||
b28cb941 MW |
1248 | skip_dma_map: |
1249 | return omap2_mcspi_work_one(mcspi, spi, t); | |
ccdc7bf9 SO |
1250 | } |
1251 | ||
fd4a319b | 1252 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1253 | { |
1254 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1255 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1256 | int ret = 0; |
ccdc7bf9 | 1257 | |
034d3dc9 | 1258 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1259 | if (ret < 0) |
1260 | return ret; | |
ddb22195 | 1261 | |
39f8052d | 1262 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1263 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1264 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1265 | |
1266 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1267 | pm_runtime_mark_last_busy(mcspi->dev); |
1268 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1269 | return 0; |
1270 | } | |
1271 | ||
1f1a4384 G |
1272 | static int omap_mcspi_runtime_resume(struct device *dev) |
1273 | { | |
1274 | struct omap2_mcspi *mcspi; | |
1275 | struct spi_master *master; | |
1276 | ||
1277 | master = dev_get_drvdata(dev); | |
1278 | mcspi = spi_master_get_devdata(master); | |
1279 | omap2_mcspi_restore_ctx(mcspi); | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
d5a80031 BC |
1284 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1285 | .regs_offset = 0, | |
1286 | }; | |
1287 | ||
1288 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1289 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1290 | }; | |
1291 | ||
1292 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1293 | { | |
1294 | .compatible = "ti,omap2-mcspi", | |
1295 | .data = &omap2_pdata, | |
1296 | }, | |
1297 | { | |
1298 | .compatible = "ti,omap4-mcspi", | |
1299 | .data = &omap4_pdata, | |
1300 | }, | |
1301 | { }, | |
1302 | }; | |
1303 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1304 | |
fd4a319b | 1305 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1306 | { |
1307 | struct spi_master *master; | |
83a01e72 | 1308 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1309 | struct omap2_mcspi *mcspi; |
1310 | struct resource *r; | |
1311 | int status = 0, i; | |
d5a80031 BC |
1312 | u32 regs_offset = 0; |
1313 | static int bus_num = 1; | |
1314 | struct device_node *node = pdev->dev.of_node; | |
1315 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1316 | |
1317 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1318 | if (master == NULL) { | |
1319 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1320 | return -ENOMEM; | |
1321 | } | |
1322 | ||
e7db06b5 DB |
1323 | /* the spi->mode bits understood by this driver: */ |
1324 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1325 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1326 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1327 | master->auto_runtime_pm = true; |
b28cb941 | 1328 | master->transfer_one = omap2_mcspi_transfer_one; |
ddcad7e9 | 1329 | master->set_cs = omap2_mcspi_set_cs; |
ccdc7bf9 | 1330 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1331 | master->dev.of_node = node; |
aca0924b AL |
1332 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1333 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1334 | |
24b5a82c | 1335 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1336 | |
1337 | mcspi = spi_master_get_devdata(master); | |
1338 | mcspi->master = master; | |
1339 | ||
d5a80031 BC |
1340 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1341 | if (match) { | |
1342 | u32 num_cs = 1; /* default number of chipselect */ | |
1343 | pdata = match->data; | |
1344 | ||
1345 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1346 | master->num_chipselect = num_cs; | |
1347 | master->bus_num = bus_num++; | |
2cd45179 DM |
1348 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1349 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1350 | } else { |
8074cf06 | 1351 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1352 | master->num_chipselect = pdata->num_cs; |
1353 | if (pdev->id != -1) | |
1354 | master->bus_num = pdev->id; | |
0384e90b | 1355 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1356 | } |
1357 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1358 | |
ccdc7bf9 SO |
1359 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1360 | if (r == NULL) { | |
1361 | status = -ENODEV; | |
39f1b565 | 1362 | goto free_master; |
ccdc7bf9 | 1363 | } |
1458d160 | 1364 | |
d5a80031 BC |
1365 | r->start += regs_offset; |
1366 | r->end += regs_offset; | |
1458d160 | 1367 | mcspi->phys = r->start; |
ccdc7bf9 | 1368 | |
b0ee5605 TR |
1369 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1370 | if (IS_ERR(mcspi->base)) { | |
1371 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1372 | goto free_master; |
55c381e4 | 1373 | } |
ccdc7bf9 | 1374 | |
1f1a4384 | 1375 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1376 | |
1bd897f8 | 1377 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1378 | |
a6f936db AL |
1379 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1380 | sizeof(struct omap2_mcspi_dma), | |
1381 | GFP_KERNEL); | |
1382 | if (mcspi->dma_channels == NULL) { | |
1383 | status = -ENOMEM; | |
1a77b127 | 1384 | goto free_master; |
a6f936db | 1385 | } |
ccdc7bf9 | 1386 | |
1a5d8190 | 1387 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1388 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1389 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1390 | struct resource *dma_res; |
1391 | ||
74f3aaad MP |
1392 | sprintf(dma_rx_ch_name, "rx%d", i); |
1393 | if (!pdev->dev.of_node) { | |
1394 | dma_res = | |
1395 | platform_get_resource_byname(pdev, | |
1396 | IORESOURCE_DMA, | |
1397 | dma_rx_ch_name); | |
1398 | if (!dma_res) { | |
1399 | dev_dbg(&pdev->dev, | |
1400 | "cannot get DMA RX channel\n"); | |
1401 | status = -ENODEV; | |
1402 | break; | |
1403 | } | |
1a5d8190 | 1404 | |
74f3aaad MP |
1405 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1406 | dma_res->start; | |
1a5d8190 | 1407 | } |
74f3aaad MP |
1408 | sprintf(dma_tx_ch_name, "tx%d", i); |
1409 | if (!pdev->dev.of_node) { | |
1410 | dma_res = | |
1411 | platform_get_resource_byname(pdev, | |
1412 | IORESOURCE_DMA, | |
1413 | dma_tx_ch_name); | |
1414 | if (!dma_res) { | |
1415 | dev_dbg(&pdev->dev, | |
1416 | "cannot get DMA TX channel\n"); | |
1417 | status = -ENODEV; | |
1418 | break; | |
1419 | } | |
1a5d8190 | 1420 | |
74f3aaad MP |
1421 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1422 | dma_res->start; | |
1423 | } | |
ccdc7bf9 SO |
1424 | } |
1425 | ||
39f1b565 | 1426 | if (status < 0) |
a6f936db | 1427 | goto free_master; |
39f1b565 | 1428 | |
27b5284c S |
1429 | pm_runtime_use_autosuspend(&pdev->dev); |
1430 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1431 | pm_runtime_enable(&pdev->dev); |
1432 | ||
142e07be WY |
1433 | status = omap2_mcspi_master_setup(mcspi); |
1434 | if (status < 0) | |
39f1b565 | 1435 | goto disable_pm; |
ccdc7bf9 | 1436 | |
b95e02b7 | 1437 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1438 | if (status < 0) |
37a2d84a | 1439 | goto disable_pm; |
ccdc7bf9 SO |
1440 | |
1441 | return status; | |
1442 | ||
39f1b565 | 1443 | disable_pm: |
751c925c | 1444 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1445 | free_master: |
37a2d84a | 1446 | spi_master_put(master); |
ccdc7bf9 SO |
1447 | return status; |
1448 | } | |
1449 | ||
fd4a319b | 1450 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1451 | { |
a6f936db AL |
1452 | struct spi_master *master = platform_get_drvdata(pdev); |
1453 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1454 | |
a93a2029 | 1455 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1456 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1457 | |
ccdc7bf9 SO |
1458 | return 0; |
1459 | } | |
1460 | ||
7e38c3c4 KS |
1461 | /* work with hotplug and coldplug */ |
1462 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1463 | ||
42ce7fd6 GC |
1464 | #ifdef CONFIG_SUSPEND |
1465 | /* | |
1466 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1467 | * unactive state when driver was suspend, then force it to unactive state at | |
1468 | * wake up. | |
1469 | */ | |
1470 | static int omap2_mcspi_resume(struct device *dev) | |
1471 | { | |
1472 | struct spi_master *master = dev_get_drvdata(dev); | |
1473 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1474 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1475 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1476 | |
034d3dc9 | 1477 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1478 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1479 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1480 | /* |
1481 | * We need to toggle CS state for OMAP take this | |
1482 | * change in account. | |
1483 | */ | |
af4e944d | 1484 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1485 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1486 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1487 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1488 | } |
1489 | } | |
034d3dc9 S |
1490 | pm_runtime_mark_last_busy(mcspi->dev); |
1491 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1492 | return 0; |
1493 | } | |
1494 | #else | |
1495 | #define omap2_mcspi_resume NULL | |
1496 | #endif | |
1497 | ||
1498 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1499 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1500 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1501 | }; |
1502 | ||
ccdc7bf9 SO |
1503 | static struct platform_driver omap2_mcspi_driver = { |
1504 | .driver = { | |
1505 | .name = "omap2_mcspi", | |
d5a80031 BC |
1506 | .pm = &omap2_mcspi_pm_ops, |
1507 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1508 | }, |
7d6b6d83 | 1509 | .probe = omap2_mcspi_probe, |
fd4a319b | 1510 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1511 | }; |
1512 | ||
9fdca9df | 1513 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1514 | MODULE_LICENSE("GPL"); |