Commit | Line | Data |
---|---|---|
60cadec9 | 1 | /* |
ca632f55 | 2 | * Marvell Orion SPI controller driver |
60cadec9 SA |
3 | * |
4 | * Author: Shadi Ammouri <shadi@marvell.com> | |
5 | * Copyright (C) 2007-2008 Marvell Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
60cadec9 SA |
12 | #include <linux/interrupt.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/spi/spi.h> | |
d7614de4 | 18 | #include <linux/module.h> |
5c678694 | 19 | #include <linux/pm_runtime.h> |
f814f9ac | 20 | #include <linux/of.h> |
df59fa7f | 21 | #include <linux/of_device.h> |
4574b886 | 22 | #include <linux/clk.h> |
895248f8 | 23 | #include <linux/sizes.h> |
60cadec9 SA |
24 | #include <asm/unaligned.h> |
25 | ||
26 | #define DRIVER_NAME "orion_spi" | |
27 | ||
5c678694 RK |
28 | /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ |
29 | #define SPI_AUTOSUSPEND_TIMEOUT 200 | |
30 | ||
23244404 KW |
31 | /* Some SoCs using this driver support up to 8 chip selects. |
32 | * It is up to the implementer to only use the chip selects | |
33 | * that are available. | |
34 | */ | |
35 | #define ORION_NUM_CHIPSELECTS 8 | |
36 | ||
60cadec9 SA |
37 | #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ |
38 | ||
39 | #define ORION_SPI_IF_CTRL_REG 0x00 | |
40 | #define ORION_SPI_IF_CONFIG_REG 0x04 | |
41 | #define ORION_SPI_DATA_OUT_REG 0x08 | |
42 | #define ORION_SPI_DATA_IN_REG 0x0c | |
43 | #define ORION_SPI_INT_CAUSE_REG 0x10 | |
44 | ||
b15d5d70 JG |
45 | #define ORION_SPI_MODE_CPOL (1 << 11) |
46 | #define ORION_SPI_MODE_CPHA (1 << 12) | |
60cadec9 SA |
47 | #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) |
48 | #define ORION_SPI_CLK_PRESCALE_MASK 0x1F | |
df59fa7f | 49 | #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF |
b15d5d70 JG |
50 | #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ |
51 | ORION_SPI_MODE_CPHA) | |
23244404 KW |
52 | #define ORION_SPI_CS_MASK 0x1C |
53 | #define ORION_SPI_CS_SHIFT 2 | |
54 | #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ | |
55 | ORION_SPI_CS_MASK) | |
60cadec9 | 56 | |
df59fa7f GU |
57 | enum orion_spi_type { |
58 | ORION_SPI, | |
59 | ARMADA_SPI, | |
60 | }; | |
61 | ||
62 | struct orion_spi_dev { | |
63 | enum orion_spi_type typ; | |
ce2f6ea1 GC |
64 | /* |
65 | * min_divisor and max_hz should be exclusive, the only we can | |
66 | * have both is for managing the armada-370-spi case with old | |
67 | * device tree | |
68 | */ | |
69 | unsigned long max_hz; | |
df59fa7f GU |
70 | unsigned int min_divisor; |
71 | unsigned int max_divisor; | |
72 | u32 prescale_mask; | |
73 | }; | |
74 | ||
60cadec9 | 75 | struct orion_spi { |
60cadec9 SA |
76 | struct spi_master *master; |
77 | void __iomem *base; | |
4574b886 | 78 | struct clk *clk; |
df59fa7f | 79 | const struct orion_spi_dev *devdata; |
60cadec9 SA |
80 | }; |
81 | ||
60cadec9 SA |
82 | static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
83 | { | |
84 | return orion_spi->base + reg; | |
85 | } | |
86 | ||
87 | static inline void | |
88 | orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
89 | { | |
90 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
91 | u32 val; | |
92 | ||
93 | val = readl(reg_addr); | |
94 | val |= mask; | |
95 | writel(val, reg_addr); | |
96 | } | |
97 | ||
98 | static inline void | |
99 | orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
100 | { | |
101 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
102 | u32 val; | |
103 | ||
104 | val = readl(reg_addr); | |
105 | val &= ~mask; | |
106 | writel(val, reg_addr); | |
107 | } | |
108 | ||
60cadec9 SA |
109 | static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) |
110 | { | |
111 | u32 tclk_hz; | |
112 | u32 rate; | |
113 | u32 prescale; | |
114 | u32 reg; | |
115 | struct orion_spi *orion_spi; | |
df59fa7f | 116 | const struct orion_spi_dev *devdata; |
60cadec9 SA |
117 | |
118 | orion_spi = spi_master_get_devdata(spi->master); | |
df59fa7f | 119 | devdata = orion_spi->devdata; |
60cadec9 | 120 | |
4574b886 | 121 | tclk_hz = clk_get_rate(orion_spi->clk); |
60cadec9 | 122 | |
df59fa7f GU |
123 | if (devdata->typ == ARMADA_SPI) { |
124 | unsigned int clk, spr, sppr, sppr2, err; | |
125 | unsigned int best_spr, best_sppr, best_err; | |
60cadec9 | 126 | |
df59fa7f GU |
127 | best_err = speed; |
128 | best_spr = 0; | |
129 | best_sppr = 0; | |
60cadec9 | 130 | |
df59fa7f GU |
131 | /* Iterate over the valid range looking for best fit */ |
132 | for (sppr = 0; sppr < 8; sppr++) { | |
133 | sppr2 = 0x1 << sppr; | |
134 | ||
135 | spr = tclk_hz / sppr2; | |
136 | spr = DIV_ROUND_UP(spr, speed); | |
137 | if ((spr == 0) || (spr > 15)) | |
138 | continue; | |
60cadec9 | 139 | |
df59fa7f GU |
140 | clk = tclk_hz / (spr * sppr2); |
141 | err = speed - clk; | |
60cadec9 | 142 | |
df59fa7f GU |
143 | if (err < best_err) { |
144 | best_spr = spr; | |
145 | best_sppr = sppr; | |
146 | best_err = err; | |
147 | } | |
148 | } | |
60cadec9 | 149 | |
df59fa7f GU |
150 | if ((best_sppr == 0) && (best_spr == 0)) |
151 | return -EINVAL; | |
152 | ||
153 | prescale = ((best_sppr & 0x6) << 5) | | |
154 | ((best_sppr & 0x1) << 4) | best_spr; | |
155 | } else { | |
156 | /* | |
157 | * the supported rates are: 4,6,8...30 | |
158 | * round up as we look for equal or less speed | |
159 | */ | |
160 | rate = DIV_ROUND_UP(tclk_hz, speed); | |
161 | rate = roundup(rate, 2); | |
162 | ||
163 | /* check if requested speed is too small */ | |
164 | if (rate > 30) | |
165 | return -EINVAL; | |
60cadec9 | 166 | |
df59fa7f GU |
167 | if (rate < 4) |
168 | rate = 4; | |
169 | ||
170 | /* Convert the rate to SPI clock divisor value. */ | |
171 | prescale = 0x10 + rate/2; | |
172 | } | |
60cadec9 SA |
173 | |
174 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
df59fa7f | 175 | reg = ((reg & ~devdata->prescale_mask) | prescale); |
60cadec9 SA |
176 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
b15d5d70 JG |
181 | static void |
182 | orion_spi_mode_set(struct spi_device *spi) | |
183 | { | |
184 | u32 reg; | |
185 | struct orion_spi *orion_spi; | |
186 | ||
187 | orion_spi = spi_master_get_devdata(spi->master); | |
188 | ||
189 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
190 | reg &= ~ORION_SPI_MODE_MASK; | |
191 | if (spi->mode & SPI_CPOL) | |
192 | reg |= ORION_SPI_MODE_CPOL; | |
193 | if (spi->mode & SPI_CPHA) | |
194 | reg |= ORION_SPI_MODE_CPHA; | |
195 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
196 | } | |
197 | ||
60cadec9 SA |
198 | /* |
199 | * called only when no transfer is active on the bus | |
200 | */ | |
201 | static int | |
202 | orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
203 | { | |
204 | struct orion_spi *orion_spi; | |
205 | unsigned int speed = spi->max_speed_hz; | |
206 | unsigned int bits_per_word = spi->bits_per_word; | |
207 | int rc; | |
208 | ||
209 | orion_spi = spi_master_get_devdata(spi->master); | |
210 | ||
211 | if ((t != NULL) && t->speed_hz) | |
212 | speed = t->speed_hz; | |
213 | ||
214 | if ((t != NULL) && t->bits_per_word) | |
215 | bits_per_word = t->bits_per_word; | |
216 | ||
b15d5d70 JG |
217 | orion_spi_mode_set(spi); |
218 | ||
60cadec9 SA |
219 | rc = orion_spi_baudrate_set(spi, speed); |
220 | if (rc) | |
221 | return rc; | |
222 | ||
495b3358 AL |
223 | if (bits_per_word == 16) |
224 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
225 | ORION_SPI_IF_8_16_BIT_MODE); | |
226 | else | |
227 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
228 | ORION_SPI_IF_8_16_BIT_MODE); | |
229 | ||
230 | return 0; | |
60cadec9 SA |
231 | } |
232 | ||
75872ebe | 233 | static void orion_spi_set_cs(struct spi_device *spi, bool enable) |
60cadec9 | 234 | { |
75872ebe KW |
235 | struct orion_spi *orion_spi; |
236 | ||
237 | orion_spi = spi_master_get_devdata(spi->master); | |
238 | ||
23244404 KW |
239 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); |
240 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, | |
241 | ORION_SPI_CS(spi->chip_select)); | |
242 | ||
75872ebe KW |
243 | /* Chip select logic is inverted from spi_set_cs */ |
244 | if (!enable) | |
60cadec9 SA |
245 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
246 | else | |
247 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); | |
248 | } | |
249 | ||
250 | static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) | |
251 | { | |
252 | int i; | |
253 | ||
254 | for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { | |
255 | if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) | |
256 | return 1; | |
b8434048 JH |
257 | |
258 | udelay(1); | |
60cadec9 SA |
259 | } |
260 | ||
261 | return -1; | |
262 | } | |
263 | ||
264 | static inline int | |
265 | orion_spi_write_read_8bit(struct spi_device *spi, | |
266 | const u8 **tx_buf, u8 **rx_buf) | |
267 | { | |
268 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
269 | struct orion_spi *orion_spi; | |
270 | ||
271 | orion_spi = spi_master_get_devdata(spi->master); | |
272 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
273 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
274 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
275 | ||
276 | /* clear the interrupt cause register */ | |
277 | writel(0x0, int_reg); | |
278 | ||
279 | if (tx_buf && *tx_buf) | |
280 | writel(*(*tx_buf)++, tx_reg); | |
281 | else | |
282 | writel(0, tx_reg); | |
283 | ||
284 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
285 | dev_err(&spi->dev, "TXS timed out\n"); | |
286 | return -1; | |
287 | } | |
288 | ||
289 | if (rx_buf && *rx_buf) | |
290 | *(*rx_buf)++ = readl(rx_reg); | |
291 | ||
292 | return 1; | |
293 | } | |
294 | ||
295 | static inline int | |
296 | orion_spi_write_read_16bit(struct spi_device *spi, | |
297 | const u16 **tx_buf, u16 **rx_buf) | |
298 | { | |
299 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
300 | struct orion_spi *orion_spi; | |
301 | ||
302 | orion_spi = spi_master_get_devdata(spi->master); | |
303 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
304 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
305 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
306 | ||
307 | /* clear the interrupt cause register */ | |
308 | writel(0x0, int_reg); | |
309 | ||
310 | if (tx_buf && *tx_buf) | |
311 | writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); | |
312 | else | |
313 | writel(0, tx_reg); | |
314 | ||
315 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
316 | dev_err(&spi->dev, "TXS timed out\n"); | |
317 | return -1; | |
318 | } | |
319 | ||
320 | if (rx_buf && *rx_buf) | |
321 | put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); | |
322 | ||
323 | return 1; | |
324 | } | |
325 | ||
326 | static unsigned int | |
327 | orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) | |
328 | { | |
60cadec9 SA |
329 | unsigned int count; |
330 | int word_len; | |
331 | ||
60cadec9 SA |
332 | word_len = spi->bits_per_word; |
333 | count = xfer->len; | |
334 | ||
335 | if (word_len == 8) { | |
336 | const u8 *tx = xfer->tx_buf; | |
337 | u8 *rx = xfer->rx_buf; | |
338 | ||
339 | do { | |
340 | if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) | |
341 | goto out; | |
342 | count--; | |
343 | } while (count); | |
344 | } else if (word_len == 16) { | |
345 | const u16 *tx = xfer->tx_buf; | |
346 | u16 *rx = xfer->rx_buf; | |
347 | ||
348 | do { | |
349 | if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) | |
350 | goto out; | |
351 | count -= 2; | |
352 | } while (count); | |
353 | } | |
354 | ||
355 | out: | |
356 | return xfer->len - count; | |
357 | } | |
358 | ||
75872ebe KW |
359 | static int orion_spi_transfer_one(struct spi_master *master, |
360 | struct spi_device *spi, | |
361 | struct spi_transfer *t) | |
60cadec9 | 362 | { |
ba59a807 | 363 | int status = 0; |
60cadec9 | 364 | |
75872ebe | 365 | status = orion_spi_setup_transfer(spi, t); |
ba59a807 | 366 | if (status < 0) |
75872ebe | 367 | return status; |
60cadec9 | 368 | |
75872ebe KW |
369 | if (t->len) |
370 | orion_spi_write_read(spi, t); | |
ba59a807 | 371 | |
75872ebe KW |
372 | return status; |
373 | } | |
ba59a807 | 374 | |
75872ebe KW |
375 | static int orion_spi_setup(struct spi_device *spi) |
376 | { | |
377 | return orion_spi_setup_transfer(spi, NULL); | |
60cadec9 SA |
378 | } |
379 | ||
2deff8d6 | 380 | static int orion_spi_reset(struct orion_spi *orion_spi) |
60cadec9 SA |
381 | { |
382 | /* Verify that the CS is deasserted */ | |
75872ebe | 383 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
60cadec9 SA |
384 | return 0; |
385 | } | |
386 | ||
df59fa7f GU |
387 | static const struct orion_spi_dev orion_spi_dev_data = { |
388 | .typ = ORION_SPI, | |
389 | .min_divisor = 4, | |
390 | .max_divisor = 30, | |
391 | .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, | |
392 | }; | |
393 | ||
4dacccfa | 394 | static const struct orion_spi_dev armada_370_spi_dev_data = { |
df59fa7f | 395 | .typ = ARMADA_SPI, |
ce2f6ea1 | 396 | .min_divisor = 4, |
df59fa7f | 397 | .max_divisor = 1920, |
ce2f6ea1 | 398 | .max_hz = 50000000, |
df59fa7f GU |
399 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
400 | }; | |
401 | ||
4dacccfa GC |
402 | static const struct orion_spi_dev armada_xp_spi_dev_data = { |
403 | .typ = ARMADA_SPI, | |
404 | .max_hz = 50000000, | |
405 | .max_divisor = 1920, | |
406 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
407 | }; | |
408 | ||
409 | static const struct orion_spi_dev armada_375_spi_dev_data = { | |
410 | .typ = ARMADA_SPI, | |
411 | .min_divisor = 15, | |
412 | .max_divisor = 1920, | |
413 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
414 | }; | |
415 | ||
df59fa7f | 416 | static const struct of_device_id orion_spi_of_match_table[] = { |
4dacccfa GC |
417 | { |
418 | .compatible = "marvell,orion-spi", | |
419 | .data = &orion_spi_dev_data, | |
420 | }, | |
421 | { | |
422 | .compatible = "marvell,armada-370-spi", | |
423 | .data = &armada_370_spi_dev_data, | |
424 | }, | |
425 | { | |
426 | .compatible = "marvell,armada-375-spi", | |
427 | .data = &armada_375_spi_dev_data, | |
428 | }, | |
429 | { | |
430 | .compatible = "marvell,armada-380-spi", | |
431 | .data = &armada_xp_spi_dev_data, | |
432 | }, | |
433 | { | |
434 | .compatible = "marvell,armada-390-spi", | |
435 | .data = &armada_xp_spi_dev_data, | |
436 | }, | |
437 | { | |
438 | .compatible = "marvell,armada-xp-spi", | |
439 | .data = &armada_xp_spi_dev_data, | |
440 | }, | |
441 | ||
df59fa7f GU |
442 | {} |
443 | }; | |
444 | MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); | |
445 | ||
2deff8d6 | 446 | static int orion_spi_probe(struct platform_device *pdev) |
60cadec9 | 447 | { |
df59fa7f GU |
448 | const struct of_device_id *of_id; |
449 | const struct orion_spi_dev *devdata; | |
60cadec9 SA |
450 | struct spi_master *master; |
451 | struct orion_spi *spi; | |
452 | struct resource *r; | |
4574b886 | 453 | unsigned long tclk_hz; |
60cadec9 SA |
454 | int status = 0; |
455 | ||
3fed8068 | 456 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); |
60cadec9 SA |
457 | if (master == NULL) { |
458 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
459 | return -ENOMEM; | |
460 | } | |
461 | ||
462 | if (pdev->id != -1) | |
463 | master->bus_num = pdev->id; | |
f814f9ac | 464 | if (pdev->dev.of_node) { |
e06871cd | 465 | u32 cell_index; |
b8434048 | 466 | |
e06871cd TP |
467 | if (!of_property_read_u32(pdev->dev.of_node, "cell-index", |
468 | &cell_index)) | |
469 | master->bus_num = cell_index; | |
f814f9ac | 470 | } |
60cadec9 | 471 | |
e7db06b5 | 472 | /* we support only mode 0, and no options */ |
b15d5d70 | 473 | master->mode_bits = SPI_CPHA | SPI_CPOL; |
75872ebe KW |
474 | master->set_cs = orion_spi_set_cs; |
475 | master->transfer_one = orion_spi_transfer_one; | |
60cadec9 | 476 | master->num_chipselect = ORION_NUM_CHIPSELECTS; |
75872ebe | 477 | master->setup = orion_spi_setup; |
495b3358 | 478 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
5c678694 | 479 | master->auto_runtime_pm = true; |
60cadec9 | 480 | |
24b5a82c | 481 | platform_set_drvdata(pdev, master); |
60cadec9 SA |
482 | |
483 | spi = spi_master_get_devdata(master); | |
484 | spi->master = master; | |
60cadec9 | 485 | |
df59fa7f | 486 | of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); |
9a2d3635 | 487 | devdata = (of_id) ? of_id->data : &orion_spi_dev_data; |
df59fa7f GU |
488 | spi->devdata = devdata; |
489 | ||
bb489841 | 490 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
4574b886 AL |
491 | if (IS_ERR(spi->clk)) { |
492 | status = PTR_ERR(spi->clk); | |
493 | goto out; | |
494 | } | |
495 | ||
c85012ad RK |
496 | status = clk_prepare_enable(spi->clk); |
497 | if (status) | |
498 | goto out; | |
499 | ||
4574b886 | 500 | tclk_hz = clk_get_rate(spi->clk); |
ce2f6ea1 GC |
501 | |
502 | /* | |
503 | * With old device tree, armada-370-spi could be used with | |
504 | * Armada XP, however for this SoC the maximum frequency is | |
505 | * 50MHz instead of tclk/4. On Armada 370, tclk cannot be | |
506 | * higher than 200MHz. So, in order to be able to handle both | |
507 | * SoCs, we can take the minimum of 50MHz and tclk/4. | |
508 | */ | |
509 | if (of_device_is_compatible(pdev->dev.of_node, | |
510 | "marvell,armada-370-spi")) | |
511 | master->max_speed_hz = min(devdata->max_hz, | |
512 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); | |
4dacccfa | 513 | else if (devdata->min_divisor) |
ce2f6ea1 GC |
514 | master->max_speed_hz = |
515 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor); | |
4dacccfa GC |
516 | else |
517 | master->max_speed_hz = devdata->max_hz; | |
df59fa7f | 518 | master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); |
60cadec9 SA |
519 | |
520 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1729ce34 MB |
521 | spi->base = devm_ioremap_resource(&pdev->dev, r); |
522 | if (IS_ERR(spi->base)) { | |
523 | status = PTR_ERR(spi->base); | |
4574b886 | 524 | goto out_rel_clk; |
60cadec9 SA |
525 | } |
526 | ||
5c678694 RK |
527 | pm_runtime_set_active(&pdev->dev); |
528 | pm_runtime_use_autosuspend(&pdev->dev); | |
529 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
530 | pm_runtime_enable(&pdev->dev); | |
531 | ||
14033816 WY |
532 | status = orion_spi_reset(spi); |
533 | if (status < 0) | |
5c678694 RK |
534 | goto out_rel_pm; |
535 | ||
536 | pm_runtime_mark_last_busy(&pdev->dev); | |
537 | pm_runtime_put_autosuspend(&pdev->dev); | |
60cadec9 | 538 | |
f814f9ac | 539 | master->dev.of_node = pdev->dev.of_node; |
5c678694 | 540 | status = spi_register_master(master); |
60cadec9 | 541 | if (status < 0) |
5c678694 | 542 | goto out_rel_pm; |
60cadec9 SA |
543 | |
544 | return status; | |
545 | ||
5c678694 RK |
546 | out_rel_pm: |
547 | pm_runtime_disable(&pdev->dev); | |
4574b886 AL |
548 | out_rel_clk: |
549 | clk_disable_unprepare(spi->clk); | |
60cadec9 SA |
550 | out: |
551 | spi_master_put(master); | |
552 | return status; | |
553 | } | |
554 | ||
555 | ||
2deff8d6 | 556 | static int orion_spi_remove(struct platform_device *pdev) |
60cadec9 | 557 | { |
5c678694 RK |
558 | struct spi_master *master = platform_get_drvdata(pdev); |
559 | struct orion_spi *spi = spi_master_get_devdata(master); | |
60cadec9 | 560 | |
5c678694 | 561 | pm_runtime_get_sync(&pdev->dev); |
4574b886 | 562 | clk_disable_unprepare(spi->clk); |
4574b886 | 563 | |
5c678694 RK |
564 | spi_unregister_master(master); |
565 | pm_runtime_disable(&pdev->dev); | |
566 | ||
60cadec9 SA |
567 | return 0; |
568 | } | |
569 | ||
570 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
571 | ||
ec833050 | 572 | #ifdef CONFIG_PM |
5c678694 RK |
573 | static int orion_spi_runtime_suspend(struct device *dev) |
574 | { | |
575 | struct spi_master *master = dev_get_drvdata(dev); | |
576 | struct orion_spi *spi = spi_master_get_devdata(master); | |
577 | ||
578 | clk_disable_unprepare(spi->clk); | |
579 | return 0; | |
580 | } | |
581 | ||
582 | static int orion_spi_runtime_resume(struct device *dev) | |
583 | { | |
584 | struct spi_master *master = dev_get_drvdata(dev); | |
585 | struct orion_spi *spi = spi_master_get_devdata(master); | |
586 | ||
587 | return clk_prepare_enable(spi->clk); | |
588 | } | |
589 | #endif | |
590 | ||
591 | static const struct dev_pm_ops orion_spi_pm_ops = { | |
592 | SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, | |
593 | orion_spi_runtime_resume, | |
594 | NULL) | |
595 | }; | |
596 | ||
60cadec9 SA |
597 | static struct platform_driver orion_spi_driver = { |
598 | .driver = { | |
599 | .name = DRIVER_NAME, | |
5c678694 | 600 | .pm = &orion_spi_pm_ops, |
f814f9ac | 601 | .of_match_table = of_match_ptr(orion_spi_of_match_table), |
60cadec9 | 602 | }, |
41ab724a | 603 | .probe = orion_spi_probe, |
2deff8d6 | 604 | .remove = orion_spi_remove, |
60cadec9 SA |
605 | }; |
606 | ||
41ab724a | 607 | module_platform_driver(orion_spi_driver); |
60cadec9 SA |
608 | |
609 | MODULE_DESCRIPTION("Orion SPI driver"); | |
610 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); | |
611 | MODULE_LICENSE("GPL"); |