Commit | Line | Data |
---|---|---|
1bcb9f8c PCM |
1 | /* |
2 | * Microchip PIC32 SPI controller driver. | |
3 | * | |
4 | * Purna Chandra Mandal <purna.mandal@microchip.com> | |
5 | * Copyright (c) 2016, Microchip Technology Inc. | |
6 | * | |
7 | * This program is free software; you can distribute it and/or modify it | |
8 | * under the terms of the GNU General Public License (Version 2) as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/clkdev.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/dmaengine.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_gpio.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/spi/spi.h> | |
32 | ||
33 | /* SPI controller registers */ | |
34 | struct pic32_spi_regs { | |
35 | u32 ctrl; | |
36 | u32 ctrl_clr; | |
37 | u32 ctrl_set; | |
38 | u32 ctrl_inv; | |
39 | u32 status; | |
40 | u32 status_clr; | |
41 | u32 status_set; | |
42 | u32 status_inv; | |
43 | u32 buf; | |
44 | u32 dontuse[3]; | |
45 | u32 baud; | |
46 | u32 dontuse2[3]; | |
47 | u32 ctrl2; | |
48 | u32 ctrl2_clr; | |
49 | u32 ctrl2_set; | |
50 | u32 ctrl2_inv; | |
51 | }; | |
52 | ||
53 | /* Bit fields of SPI Control Register */ | |
54 | #define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */ | |
55 | #define RX_FIFO_EMTPY 0 | |
56 | #define RX_FIFO_NOT_EMPTY 1 /* not empty */ | |
57 | #define RX_FIFO_HALF_FULL 2 /* full by half or more */ | |
58 | #define RX_FIFO_FULL 3 /* completely full */ | |
59 | ||
60 | #define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */ | |
61 | #define TX_FIFO_ALL_EMPTY 0 /* completely empty */ | |
62 | #define TX_FIFO_EMTPY 1 /* empty */ | |
63 | #define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */ | |
64 | #define TX_FIFO_NOT_FULL 3 /* atleast one empty */ | |
65 | ||
66 | #define CTRL_MSTEN BIT(5) /* enable master mode */ | |
67 | #define CTRL_CKP BIT(6) /* active low */ | |
68 | #define CTRL_CKE BIT(8) /* Tx on falling edge */ | |
69 | #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */ | |
70 | #define CTRL_BPW_MASK 0x03 /* bits per word/sample */ | |
71 | #define CTRL_BPW_SHIFT 10 | |
72 | #define PIC32_BPW_8 0 | |
73 | #define PIC32_BPW_16 1 | |
74 | #define PIC32_BPW_32 2 | |
75 | #define CTRL_SIDL BIT(13) /* sleep when idle */ | |
76 | #define CTRL_ON BIT(15) /* enable macro */ | |
77 | #define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */ | |
78 | #define CTRL_MCLKSEL BIT(23) /* select clock source */ | |
79 | #define CTRL_MSSEN BIT(28) /* macro driven /SS */ | |
80 | #define CTRL_FRMEN BIT(31) /* enable framing mode */ | |
81 | ||
82 | /* Bit fields of SPI Status Register */ | |
83 | #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */ | |
84 | #define STAT_RX_OV BIT(6) /* err, s/w needs to clear */ | |
85 | #define STAT_TX_UR BIT(8) /* UR in Framed SPI modes */ | |
86 | #define STAT_FRM_ERR BIT(12) /* Multiple Frame Sync pulse */ | |
87 | #define STAT_TF_LVL_MASK 0x1F | |
88 | #define STAT_TF_LVL_SHIFT 16 | |
89 | #define STAT_RF_LVL_MASK 0x1F | |
90 | #define STAT_RF_LVL_SHIFT 24 | |
91 | ||
92 | /* Bit fields of SPI Baud Register */ | |
93 | #define BAUD_MASK 0x1ff | |
94 | ||
95 | /* Bit fields of SPI Control2 Register */ | |
96 | #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */ | |
97 | #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */ | |
98 | #define CTRL2_FRM_ERR_EN BIT(12) /* Enable frame err int */ | |
99 | ||
100 | /* Minimum DMA transfer size */ | |
101 | #define PIC32_DMA_LEN_MIN 64 | |
102 | ||
103 | struct pic32_spi { | |
104 | dma_addr_t dma_base; | |
105 | struct pic32_spi_regs __iomem *regs; | |
106 | int fault_irq; | |
107 | int rx_irq; | |
108 | int tx_irq; | |
109 | u32 fifo_n_byte; /* FIFO depth in bytes */ | |
110 | struct clk *clk; | |
111 | struct spi_master *master; | |
112 | /* Current controller setting */ | |
113 | u32 speed_hz; /* spi-clk rate */ | |
114 | u32 mode; | |
115 | u32 bits_per_word; | |
116 | u32 fifo_n_elm; /* FIFO depth in words */ | |
117 | #define PIC32F_DMA_PREP 0 /* DMA chnls configured */ | |
118 | unsigned long flags; | |
119 | /* Current transfer state */ | |
120 | struct completion xfer_done; | |
121 | /* PIO transfer specific */ | |
122 | const void *tx; | |
123 | const void *tx_end; | |
124 | const void *rx; | |
125 | const void *rx_end; | |
126 | int len; | |
127 | void (*rx_fifo)(struct pic32_spi *); | |
128 | void (*tx_fifo)(struct pic32_spi *); | |
129 | }; | |
130 | ||
131 | static inline void pic32_spi_enable(struct pic32_spi *pic32s) | |
132 | { | |
133 | writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set); | |
134 | } | |
135 | ||
136 | static inline void pic32_spi_disable(struct pic32_spi *pic32s) | |
137 | { | |
138 | writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr); | |
139 | ||
140 | /* avoid SPI registers read/write at immediate next CPU clock */ | |
141 | ndelay(20); | |
142 | } | |
143 | ||
144 | static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck) | |
145 | { | |
146 | u32 div; | |
147 | ||
148 | /* div = (clk_in / 2 * spi_ck) - 1 */ | |
149 | div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1; | |
150 | ||
151 | writel(div & BAUD_MASK, &pic32s->regs->baud); | |
152 | } | |
153 | ||
154 | static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s) | |
155 | { | |
156 | u32 sr = readl(&pic32s->regs->status); | |
157 | ||
158 | return (sr >> STAT_RF_LVL_SHIFT) & STAT_RF_LVL_MASK; | |
159 | } | |
160 | ||
161 | static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s) | |
162 | { | |
163 | u32 sr = readl(&pic32s->regs->status); | |
164 | ||
165 | return (sr >> STAT_TF_LVL_SHIFT) & STAT_TF_LVL_MASK; | |
166 | } | |
167 | ||
168 | /* Return the max entries we can fill into tx fifo */ | |
169 | static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes) | |
170 | { | |
171 | u32 tx_left, tx_room, rxtx_gap; | |
172 | ||
173 | tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes; | |
174 | tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s); | |
175 | ||
176 | /* | |
177 | * Another concern is about the tx/rx mismatch, we | |
178 | * though to use (pic32s->fifo_n_byte - rxfl - txfl) as | |
179 | * one maximum value for tx, but it doesn't cover the | |
180 | * data which is out of tx/rx fifo and inside the | |
181 | * shift registers. So a ctrl from sw point of | |
182 | * view is taken. | |
183 | */ | |
184 | rxtx_gap = ((pic32s->rx_end - pic32s->rx) - | |
185 | (pic32s->tx_end - pic32s->tx)) / n_bytes; | |
186 | return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap)); | |
187 | } | |
188 | ||
189 | /* Return the max entries we should read out of rx fifo */ | |
190 | static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes) | |
191 | { | |
192 | u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes; | |
193 | ||
194 | return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s)); | |
195 | } | |
196 | ||
197 | #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \ | |
198 | static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \ | |
199 | { \ | |
200 | __type v; \ | |
201 | u32 mx = pic32_rx_max(pic32s, sizeof(__type)); \ | |
202 | for (; mx; mx--) { \ | |
203 | v = read##__bwl(&pic32s->regs->buf); \ | |
204 | if (pic32s->rx_end - pic32s->len) \ | |
205 | *(__type *)(pic32s->rx) = v; \ | |
206 | pic32s->rx += sizeof(__type); \ | |
207 | } \ | |
208 | } \ | |
209 | \ | |
210 | static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \ | |
211 | { \ | |
212 | __type v; \ | |
213 | u32 mx = pic32_tx_max(pic32s, sizeof(__type)); \ | |
214 | for (; mx ; mx--) { \ | |
215 | v = (__type)~0U; \ | |
216 | if (pic32s->tx_end - pic32s->len) \ | |
217 | v = *(__type *)(pic32s->tx); \ | |
218 | write##__bwl(v, &pic32s->regs->buf); \ | |
219 | pic32s->tx += sizeof(__type); \ | |
220 | } \ | |
221 | } | |
222 | ||
223 | BUILD_SPI_FIFO_RW(byte, u8, b); | |
224 | BUILD_SPI_FIFO_RW(word, u16, w); | |
225 | BUILD_SPI_FIFO_RW(dword, u32, l); | |
226 | ||
227 | static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg) | |
228 | { | |
229 | /* disable all interrupts */ | |
230 | disable_irq_nosync(pic32s->fault_irq); | |
231 | disable_irq_nosync(pic32s->rx_irq); | |
232 | disable_irq_nosync(pic32s->tx_irq); | |
233 | ||
234 | /* Show err message and abort xfer with err */ | |
235 | dev_err(&pic32s->master->dev, "%s\n", msg); | |
236 | if (pic32s->master->cur_msg) | |
237 | pic32s->master->cur_msg->status = -EIO; | |
238 | complete(&pic32s->xfer_done); | |
239 | } | |
240 | ||
241 | static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id) | |
242 | { | |
243 | struct pic32_spi *pic32s = dev_id; | |
244 | u32 status; | |
245 | ||
246 | status = readl(&pic32s->regs->status); | |
247 | ||
248 | /* Error handling */ | |
249 | if (status & (STAT_RX_OV | STAT_TX_UR)) { | |
250 | writel(STAT_RX_OV, &pic32s->regs->status_clr); | |
251 | writel(STAT_TX_UR, &pic32s->regs->status_clr); | |
252 | pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n"); | |
253 | return IRQ_HANDLED; | |
254 | } | |
255 | ||
256 | if (status & STAT_FRM_ERR) { | |
257 | pic32_err_stop(pic32s, "err_irq: frame error"); | |
258 | return IRQ_HANDLED; | |
259 | } | |
260 | ||
261 | if (!pic32s->master->cur_msg) { | |
262 | pic32_err_stop(pic32s, "err_irq: no mesg"); | |
263 | return IRQ_NONE; | |
264 | } | |
265 | ||
266 | return IRQ_NONE; | |
267 | } | |
268 | ||
269 | static irqreturn_t pic32_spi_rx_irq(int irq, void *dev_id) | |
270 | { | |
271 | struct pic32_spi *pic32s = dev_id; | |
272 | ||
273 | pic32s->rx_fifo(pic32s); | |
274 | ||
275 | /* rx complete ? */ | |
276 | if (pic32s->rx_end == pic32s->rx) { | |
277 | /* disable all interrupts */ | |
278 | disable_irq_nosync(pic32s->fault_irq); | |
279 | disable_irq_nosync(pic32s->rx_irq); | |
280 | ||
281 | /* complete current xfer */ | |
282 | complete(&pic32s->xfer_done); | |
283 | } | |
284 | ||
285 | return IRQ_HANDLED; | |
286 | } | |
287 | ||
288 | static irqreturn_t pic32_spi_tx_irq(int irq, void *dev_id) | |
289 | { | |
290 | struct pic32_spi *pic32s = dev_id; | |
291 | ||
292 | pic32s->tx_fifo(pic32s); | |
293 | ||
294 | /* tx complete? disable tx interrupt */ | |
295 | if (pic32s->tx_end == pic32s->tx) | |
296 | disable_irq_nosync(pic32s->tx_irq); | |
297 | ||
298 | return IRQ_HANDLED; | |
299 | } | |
300 | ||
301 | static void pic32_spi_dma_rx_notify(void *data) | |
302 | { | |
303 | struct pic32_spi *pic32s = data; | |
304 | ||
305 | complete(&pic32s->xfer_done); | |
306 | } | |
307 | ||
308 | static int pic32_spi_dma_transfer(struct pic32_spi *pic32s, | |
309 | struct spi_transfer *xfer) | |
310 | { | |
311 | struct spi_master *master = pic32s->master; | |
312 | struct dma_async_tx_descriptor *desc_rx; | |
313 | struct dma_async_tx_descriptor *desc_tx; | |
314 | dma_cookie_t cookie; | |
315 | int ret; | |
316 | ||
317 | if (!master->dma_rx || !master->dma_tx) | |
318 | return -ENODEV; | |
319 | ||
320 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, | |
321 | xfer->rx_sg.sgl, | |
322 | xfer->rx_sg.nents, | |
323 | DMA_FROM_DEVICE, | |
324 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
325 | if (!desc_rx) { | |
326 | ret = -EINVAL; | |
327 | goto err_dma; | |
328 | } | |
329 | ||
330 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, | |
331 | xfer->tx_sg.sgl, | |
332 | xfer->tx_sg.nents, | |
333 | DMA_TO_DEVICE, | |
334 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
335 | if (!desc_tx) { | |
336 | ret = -EINVAL; | |
337 | goto err_dma; | |
338 | } | |
339 | ||
340 | /* Put callback on the RX transfer, that should finish last */ | |
341 | desc_rx->callback = pic32_spi_dma_rx_notify; | |
342 | desc_rx->callback_param = pic32s; | |
343 | ||
344 | cookie = dmaengine_submit(desc_rx); | |
345 | ret = dma_submit_error(cookie); | |
346 | if (ret) | |
347 | goto err_dma; | |
348 | ||
349 | cookie = dmaengine_submit(desc_tx); | |
350 | ret = dma_submit_error(cookie); | |
351 | if (ret) | |
352 | goto err_dma_tx; | |
353 | ||
354 | dma_async_issue_pending(master->dma_rx); | |
355 | dma_async_issue_pending(master->dma_tx); | |
356 | ||
357 | return 0; | |
358 | ||
359 | err_dma_tx: | |
360 | dmaengine_terminate_all(master->dma_rx); | |
361 | err_dma: | |
362 | return ret; | |
363 | } | |
364 | ||
365 | static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width) | |
366 | { | |
367 | int buf_offset = offsetof(struct pic32_spi_regs, buf); | |
368 | struct spi_master *master = pic32s->master; | |
369 | struct dma_slave_config cfg; | |
370 | int ret; | |
371 | ||
372 | cfg.device_fc = true; | |
373 | cfg.src_addr = pic32s->dma_base + buf_offset; | |
374 | cfg.dst_addr = pic32s->dma_base + buf_offset; | |
375 | cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */ | |
376 | cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */ | |
377 | cfg.src_addr_width = dma_width; | |
378 | cfg.dst_addr_width = dma_width; | |
379 | /* tx channel */ | |
380 | cfg.slave_id = pic32s->tx_irq; | |
381 | cfg.direction = DMA_MEM_TO_DEV; | |
382 | ret = dmaengine_slave_config(master->dma_tx, &cfg); | |
383 | if (ret) { | |
384 | dev_err(&master->dev, "tx channel setup failed\n"); | |
385 | return ret; | |
386 | } | |
387 | /* rx channel */ | |
388 | cfg.slave_id = pic32s->rx_irq; | |
389 | cfg.direction = DMA_DEV_TO_MEM; | |
390 | ret = dmaengine_slave_config(master->dma_rx, &cfg); | |
391 | if (ret) | |
392 | dev_err(&master->dev, "rx channel setup failed\n"); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
397 | static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word) | |
398 | { | |
399 | enum dma_slave_buswidth dmawidth; | |
400 | u32 buswidth, v; | |
401 | ||
402 | switch (bits_per_word) { | |
403 | case 8: | |
404 | pic32s->rx_fifo = pic32_spi_rx_byte; | |
405 | pic32s->tx_fifo = pic32_spi_tx_byte; | |
406 | buswidth = PIC32_BPW_8; | |
407 | dmawidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
408 | break; | |
409 | case 16: | |
410 | pic32s->rx_fifo = pic32_spi_rx_word; | |
411 | pic32s->tx_fifo = pic32_spi_tx_word; | |
412 | buswidth = PIC32_BPW_16; | |
413 | dmawidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
414 | break; | |
415 | case 32: | |
416 | pic32s->rx_fifo = pic32_spi_rx_dword; | |
417 | pic32s->tx_fifo = pic32_spi_tx_dword; | |
418 | buswidth = PIC32_BPW_32; | |
419 | dmawidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
420 | break; | |
421 | default: | |
422 | /* not supported */ | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | /* calculate maximum number of words fifos can hold */ | |
427 | pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte, | |
428 | bits_per_word / 8); | |
429 | /* set word size */ | |
430 | v = readl(&pic32s->regs->ctrl); | |
431 | v &= ~(CTRL_BPW_MASK << CTRL_BPW_SHIFT); | |
432 | v |= buswidth << CTRL_BPW_SHIFT; | |
433 | writel(v, &pic32s->regs->ctrl); | |
434 | ||
435 | /* re-configure dma width, if required */ | |
436 | if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) | |
437 | pic32_spi_dma_config(pic32s, dmawidth); | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
442 | static int pic32_spi_prepare_hardware(struct spi_master *master) | |
443 | { | |
444 | struct pic32_spi *pic32s = spi_master_get_devdata(master); | |
445 | ||
446 | pic32_spi_enable(pic32s); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static int pic32_spi_prepare_message(struct spi_master *master, | |
452 | struct spi_message *msg) | |
453 | { | |
454 | struct pic32_spi *pic32s = spi_master_get_devdata(master); | |
455 | struct spi_device *spi = msg->spi; | |
456 | u32 val; | |
457 | ||
458 | /* set device specific bits_per_word */ | |
459 | if (pic32s->bits_per_word != spi->bits_per_word) { | |
460 | pic32_spi_set_word_size(pic32s, spi->bits_per_word); | |
461 | pic32s->bits_per_word = spi->bits_per_word; | |
462 | } | |
463 | ||
464 | /* device specific speed change */ | |
465 | if (pic32s->speed_hz != spi->max_speed_hz) { | |
466 | pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz); | |
467 | pic32s->speed_hz = spi->max_speed_hz; | |
468 | } | |
469 | ||
470 | /* device specific mode change */ | |
471 | if (pic32s->mode != spi->mode) { | |
472 | val = readl(&pic32s->regs->ctrl); | |
473 | /* active low */ | |
474 | if (spi->mode & SPI_CPOL) | |
475 | val |= CTRL_CKP; | |
476 | else | |
477 | val &= ~CTRL_CKP; | |
478 | /* tx on rising edge */ | |
479 | if (spi->mode & SPI_CPHA) | |
480 | val &= ~CTRL_CKE; | |
481 | else | |
482 | val |= CTRL_CKE; | |
483 | ||
484 | /* rx at end of tx */ | |
485 | val |= CTRL_SMP; | |
486 | writel(val, &pic32s->regs->ctrl); | |
487 | pic32s->mode = spi->mode; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static bool pic32_spi_can_dma(struct spi_master *master, | |
494 | struct spi_device *spi, | |
495 | struct spi_transfer *xfer) | |
496 | { | |
497 | struct pic32_spi *pic32s = spi_master_get_devdata(master); | |
498 | ||
499 | /* skip using DMA on small size transfer to avoid overhead.*/ | |
500 | return (xfer->len >= PIC32_DMA_LEN_MIN) && | |
501 | test_bit(PIC32F_DMA_PREP, &pic32s->flags); | |
502 | } | |
503 | ||
504 | static int pic32_spi_one_transfer(struct spi_master *master, | |
505 | struct spi_device *spi, | |
506 | struct spi_transfer *transfer) | |
507 | { | |
508 | struct pic32_spi *pic32s; | |
509 | bool dma_issued = false; | |
57c2b0dd | 510 | unsigned long timeout; |
1bcb9f8c PCM |
511 | int ret; |
512 | ||
513 | pic32s = spi_master_get_devdata(master); | |
514 | ||
515 | /* handle transfer specific word size change */ | |
516 | if (transfer->bits_per_word && | |
517 | (transfer->bits_per_word != pic32s->bits_per_word)) { | |
518 | ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word); | |
519 | if (ret) | |
520 | return ret; | |
521 | pic32s->bits_per_word = transfer->bits_per_word; | |
522 | } | |
523 | ||
524 | /* handle transfer specific speed change */ | |
525 | if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) { | |
526 | pic32_spi_set_clk_rate(pic32s, transfer->speed_hz); | |
527 | pic32s->speed_hz = transfer->speed_hz; | |
528 | } | |
529 | ||
530 | reinit_completion(&pic32s->xfer_done); | |
531 | ||
532 | /* transact by DMA mode */ | |
533 | if (transfer->rx_sg.nents && transfer->tx_sg.nents) { | |
534 | ret = pic32_spi_dma_transfer(pic32s, transfer); | |
535 | if (ret) { | |
536 | dev_err(&spi->dev, "dma submit error\n"); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | /* DMA issued */ | |
541 | dma_issued = true; | |
542 | } else { | |
543 | /* set current transfer information */ | |
544 | pic32s->tx = (const void *)transfer->tx_buf; | |
545 | pic32s->rx = (const void *)transfer->rx_buf; | |
546 | pic32s->tx_end = pic32s->tx + transfer->len; | |
547 | pic32s->rx_end = pic32s->rx + transfer->len; | |
548 | pic32s->len = transfer->len; | |
549 | ||
550 | /* transact by interrupt driven PIO */ | |
551 | enable_irq(pic32s->fault_irq); | |
552 | enable_irq(pic32s->rx_irq); | |
553 | enable_irq(pic32s->tx_irq); | |
554 | } | |
555 | ||
556 | /* wait for completion */ | |
57c2b0dd NMG |
557 | timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ); |
558 | if (timeout == 0) { | |
1bcb9f8c PCM |
559 | dev_err(&spi->dev, "wait error/timedout\n"); |
560 | if (dma_issued) { | |
561 | dmaengine_terminate_all(master->dma_rx); | |
562 | dmaengine_terminate_all(master->dma_rx); | |
563 | } | |
564 | ret = -ETIMEDOUT; | |
565 | } else { | |
566 | ret = 0; | |
567 | } | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | static int pic32_spi_unprepare_message(struct spi_master *master, | |
573 | struct spi_message *msg) | |
574 | { | |
575 | /* nothing to do */ | |
576 | return 0; | |
577 | } | |
578 | ||
579 | static int pic32_spi_unprepare_hardware(struct spi_master *master) | |
580 | { | |
581 | struct pic32_spi *pic32s = spi_master_get_devdata(master); | |
582 | ||
583 | pic32_spi_disable(pic32s); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | /* This may be called multiple times by same spi dev */ | |
589 | static int pic32_spi_setup(struct spi_device *spi) | |
590 | { | |
591 | if (!spi->max_speed_hz) { | |
592 | dev_err(&spi->dev, "No max speed HZ parameter\n"); | |
593 | return -EINVAL; | |
594 | } | |
595 | ||
1bcb9f8c PCM |
596 | /* PIC32 spi controller can drive /CS during transfer depending |
597 | * on tx fifo fill-level. /CS will stay asserted as long as TX | |
598 | * fifo is non-empty, else will be deasserted indicating | |
599 | * completion of the ongoing transfer. This might result into | |
600 | * unreliable/erroneous SPI transactions. | |
601 | * To avoid that we will always handle /CS by toggling GPIO. | |
602 | */ | |
603 | if (!gpio_is_valid(spi->cs_gpio)) | |
604 | return -EINVAL; | |
605 | ||
606 | gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static void pic32_spi_cleanup(struct spi_device *spi) | |
612 | { | |
613 | /* de-activate cs-gpio */ | |
614 | gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
615 | } | |
616 | ||
617 | static void pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev) | |
618 | { | |
619 | struct spi_master *master = pic32s->master; | |
620 | dma_cap_mask_t mask; | |
621 | ||
622 | dma_cap_zero(mask); | |
623 | dma_cap_set(DMA_SLAVE, mask); | |
624 | ||
625 | master->dma_rx = dma_request_slave_channel_compat(mask, NULL, NULL, | |
626 | dev, "spi-rx"); | |
627 | if (!master->dma_rx) { | |
628 | dev_warn(dev, "RX channel not found.\n"); | |
629 | goto out_err; | |
630 | } | |
631 | ||
632 | master->dma_tx = dma_request_slave_channel_compat(mask, NULL, NULL, | |
633 | dev, "spi-tx"); | |
634 | if (!master->dma_tx) { | |
635 | dev_warn(dev, "TX channel not found.\n"); | |
636 | goto out_err; | |
637 | } | |
638 | ||
639 | if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE)) | |
640 | goto out_err; | |
641 | ||
642 | /* DMA chnls allocated and prepared */ | |
643 | set_bit(PIC32F_DMA_PREP, &pic32s->flags); | |
644 | ||
645 | return; | |
646 | ||
647 | out_err: | |
648 | if (master->dma_rx) | |
649 | dma_release_channel(master->dma_rx); | |
650 | ||
651 | if (master->dma_tx) | |
652 | dma_release_channel(master->dma_tx); | |
653 | } | |
654 | ||
655 | static void pic32_spi_dma_unprep(struct pic32_spi *pic32s) | |
656 | { | |
657 | if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags)) | |
658 | return; | |
659 | ||
660 | clear_bit(PIC32F_DMA_PREP, &pic32s->flags); | |
661 | if (pic32s->master->dma_rx) | |
662 | dma_release_channel(pic32s->master->dma_rx); | |
663 | ||
664 | if (pic32s->master->dma_tx) | |
665 | dma_release_channel(pic32s->master->dma_tx); | |
666 | } | |
667 | ||
668 | static void pic32_spi_hw_init(struct pic32_spi *pic32s) | |
669 | { | |
670 | u32 ctrl; | |
671 | ||
672 | /* disable hardware */ | |
673 | pic32_spi_disable(pic32s); | |
674 | ||
675 | ctrl = readl(&pic32s->regs->ctrl); | |
676 | /* enable enhanced fifo of 128bit deep */ | |
677 | ctrl |= CTRL_ENHBUF; | |
678 | pic32s->fifo_n_byte = 16; | |
679 | ||
680 | /* disable framing mode */ | |
681 | ctrl &= ~CTRL_FRMEN; | |
682 | ||
683 | /* enable master mode while disabled */ | |
684 | ctrl |= CTRL_MSTEN; | |
685 | ||
686 | /* set tx fifo threshold interrupt */ | |
687 | ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT); | |
688 | ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT); | |
689 | ||
690 | /* set rx fifo threshold interrupt */ | |
691 | ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT); | |
692 | ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT); | |
693 | ||
694 | /* select clk source */ | |
695 | ctrl &= ~CTRL_MCLKSEL; | |
696 | ||
697 | /* set manual /CS mode */ | |
698 | ctrl &= ~CTRL_MSSEN; | |
699 | ||
700 | writel(ctrl, &pic32s->regs->ctrl); | |
701 | ||
702 | /* enable error reporting */ | |
703 | ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN; | |
704 | writel(ctrl, &pic32s->regs->ctrl2_set); | |
705 | } | |
706 | ||
707 | static int pic32_spi_hw_probe(struct platform_device *pdev, | |
708 | struct pic32_spi *pic32s) | |
709 | { | |
710 | struct resource *mem; | |
711 | int ret; | |
712 | ||
713 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
714 | pic32s->regs = devm_ioremap_resource(&pdev->dev, mem); | |
866e48b0 AL |
715 | if (IS_ERR(pic32s->regs)) |
716 | return PTR_ERR(pic32s->regs); | |
717 | ||
1bcb9f8c PCM |
718 | pic32s->dma_base = mem->start; |
719 | ||
720 | /* get irq resources: err-irq, rx-irq, tx-irq */ | |
721 | pic32s->fault_irq = platform_get_irq_byname(pdev, "fault"); | |
722 | if (pic32s->fault_irq < 0) { | |
723 | dev_err(&pdev->dev, "fault-irq not found\n"); | |
724 | return pic32s->fault_irq; | |
725 | } | |
726 | ||
727 | pic32s->rx_irq = platform_get_irq_byname(pdev, "rx"); | |
728 | if (pic32s->rx_irq < 0) { | |
729 | dev_err(&pdev->dev, "rx-irq not found\n"); | |
730 | return pic32s->rx_irq; | |
731 | } | |
732 | ||
733 | pic32s->tx_irq = platform_get_irq_byname(pdev, "tx"); | |
734 | if (pic32s->tx_irq < 0) { | |
735 | dev_err(&pdev->dev, "tx-irq not found\n"); | |
736 | return pic32s->tx_irq; | |
737 | } | |
738 | ||
739 | /* get clock */ | |
740 | pic32s->clk = devm_clk_get(&pdev->dev, "mck0"); | |
741 | if (IS_ERR(pic32s->clk)) { | |
742 | dev_err(&pdev->dev, "clk not found\n"); | |
743 | ret = PTR_ERR(pic32s->clk); | |
744 | goto err_unmap_mem; | |
745 | } | |
746 | ||
747 | ret = clk_prepare_enable(pic32s->clk); | |
748 | if (ret) | |
749 | goto err_unmap_mem; | |
750 | ||
751 | pic32_spi_hw_init(pic32s); | |
752 | ||
753 | return 0; | |
754 | ||
755 | err_unmap_mem: | |
756 | dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret); | |
757 | return ret; | |
758 | } | |
759 | ||
760 | static int pic32_spi_probe(struct platform_device *pdev) | |
761 | { | |
762 | struct spi_master *master; | |
763 | struct pic32_spi *pic32s; | |
764 | int ret; | |
765 | ||
766 | master = spi_alloc_master(&pdev->dev, sizeof(*pic32s)); | |
767 | if (!master) | |
768 | return -ENOMEM; | |
769 | ||
770 | pic32s = spi_master_get_devdata(master); | |
771 | pic32s->master = master; | |
772 | ||
773 | ret = pic32_spi_hw_probe(pdev, pic32s); | |
774 | if (ret) | |
775 | goto err_master; | |
776 | ||
777 | master->dev.of_node = of_node_get(pdev->dev.of_node); | |
778 | master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH; | |
779 | master->num_chipselect = 1; /* single chip-select */ | |
780 | master->max_speed_hz = clk_get_rate(pic32s->clk); | |
781 | master->setup = pic32_spi_setup; | |
782 | master->cleanup = pic32_spi_cleanup; | |
783 | master->flags = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX; | |
2452ee25 AL |
784 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | |
785 | SPI_BPW_MASK(32); | |
1bcb9f8c PCM |
786 | master->transfer_one = pic32_spi_one_transfer; |
787 | master->prepare_message = pic32_spi_prepare_message; | |
788 | master->unprepare_message = pic32_spi_unprepare_message; | |
789 | master->prepare_transfer_hardware = pic32_spi_prepare_hardware; | |
790 | master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware; | |
791 | ||
792 | /* optional DMA support */ | |
793 | pic32_spi_dma_prep(pic32s, &pdev->dev); | |
794 | if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) | |
795 | master->can_dma = pic32_spi_can_dma; | |
796 | ||
797 | init_completion(&pic32s->xfer_done); | |
798 | pic32s->mode = -1; | |
799 | ||
800 | /* install irq handlers (with irq-disabled) */ | |
801 | irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN); | |
802 | ret = devm_request_irq(&pdev->dev, pic32s->fault_irq, | |
803 | pic32_spi_fault_irq, IRQF_NO_THREAD, | |
804 | dev_name(&pdev->dev), pic32s); | |
805 | if (ret < 0) { | |
806 | dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq); | |
807 | goto err_bailout; | |
808 | } | |
809 | ||
810 | /* receive interrupt handler */ | |
811 | irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN); | |
812 | ret = devm_request_irq(&pdev->dev, pic32s->rx_irq, | |
813 | pic32_spi_rx_irq, IRQF_NO_THREAD, | |
814 | dev_name(&pdev->dev), pic32s); | |
815 | if (ret < 0) { | |
816 | dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq); | |
817 | goto err_bailout; | |
818 | } | |
819 | ||
820 | /* transmit interrupt handler */ | |
821 | irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN); | |
822 | ret = devm_request_irq(&pdev->dev, pic32s->tx_irq, | |
823 | pic32_spi_tx_irq, IRQF_NO_THREAD, | |
824 | dev_name(&pdev->dev), pic32s); | |
825 | if (ret < 0) { | |
826 | dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq); | |
827 | goto err_bailout; | |
828 | } | |
829 | ||
830 | /* register master */ | |
831 | ret = devm_spi_register_master(&pdev->dev, master); | |
832 | if (ret) { | |
833 | dev_err(&master->dev, "failed registering spi master\n"); | |
834 | goto err_bailout; | |
835 | } | |
836 | ||
837 | platform_set_drvdata(pdev, pic32s); | |
838 | ||
839 | return 0; | |
840 | ||
841 | err_bailout: | |
842 | clk_disable_unprepare(pic32s->clk); | |
843 | err_master: | |
844 | spi_master_put(master); | |
845 | return ret; | |
846 | } | |
847 | ||
848 | static int pic32_spi_remove(struct platform_device *pdev) | |
849 | { | |
850 | struct pic32_spi *pic32s; | |
851 | ||
852 | pic32s = platform_get_drvdata(pdev); | |
853 | pic32_spi_disable(pic32s); | |
854 | clk_disable_unprepare(pic32s->clk); | |
855 | pic32_spi_dma_unprep(pic32s); | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | static const struct of_device_id pic32_spi_of_match[] = { | |
861 | {.compatible = "microchip,pic32mzda-spi",}, | |
862 | {}, | |
863 | }; | |
864 | MODULE_DEVICE_TABLE(of, pic32_spi_of_match); | |
865 | ||
866 | static struct platform_driver pic32_spi_driver = { | |
867 | .driver = { | |
868 | .name = "spi-pic32", | |
869 | .of_match_table = of_match_ptr(pic32_spi_of_match), | |
870 | }, | |
871 | .probe = pic32_spi_probe, | |
872 | .remove = pic32_spi_remove, | |
873 | }; | |
874 | ||
875 | module_platform_driver(pic32_spi_driver); | |
876 | ||
877 | MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>"); | |
878 | MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SPI controller."); | |
879 | MODULE_LICENSE("GPL v2"); |