Commit | Line | Data |
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b43d65f7 | 1 | /* |
b43d65f7 LW |
2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
3 | * | |
4 | * Copyright (C) 2008-2009 ST-Ericsson AB | |
5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. | |
6 | * | |
7 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
8 | * | |
9 | * Initial version inspired by: | |
10 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c | |
11 | * Initial adoption to PL022 by: | |
12 | * Sachin Verma <sachin.verma@st.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | */ | |
24 | ||
b43d65f7 LW |
25 | #include <linux/init.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/spi/spi.h> | |
32 | #include <linux/workqueue.h> | |
b43d65f7 LW |
33 | #include <linux/delay.h> |
34 | #include <linux/clk.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/amba/bus.h> | |
37 | #include <linux/amba/pl022.h> | |
38 | #include <linux/io.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
b1b6b9aa LW |
40 | #include <linux/dmaengine.h> |
41 | #include <linux/dma-mapping.h> | |
42 | #include <linux/scatterlist.h> | |
b43d65f7 LW |
43 | |
44 | /* | |
45 | * This macro is used to define some register default values. | |
46 | * reg is masked with mask, the OR:ed with an (again masked) | |
47 | * val shifted sb steps to the left. | |
48 | */ | |
49 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ | |
50 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) | |
51 | ||
52 | /* | |
53 | * This macro is also used to define some default values. | |
54 | * It will just shift val by sb steps to the left and mask | |
55 | * the result with mask. | |
56 | */ | |
57 | #define GEN_MASK_BITS(val, mask, sb) \ | |
58 | (((val)<<(sb)) & (mask)) | |
59 | ||
60 | #define DRIVE_TX 0 | |
61 | #define DO_NOT_DRIVE_TX 1 | |
62 | ||
63 | #define DO_NOT_QUEUE_DMA 0 | |
64 | #define QUEUE_DMA 1 | |
65 | ||
66 | #define RX_TRANSFER 1 | |
67 | #define TX_TRANSFER 2 | |
68 | ||
69 | /* | |
70 | * Macros to access SSP Registers with their offsets | |
71 | */ | |
72 | #define SSP_CR0(r) (r + 0x000) | |
73 | #define SSP_CR1(r) (r + 0x004) | |
74 | #define SSP_DR(r) (r + 0x008) | |
75 | #define SSP_SR(r) (r + 0x00C) | |
76 | #define SSP_CPSR(r) (r + 0x010) | |
77 | #define SSP_IMSC(r) (r + 0x014) | |
78 | #define SSP_RIS(r) (r + 0x018) | |
79 | #define SSP_MIS(r) (r + 0x01C) | |
80 | #define SSP_ICR(r) (r + 0x020) | |
81 | #define SSP_DMACR(r) (r + 0x024) | |
82 | #define SSP_ITCR(r) (r + 0x080) | |
83 | #define SSP_ITIP(r) (r + 0x084) | |
84 | #define SSP_ITOP(r) (r + 0x088) | |
85 | #define SSP_TDR(r) (r + 0x08C) | |
86 | ||
87 | #define SSP_PID0(r) (r + 0xFE0) | |
88 | #define SSP_PID1(r) (r + 0xFE4) | |
89 | #define SSP_PID2(r) (r + 0xFE8) | |
90 | #define SSP_PID3(r) (r + 0xFEC) | |
91 | ||
92 | #define SSP_CID0(r) (r + 0xFF0) | |
93 | #define SSP_CID1(r) (r + 0xFF4) | |
94 | #define SSP_CID2(r) (r + 0xFF8) | |
95 | #define SSP_CID3(r) (r + 0xFFC) | |
96 | ||
97 | /* | |
98 | * SSP Control Register 0 - SSP_CR0 | |
99 | */ | |
556f4aeb LW |
100 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
101 | #define SSP_CR0_MASK_FRF (0x3UL << 4) | |
b43d65f7 LW |
102 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
103 | #define SSP_CR0_MASK_SPH (0x1UL << 7) | |
104 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) | |
556f4aeb LW |
105 | |
106 | /* | |
107 | * The ST version of this block moves som bits | |
108 | * in SSP_CR0 and extends it to 32 bits | |
109 | */ | |
110 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) | |
111 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) | |
112 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | |
113 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | |
114 | ||
b43d65f7 LW |
115 | |
116 | /* | |
117 | * SSP Control Register 0 - SSP_CR1 | |
118 | */ | |
119 | #define SSP_CR1_MASK_LBM (0x1UL << 0) | |
120 | #define SSP_CR1_MASK_SSE (0x1UL << 1) | |
121 | #define SSP_CR1_MASK_MS (0x1UL << 2) | |
122 | #define SSP_CR1_MASK_SOD (0x1UL << 3) | |
b43d65f7 LW |
123 | |
124 | /* | |
556f4aeb LW |
125 | * The ST version of this block adds some bits |
126 | * in SSP_CR1 | |
b43d65f7 | 127 | */ |
556f4aeb LW |
128 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
129 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) | |
130 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) | |
131 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) | |
132 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) | |
781c7b12 LW |
133 | /* This one is only in the PL023 variant */ |
134 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) | |
b43d65f7 LW |
135 | |
136 | /* | |
137 | * SSP Status Register - SSP_SR | |
138 | */ | |
139 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ | |
140 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ | |
141 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ | |
556f4aeb | 142 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
b43d65f7 LW |
143 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
144 | ||
145 | /* | |
146 | * SSP Clock Prescale Register - SSP_CPSR | |
147 | */ | |
148 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) | |
149 | ||
150 | /* | |
151 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC | |
152 | */ | |
153 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ | |
154 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ | |
155 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ | |
156 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ | |
157 | ||
158 | /* | |
159 | * SSP Raw Interrupt Status Register - SSP_RIS | |
160 | */ | |
161 | /* Receive Overrun Raw Interrupt status */ | |
162 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) | |
163 | /* Receive Timeout Raw Interrupt status */ | |
164 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) | |
165 | /* Receive FIFO Raw Interrupt status */ | |
166 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) | |
167 | /* Transmit FIFO Raw Interrupt status */ | |
168 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) | |
169 | ||
170 | /* | |
171 | * SSP Masked Interrupt Status Register - SSP_MIS | |
172 | */ | |
173 | /* Receive Overrun Masked Interrupt status */ | |
174 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) | |
175 | /* Receive Timeout Masked Interrupt status */ | |
176 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) | |
177 | /* Receive FIFO Masked Interrupt status */ | |
178 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) | |
179 | /* Transmit FIFO Masked Interrupt status */ | |
180 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) | |
181 | ||
182 | /* | |
183 | * SSP Interrupt Clear Register - SSP_ICR | |
184 | */ | |
185 | /* Receive Overrun Raw Clear Interrupt bit */ | |
186 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) | |
187 | /* Receive Timeout Clear Interrupt bit */ | |
188 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) | |
189 | ||
190 | /* | |
191 | * SSP DMA Control Register - SSP_DMACR | |
192 | */ | |
193 | /* Receive DMA Enable bit */ | |
194 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) | |
195 | /* Transmit DMA Enable bit */ | |
196 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) | |
197 | ||
198 | /* | |
199 | * SSP Integration Test control Register - SSP_ITCR | |
200 | */ | |
201 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) | |
202 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) | |
203 | ||
204 | /* | |
205 | * SSP Integration Test Input Register - SSP_ITIP | |
206 | */ | |
207 | #define ITIP_MASK_SSPRXD (0x1UL << 0) | |
208 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) | |
209 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) | |
210 | #define ITIP_MASK_RXDMAC (0x1UL << 3) | |
211 | #define ITIP_MASK_TXDMAC (0x1UL << 4) | |
212 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) | |
213 | ||
214 | /* | |
215 | * SSP Integration Test output Register - SSP_ITOP | |
216 | */ | |
217 | #define ITOP_MASK_SSPTXD (0x1UL << 0) | |
218 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) | |
219 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) | |
220 | #define ITOP_MASK_SSPOEn (0x1UL << 3) | |
221 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) | |
222 | #define ITOP_MASK_RORINTR (0x1UL << 5) | |
223 | #define ITOP_MASK_RTINTR (0x1UL << 6) | |
224 | #define ITOP_MASK_RXINTR (0x1UL << 7) | |
225 | #define ITOP_MASK_TXINTR (0x1UL << 8) | |
226 | #define ITOP_MASK_INTR (0x1UL << 9) | |
227 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) | |
228 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) | |
229 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) | |
230 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) | |
231 | ||
232 | /* | |
233 | * SSP Test Data Register - SSP_TDR | |
234 | */ | |
556f4aeb | 235 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
b43d65f7 LW |
236 | |
237 | /* | |
238 | * Message State | |
239 | * we use the spi_message.state (void *) pointer to | |
240 | * hold a single state value, that's why all this | |
241 | * (void *) casting is done here. | |
242 | */ | |
556f4aeb LW |
243 | #define STATE_START ((void *) 0) |
244 | #define STATE_RUNNING ((void *) 1) | |
245 | #define STATE_DONE ((void *) 2) | |
246 | #define STATE_ERROR ((void *) -1) | |
b43d65f7 | 247 | |
b43d65f7 LW |
248 | /* |
249 | * SSP State - Whether Enabled or Disabled | |
250 | */ | |
556f4aeb LW |
251 | #define SSP_DISABLED (0) |
252 | #define SSP_ENABLED (1) | |
b43d65f7 LW |
253 | |
254 | /* | |
255 | * SSP DMA State - Whether DMA Enabled or Disabled | |
256 | */ | |
556f4aeb LW |
257 | #define SSP_DMA_DISABLED (0) |
258 | #define SSP_DMA_ENABLED (1) | |
b43d65f7 LW |
259 | |
260 | /* | |
261 | * SSP Clock Defaults | |
262 | */ | |
556f4aeb LW |
263 | #define SSP_DEFAULT_CLKRATE 0x2 |
264 | #define SSP_DEFAULT_PRESCALE 0x40 | |
b43d65f7 LW |
265 | |
266 | /* | |
267 | * SSP Clock Parameter ranges | |
268 | */ | |
269 | #define CPSDVR_MIN 0x02 | |
270 | #define CPSDVR_MAX 0xFE | |
271 | #define SCR_MIN 0x00 | |
272 | #define SCR_MAX 0xFF | |
273 | ||
274 | /* | |
275 | * SSP Interrupt related Macros | |
276 | */ | |
277 | #define DEFAULT_SSP_REG_IMSC 0x0UL | |
278 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC | |
279 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) | |
280 | ||
281 | #define CLEAR_ALL_INTERRUPTS 0x3 | |
282 | ||
a18c266f MT |
283 | #define SPI_POLLING_TIMEOUT 1000 |
284 | ||
b43d65f7 LW |
285 | |
286 | /* | |
287 | * The type of reading going on on this chip | |
288 | */ | |
289 | enum ssp_reading { | |
290 | READING_NULL, | |
291 | READING_U8, | |
292 | READING_U16, | |
293 | READING_U32 | |
294 | }; | |
295 | ||
296 | /** | |
297 | * The type of writing going on on this chip | |
298 | */ | |
299 | enum ssp_writing { | |
300 | WRITING_NULL, | |
301 | WRITING_U8, | |
302 | WRITING_U16, | |
303 | WRITING_U32 | |
304 | }; | |
305 | ||
306 | /** | |
307 | * struct vendor_data - vendor-specific config parameters | |
308 | * for PL022 derivates | |
309 | * @fifodepth: depth of FIFOs (both) | |
310 | * @max_bpw: maximum number of bits per word | |
311 | * @unidir: supports unidirection transfers | |
556f4aeb LW |
312 | * @extended_cr: 32 bit wide control register 0 with extra |
313 | * features and extra features in CR1 as found in the ST variants | |
781c7b12 | 314 | * @pl023: supports a subset of the ST extensions called "PL023" |
b43d65f7 LW |
315 | */ |
316 | struct vendor_data { | |
317 | int fifodepth; | |
318 | int max_bpw; | |
319 | bool unidir; | |
556f4aeb | 320 | bool extended_cr; |
781c7b12 | 321 | bool pl023; |
06fb01fd | 322 | bool loopback; |
b43d65f7 LW |
323 | }; |
324 | ||
325 | /** | |
326 | * struct pl022 - This is the private SSP driver data structure | |
327 | * @adev: AMBA device model hookup | |
12e8b325 LW |
328 | * @vendor: vendor data for the IP block |
329 | * @phybase: the physical memory where the SSP device resides | |
330 | * @virtbase: the virtual memory where the SSP is mapped | |
331 | * @clk: outgoing clock "SPICLK" for the SPI bus | |
b43d65f7 LW |
332 | * @master: SPI framework hookup |
333 | * @master_info: controller-specific data from machine setup | |
b43d65f7 | 334 | * @workqueue: a workqueue on which any spi_message request is queued |
12e8b325 LW |
335 | * @pump_messages: work struct for scheduling work to the workqueue |
336 | * @queue_lock: spinlock to syncronise access to message queue | |
337 | * @queue: message queue | |
b43d65f7 | 338 | * @busy: workqueue is busy |
5e8b821d | 339 | * @running: workqueue is running |
b43d65f7 LW |
340 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
341 | * @cur_msg: Pointer to current spi_message being processed | |
342 | * @cur_transfer: Pointer to current spi_transfer | |
343 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | |
344 | * @tx: current position in TX buffer to be read | |
345 | * @tx_end: end position in TX buffer to be read | |
346 | * @rx: current position in RX buffer to be written | |
347 | * @rx_end: end position in RX buffer to be written | |
12e8b325 LW |
348 | * @read: the type of read currently going on |
349 | * @write: the type of write currently going on | |
350 | * @exp_fifo_level: expected FIFO level | |
351 | * @dma_rx_channel: optional channel for RX DMA | |
352 | * @dma_tx_channel: optional channel for TX DMA | |
353 | * @sgt_rx: scattertable for the RX transfer | |
354 | * @sgt_tx: scattertable for the TX transfer | |
355 | * @dummypage: a dummy page used for driving data on the bus with DMA | |
b43d65f7 LW |
356 | */ |
357 | struct pl022 { | |
358 | struct amba_device *adev; | |
359 | struct vendor_data *vendor; | |
360 | resource_size_t phybase; | |
361 | void __iomem *virtbase; | |
362 | struct clk *clk; | |
363 | struct spi_master *master; | |
364 | struct pl022_ssp_controller *master_info; | |
365 | /* Driver message queue */ | |
366 | struct workqueue_struct *workqueue; | |
367 | struct work_struct pump_messages; | |
368 | spinlock_t queue_lock; | |
369 | struct list_head queue; | |
dec5a581 | 370 | bool busy; |
5e8b821d | 371 | bool running; |
b43d65f7 LW |
372 | /* Message transfer pump */ |
373 | struct tasklet_struct pump_transfers; | |
374 | struct spi_message *cur_msg; | |
375 | struct spi_transfer *cur_transfer; | |
376 | struct chip_data *cur_chip; | |
377 | void *tx; | |
378 | void *tx_end; | |
379 | void *rx; | |
380 | void *rx_end; | |
381 | enum ssp_reading read; | |
382 | enum ssp_writing write; | |
fc05475f | 383 | u32 exp_fifo_level; |
083be3f0 LW |
384 | enum ssp_rx_level_trig rx_lev_trig; |
385 | enum ssp_tx_level_trig tx_lev_trig; | |
b1b6b9aa LW |
386 | /* DMA settings */ |
387 | #ifdef CONFIG_DMA_ENGINE | |
388 | struct dma_chan *dma_rx_channel; | |
389 | struct dma_chan *dma_tx_channel; | |
390 | struct sg_table sgt_rx; | |
391 | struct sg_table sgt_tx; | |
392 | char *dummypage; | |
393 | #endif | |
b43d65f7 LW |
394 | }; |
395 | ||
396 | /** | |
397 | * struct chip_data - To maintain runtime state of SSP for each client chip | |
556f4aeb LW |
398 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
399 | * register is 32 bits wide rather than just 16 | |
b43d65f7 LW |
400 | * @cr1: Value of control register CR1 of SSP |
401 | * @dmacr: Value of DMA control Register of SSP | |
402 | * @cpsr: Value of Clock prescale register | |
403 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client | |
404 | * @enable_dma: Whether to enable DMA or not | |
b43d65f7 | 405 | * @read: function ptr to be used to read when doing xfer for this chip |
12e8b325 | 406 | * @write: function ptr to be used to write when doing xfer for this chip |
b43d65f7 LW |
407 | * @cs_control: chip select callback provided by chip |
408 | * @xfer_type: polling/interrupt/DMA | |
409 | * | |
410 | * Runtime state of the SSP controller, maintained per chip, | |
411 | * This would be set according to the current message that would be served | |
412 | */ | |
413 | struct chip_data { | |
556f4aeb | 414 | u32 cr0; |
b43d65f7 LW |
415 | u16 cr1; |
416 | u16 dmacr; | |
417 | u16 cpsr; | |
418 | u8 n_bytes; | |
b1b6b9aa | 419 | bool enable_dma; |
b43d65f7 LW |
420 | enum ssp_reading read; |
421 | enum ssp_writing write; | |
422 | void (*cs_control) (u32 command); | |
423 | int xfer_type; | |
424 | }; | |
425 | ||
426 | /** | |
427 | * null_cs_control - Dummy chip select function | |
428 | * @command: select/delect the chip | |
429 | * | |
430 | * If no chip select function is provided by client this is used as dummy | |
431 | * chip select | |
432 | */ | |
433 | static void null_cs_control(u32 command) | |
434 | { | |
435 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | |
436 | } | |
437 | ||
438 | /** | |
439 | * giveback - current spi_message is over, schedule next message and call | |
440 | * callback of this message. Assumes that caller already | |
441 | * set message->status; dma and pio irqs are blocked | |
442 | * @pl022: SSP driver private data structure | |
443 | */ | |
444 | static void giveback(struct pl022 *pl022) | |
445 | { | |
446 | struct spi_transfer *last_transfer; | |
447 | unsigned long flags; | |
448 | struct spi_message *msg; | |
449 | void (*curr_cs_control) (u32 command); | |
450 | ||
451 | /* | |
452 | * This local reference to the chip select function | |
453 | * is needed because we set curr_chip to NULL | |
454 | * as a step toward termininating the message. | |
455 | */ | |
456 | curr_cs_control = pl022->cur_chip->cs_control; | |
457 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
458 | msg = pl022->cur_msg; | |
459 | pl022->cur_msg = NULL; | |
460 | pl022->cur_transfer = NULL; | |
461 | pl022->cur_chip = NULL; | |
462 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
463 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
464 | ||
465 | last_transfer = list_entry(msg->transfers.prev, | |
466 | struct spi_transfer, | |
467 | transfer_list); | |
468 | ||
469 | /* Delay if requested before any change in chip select */ | |
470 | if (last_transfer->delay_usecs) | |
471 | /* | |
472 | * FIXME: This runs in interrupt context. | |
473 | * Is this really smart? | |
474 | */ | |
475 | udelay(last_transfer->delay_usecs); | |
476 | ||
477 | /* | |
478 | * Drop chip select UNLESS cs_change is true or we are returning | |
479 | * a message with an error, or next message is for another chip | |
480 | */ | |
481 | if (!last_transfer->cs_change) | |
482 | curr_cs_control(SSP_CHIP_DESELECT); | |
483 | else { | |
484 | struct spi_message *next_msg; | |
485 | ||
486 | /* Holding of cs was hinted, but we need to make sure | |
487 | * the next message is for the same chip. Don't waste | |
488 | * time with the following tests unless this was hinted. | |
489 | * | |
490 | * We cannot postpone this until pump_messages, because | |
491 | * after calling msg->complete (below) the driver that | |
492 | * sent the current message could be unloaded, which | |
493 | * could invalidate the cs_control() callback... | |
494 | */ | |
495 | ||
496 | /* get a pointer to the next message, if any */ | |
497 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
498 | if (list_empty(&pl022->queue)) | |
499 | next_msg = NULL; | |
500 | else | |
501 | next_msg = list_entry(pl022->queue.next, | |
502 | struct spi_message, queue); | |
503 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
504 | ||
505 | /* see if the next and current messages point | |
506 | * to the same chip | |
507 | */ | |
508 | if (next_msg && next_msg->spi != msg->spi) | |
509 | next_msg = NULL; | |
510 | if (!next_msg || msg->state == STATE_ERROR) | |
511 | curr_cs_control(SSP_CHIP_DESELECT); | |
512 | } | |
513 | msg->state = NULL; | |
514 | if (msg->complete) | |
515 | msg->complete(msg->context); | |
808f1037 | 516 | /* This message is completed, so let's turn off the clocks & power */ |
b43d65f7 | 517 | clk_disable(pl022->clk); |
545074fb | 518 | amba_pclk_disable(pl022->adev); |
808f1037 | 519 | amba_vcore_disable(pl022->adev); |
b43d65f7 LW |
520 | } |
521 | ||
522 | /** | |
523 | * flush - flush the FIFO to reach a clean state | |
524 | * @pl022: SSP driver private data structure | |
525 | */ | |
526 | static int flush(struct pl022 *pl022) | |
527 | { | |
528 | unsigned long limit = loops_per_jiffy << 1; | |
529 | ||
530 | dev_dbg(&pl022->adev->dev, "flush\n"); | |
531 | do { | |
532 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
533 | readw(SSP_DR(pl022->virtbase)); | |
534 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | |
fc05475f LW |
535 | |
536 | pl022->exp_fifo_level = 0; | |
537 | ||
b43d65f7 LW |
538 | return limit; |
539 | } | |
540 | ||
541 | /** | |
542 | * restore_state - Load configuration of current chip | |
543 | * @pl022: SSP driver private data structure | |
544 | */ | |
545 | static void restore_state(struct pl022 *pl022) | |
546 | { | |
547 | struct chip_data *chip = pl022->cur_chip; | |
548 | ||
556f4aeb LW |
549 | if (pl022->vendor->extended_cr) |
550 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); | |
551 | else | |
552 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); | |
b43d65f7 LW |
553 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
554 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); | |
555 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); | |
556 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
557 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
558 | } | |
559 | ||
b43d65f7 LW |
560 | /* |
561 | * Default SSP Register Values | |
562 | */ | |
563 | #define DEFAULT_SSP_REG_CR0 ( \ | |
564 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | |
556f4aeb LW |
565 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
566 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
567 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
568 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
569 | ) | |
570 | ||
571 | /* ST versions have slightly different bit layout */ | |
572 | #define DEFAULT_SSP_REG_CR0_ST ( \ | |
573 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
574 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ | |
b43d65f7 | 575 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
ee2b805c | 576 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
556f4aeb LW |
577 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
578 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ | |
579 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ | |
b43d65f7 LW |
580 | ) |
581 | ||
781c7b12 LW |
582 | /* The PL023 version is slightly different again */ |
583 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ | |
584 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
585 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
586 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
587 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
588 | ) | |
589 | ||
b43d65f7 LW |
590 | #define DEFAULT_SSP_REG_CR1 ( \ |
591 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ | |
592 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
593 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
556f4aeb | 594 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
b43d65f7 LW |
595 | ) |
596 | ||
556f4aeb LW |
597 | /* ST versions extend this register to use all 16 bits */ |
598 | #define DEFAULT_SSP_REG_CR1_ST ( \ | |
599 | DEFAULT_SSP_REG_CR1 | \ | |
600 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
601 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
602 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ | |
603 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
604 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ | |
605 | ) | |
606 | ||
781c7b12 LW |
607 | /* |
608 | * The PL023 variant has further differences: no loopback mode, no microwire | |
609 | * support, and a new clock feedback delay setting. | |
610 | */ | |
611 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ | |
612 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
613 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
614 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ | |
615 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
616 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
617 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
618 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ | |
619 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ | |
620 | ) | |
556f4aeb | 621 | |
b43d65f7 | 622 | #define DEFAULT_SSP_REG_CPSR ( \ |
556f4aeb | 623 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
b43d65f7 LW |
624 | ) |
625 | ||
626 | #define DEFAULT_SSP_REG_DMACR (\ | |
627 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ | |
628 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ | |
629 | ) | |
630 | ||
781c7b12 LW |
631 | /** |
632 | * load_ssp_default_config - Load default configuration for SSP | |
633 | * @pl022: SSP driver private data structure | |
634 | */ | |
b43d65f7 LW |
635 | static void load_ssp_default_config(struct pl022 *pl022) |
636 | { | |
781c7b12 LW |
637 | if (pl022->vendor->pl023) { |
638 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); | |
639 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); | |
640 | } else if (pl022->vendor->extended_cr) { | |
556f4aeb LW |
641 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
642 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); | |
643 | } else { | |
644 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); | |
645 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); | |
646 | } | |
b43d65f7 LW |
647 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
648 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); | |
649 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
650 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
651 | } | |
652 | ||
653 | /** | |
654 | * This will write to TX and read from RX according to the parameters | |
655 | * set in pl022. | |
656 | */ | |
657 | static void readwriter(struct pl022 *pl022) | |
658 | { | |
659 | ||
660 | /* | |
25985edc | 661 | * The FIFO depth is different between primecell variants. |
b43d65f7 LW |
662 | * I believe filling in too much in the FIFO might cause |
663 | * errons in 8bit wide transfers on ARM variants (just 8 words | |
664 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | |
665 | * | |
fc05475f LW |
666 | * To prevent this issue, the TX FIFO is only filled to the |
667 | * unused RX FIFO fill length, regardless of what the TX | |
668 | * FIFO status flag indicates. | |
b43d65f7 LW |
669 | */ |
670 | dev_dbg(&pl022->adev->dev, | |
671 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | |
672 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); | |
673 | ||
674 | /* Read as much as you can */ | |
675 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
676 | && (pl022->rx < pl022->rx_end)) { | |
677 | switch (pl022->read) { | |
678 | case READING_NULL: | |
679 | readw(SSP_DR(pl022->virtbase)); | |
680 | break; | |
681 | case READING_U8: | |
682 | *(u8 *) (pl022->rx) = | |
683 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
684 | break; | |
685 | case READING_U16: | |
686 | *(u16 *) (pl022->rx) = | |
687 | (u16) readw(SSP_DR(pl022->virtbase)); | |
688 | break; | |
689 | case READING_U32: | |
690 | *(u32 *) (pl022->rx) = | |
691 | readl(SSP_DR(pl022->virtbase)); | |
692 | break; | |
693 | } | |
694 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 695 | pl022->exp_fifo_level--; |
b43d65f7 LW |
696 | } |
697 | /* | |
fc05475f | 698 | * Write as much as possible up to the RX FIFO size |
b43d65f7 | 699 | */ |
fc05475f | 700 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
b43d65f7 LW |
701 | && (pl022->tx < pl022->tx_end)) { |
702 | switch (pl022->write) { | |
703 | case WRITING_NULL: | |
704 | writew(0x0, SSP_DR(pl022->virtbase)); | |
705 | break; | |
706 | case WRITING_U8: | |
707 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
708 | break; | |
709 | case WRITING_U16: | |
710 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); | |
711 | break; | |
712 | case WRITING_U32: | |
713 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
714 | break; | |
715 | } | |
716 | pl022->tx += (pl022->cur_chip->n_bytes); | |
fc05475f | 717 | pl022->exp_fifo_level++; |
b43d65f7 LW |
718 | /* |
719 | * This inner reader takes care of things appearing in the RX | |
720 | * FIFO as we're transmitting. This will happen a lot since the | |
721 | * clock starts running when you put things into the TX FIFO, | |
25985edc | 722 | * and then things are continuously clocked into the RX FIFO. |
b43d65f7 LW |
723 | */ |
724 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
725 | && (pl022->rx < pl022->rx_end)) { | |
726 | switch (pl022->read) { | |
727 | case READING_NULL: | |
728 | readw(SSP_DR(pl022->virtbase)); | |
729 | break; | |
730 | case READING_U8: | |
731 | *(u8 *) (pl022->rx) = | |
732 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
733 | break; | |
734 | case READING_U16: | |
735 | *(u16 *) (pl022->rx) = | |
736 | (u16) readw(SSP_DR(pl022->virtbase)); | |
737 | break; | |
738 | case READING_U32: | |
739 | *(u32 *) (pl022->rx) = | |
740 | readl(SSP_DR(pl022->virtbase)); | |
741 | break; | |
742 | } | |
743 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 744 | pl022->exp_fifo_level--; |
b43d65f7 LW |
745 | } |
746 | } | |
747 | /* | |
748 | * When we exit here the TX FIFO should be full and the RX FIFO | |
749 | * should be empty | |
750 | */ | |
751 | } | |
752 | ||
753 | ||
754 | /** | |
755 | * next_transfer - Move to the Next transfer in the current spi message | |
756 | * @pl022: SSP driver private data structure | |
757 | * | |
758 | * This function moves though the linked list of spi transfers in the | |
759 | * current spi message and returns with the state of current spi | |
760 | * message i.e whether its last transfer is done(STATE_DONE) or | |
761 | * Next transfer is ready(STATE_RUNNING) | |
762 | */ | |
763 | static void *next_transfer(struct pl022 *pl022) | |
764 | { | |
765 | struct spi_message *msg = pl022->cur_msg; | |
766 | struct spi_transfer *trans = pl022->cur_transfer; | |
767 | ||
768 | /* Move to next transfer */ | |
769 | if (trans->transfer_list.next != &msg->transfers) { | |
770 | pl022->cur_transfer = | |
771 | list_entry(trans->transfer_list.next, | |
772 | struct spi_transfer, transfer_list); | |
773 | return STATE_RUNNING; | |
774 | } | |
775 | return STATE_DONE; | |
776 | } | |
b1b6b9aa LW |
777 | |
778 | /* | |
779 | * This DMA functionality is only compiled in if we have | |
780 | * access to the generic DMA devices/DMA engine. | |
781 | */ | |
782 | #ifdef CONFIG_DMA_ENGINE | |
783 | static void unmap_free_dma_scatter(struct pl022 *pl022) | |
784 | { | |
785 | /* Unmap and free the SG tables */ | |
b7298896 | 786 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 787 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
b7298896 | 788 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
789 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
790 | sg_free_table(&pl022->sgt_rx); | |
791 | sg_free_table(&pl022->sgt_tx); | |
792 | } | |
793 | ||
794 | static void dma_callback(void *data) | |
795 | { | |
796 | struct pl022 *pl022 = data; | |
797 | struct spi_message *msg = pl022->cur_msg; | |
798 | ||
799 | BUG_ON(!pl022->sgt_rx.sgl); | |
800 | ||
801 | #ifdef VERBOSE_DEBUG | |
802 | /* | |
803 | * Optionally dump out buffers to inspect contents, this is | |
804 | * good if you want to convince yourself that the loopback | |
805 | * read/write contents are the same, when adopting to a new | |
806 | * DMA engine. | |
807 | */ | |
808 | { | |
809 | struct scatterlist *sg; | |
810 | unsigned int i; | |
811 | ||
812 | dma_sync_sg_for_cpu(&pl022->adev->dev, | |
813 | pl022->sgt_rx.sgl, | |
814 | pl022->sgt_rx.nents, | |
815 | DMA_FROM_DEVICE); | |
816 | ||
817 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { | |
818 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); | |
819 | print_hex_dump(KERN_ERR, "SPI RX: ", | |
820 | DUMP_PREFIX_OFFSET, | |
821 | 16, | |
822 | 1, | |
823 | sg_virt(sg), | |
824 | sg_dma_len(sg), | |
825 | 1); | |
826 | } | |
827 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { | |
828 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); | |
829 | print_hex_dump(KERN_ERR, "SPI TX: ", | |
830 | DUMP_PREFIX_OFFSET, | |
831 | 16, | |
832 | 1, | |
833 | sg_virt(sg), | |
834 | sg_dma_len(sg), | |
835 | 1); | |
836 | } | |
837 | } | |
838 | #endif | |
839 | ||
840 | unmap_free_dma_scatter(pl022); | |
841 | ||
25985edc | 842 | /* Update total bytes transferred */ |
b1b6b9aa LW |
843 | msg->actual_length += pl022->cur_transfer->len; |
844 | if (pl022->cur_transfer->cs_change) | |
845 | pl022->cur_chip-> | |
846 | cs_control(SSP_CHIP_DESELECT); | |
847 | ||
848 | /* Move to next transfer */ | |
849 | msg->state = next_transfer(pl022); | |
850 | tasklet_schedule(&pl022->pump_transfers); | |
851 | } | |
852 | ||
853 | static void setup_dma_scatter(struct pl022 *pl022, | |
854 | void *buffer, | |
855 | unsigned int length, | |
856 | struct sg_table *sgtab) | |
857 | { | |
858 | struct scatterlist *sg; | |
859 | int bytesleft = length; | |
860 | void *bufp = buffer; | |
861 | int mapbytes; | |
862 | int i; | |
863 | ||
864 | if (buffer) { | |
865 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
866 | /* | |
867 | * If there are less bytes left than what fits | |
868 | * in the current page (plus page alignment offset) | |
869 | * we just feed in this, else we stuff in as much | |
870 | * as we can. | |
871 | */ | |
872 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) | |
873 | mapbytes = bytesleft; | |
874 | else | |
875 | mapbytes = PAGE_SIZE - offset_in_page(bufp); | |
876 | sg_set_page(sg, virt_to_page(bufp), | |
877 | mapbytes, offset_in_page(bufp)); | |
878 | bufp += mapbytes; | |
879 | bytesleft -= mapbytes; | |
880 | dev_dbg(&pl022->adev->dev, | |
881 | "set RX/TX target page @ %p, %d bytes, %d left\n", | |
882 | bufp, mapbytes, bytesleft); | |
883 | } | |
884 | } else { | |
885 | /* Map the dummy buffer on every page */ | |
886 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
887 | if (bytesleft < PAGE_SIZE) | |
888 | mapbytes = bytesleft; | |
889 | else | |
890 | mapbytes = PAGE_SIZE; | |
891 | sg_set_page(sg, virt_to_page(pl022->dummypage), | |
892 | mapbytes, 0); | |
893 | bytesleft -= mapbytes; | |
894 | dev_dbg(&pl022->adev->dev, | |
895 | "set RX/TX to dummy page %d bytes, %d left\n", | |
896 | mapbytes, bytesleft); | |
897 | ||
898 | } | |
899 | } | |
900 | BUG_ON(bytesleft); | |
901 | } | |
902 | ||
903 | /** | |
904 | * configure_dma - configures the channels for the next transfer | |
905 | * @pl022: SSP driver's private data structure | |
906 | */ | |
907 | static int configure_dma(struct pl022 *pl022) | |
908 | { | |
909 | struct dma_slave_config rx_conf = { | |
910 | .src_addr = SSP_DR(pl022->phybase), | |
911 | .direction = DMA_FROM_DEVICE, | |
b1b6b9aa LW |
912 | }; |
913 | struct dma_slave_config tx_conf = { | |
914 | .dst_addr = SSP_DR(pl022->phybase), | |
915 | .direction = DMA_TO_DEVICE, | |
b1b6b9aa LW |
916 | }; |
917 | unsigned int pages; | |
918 | int ret; | |
082086f2 | 919 | int rx_sglen, tx_sglen; |
b1b6b9aa LW |
920 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
921 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
922 | struct dma_async_tx_descriptor *rxdesc; | |
923 | struct dma_async_tx_descriptor *txdesc; | |
b1b6b9aa LW |
924 | |
925 | /* Check that the channels are available */ | |
926 | if (!rxchan || !txchan) | |
927 | return -ENODEV; | |
928 | ||
083be3f0 LW |
929 | /* |
930 | * If supplied, the DMA burstsize should equal the FIFO trigger level. | |
931 | * Notice that the DMA engine uses one-to-one mapping. Since we can | |
932 | * not trigger on 2 elements this needs explicit mapping rather than | |
933 | * calculation. | |
934 | */ | |
935 | switch (pl022->rx_lev_trig) { | |
936 | case SSP_RX_1_OR_MORE_ELEM: | |
937 | rx_conf.src_maxburst = 1; | |
938 | break; | |
939 | case SSP_RX_4_OR_MORE_ELEM: | |
940 | rx_conf.src_maxburst = 4; | |
941 | break; | |
942 | case SSP_RX_8_OR_MORE_ELEM: | |
943 | rx_conf.src_maxburst = 8; | |
944 | break; | |
945 | case SSP_RX_16_OR_MORE_ELEM: | |
946 | rx_conf.src_maxburst = 16; | |
947 | break; | |
948 | case SSP_RX_32_OR_MORE_ELEM: | |
949 | rx_conf.src_maxburst = 32; | |
950 | break; | |
951 | default: | |
952 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; | |
953 | break; | |
954 | } | |
955 | ||
956 | switch (pl022->tx_lev_trig) { | |
957 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
958 | tx_conf.dst_maxburst = 1; | |
959 | break; | |
960 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
961 | tx_conf.dst_maxburst = 4; | |
962 | break; | |
963 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
964 | tx_conf.dst_maxburst = 8; | |
965 | break; | |
966 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
967 | tx_conf.dst_maxburst = 16; | |
968 | break; | |
969 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
970 | tx_conf.dst_maxburst = 32; | |
971 | break; | |
972 | default: | |
973 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; | |
974 | break; | |
975 | } | |
976 | ||
b1b6b9aa LW |
977 | switch (pl022->read) { |
978 | case READING_NULL: | |
979 | /* Use the same as for writing */ | |
980 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
981 | break; | |
982 | case READING_U8: | |
983 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
984 | break; | |
985 | case READING_U16: | |
986 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
987 | break; | |
988 | case READING_U32: | |
989 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
990 | break; | |
991 | } | |
992 | ||
993 | switch (pl022->write) { | |
994 | case WRITING_NULL: | |
995 | /* Use the same as for reading */ | |
996 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
997 | break; | |
998 | case WRITING_U8: | |
999 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1000 | break; | |
1001 | case WRITING_U16: | |
1002 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1003 | break; | |
1004 | case WRITING_U32: | |
bc3f67a3 | 1005 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
b1b6b9aa LW |
1006 | break; |
1007 | } | |
1008 | ||
1009 | /* SPI pecularity: we need to read and write the same width */ | |
1010 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1011 | rx_conf.src_addr_width = tx_conf.dst_addr_width; | |
1012 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1013 | tx_conf.dst_addr_width = rx_conf.src_addr_width; | |
1014 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); | |
1015 | ||
ecd442fd LW |
1016 | dmaengine_slave_config(rxchan, &rx_conf); |
1017 | dmaengine_slave_config(txchan, &tx_conf); | |
b1b6b9aa LW |
1018 | |
1019 | /* Create sglists for the transfers */ | |
1020 | pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; | |
1021 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); | |
1022 | ||
1023 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); | |
1024 | if (ret) | |
1025 | goto err_alloc_rx_sg; | |
1026 | ||
1027 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); | |
1028 | if (ret) | |
1029 | goto err_alloc_tx_sg; | |
1030 | ||
1031 | /* Fill in the scatterlists for the RX+TX buffers */ | |
1032 | setup_dma_scatter(pl022, pl022->rx, | |
1033 | pl022->cur_transfer->len, &pl022->sgt_rx); | |
1034 | setup_dma_scatter(pl022, pl022->tx, | |
1035 | pl022->cur_transfer->len, &pl022->sgt_tx); | |
1036 | ||
1037 | /* Map DMA buffers */ | |
082086f2 | 1038 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa | 1039 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
082086f2 | 1040 | if (!rx_sglen) |
b1b6b9aa LW |
1041 | goto err_rx_sgmap; |
1042 | ||
082086f2 | 1043 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 1044 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
082086f2 | 1045 | if (!tx_sglen) |
b1b6b9aa LW |
1046 | goto err_tx_sgmap; |
1047 | ||
1048 | /* Send both scatterlists */ | |
1049 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, | |
1050 | pl022->sgt_rx.sgl, | |
082086f2 | 1051 | rx_sglen, |
b1b6b9aa LW |
1052 | DMA_FROM_DEVICE, |
1053 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1054 | if (!rxdesc) | |
1055 | goto err_rxdesc; | |
1056 | ||
1057 | txdesc = txchan->device->device_prep_slave_sg(txchan, | |
1058 | pl022->sgt_tx.sgl, | |
082086f2 | 1059 | tx_sglen, |
b1b6b9aa LW |
1060 | DMA_TO_DEVICE, |
1061 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1062 | if (!txdesc) | |
1063 | goto err_txdesc; | |
1064 | ||
1065 | /* Put the callback on the RX transfer only, that should finish last */ | |
1066 | rxdesc->callback = dma_callback; | |
1067 | rxdesc->callback_param = pl022; | |
1068 | ||
1069 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
ecd442fd LW |
1070 | dmaengine_submit(rxdesc); |
1071 | dmaengine_submit(txdesc); | |
1072 | dma_async_issue_pending(rxchan); | |
1073 | dma_async_issue_pending(txchan); | |
b1b6b9aa LW |
1074 | |
1075 | return 0; | |
1076 | ||
b1b6b9aa | 1077 | err_txdesc: |
ecd442fd | 1078 | dmaengine_terminate_all(txchan); |
b1b6b9aa | 1079 | err_rxdesc: |
ecd442fd | 1080 | dmaengine_terminate_all(rxchan); |
b7298896 | 1081 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa LW |
1082 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1083 | err_tx_sgmap: | |
b7298896 | 1084 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
1085 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
1086 | err_rx_sgmap: | |
1087 | sg_free_table(&pl022->sgt_tx); | |
1088 | err_alloc_tx_sg: | |
1089 | sg_free_table(&pl022->sgt_rx); | |
1090 | err_alloc_rx_sg: | |
1091 | return -ENOMEM; | |
1092 | } | |
1093 | ||
1094 | static int __init pl022_dma_probe(struct pl022 *pl022) | |
1095 | { | |
1096 | dma_cap_mask_t mask; | |
1097 | ||
1098 | /* Try to acquire a generic DMA engine slave channel */ | |
1099 | dma_cap_zero(mask); | |
1100 | dma_cap_set(DMA_SLAVE, mask); | |
1101 | /* | |
1102 | * We need both RX and TX channels to do DMA, else do none | |
1103 | * of them. | |
1104 | */ | |
1105 | pl022->dma_rx_channel = dma_request_channel(mask, | |
1106 | pl022->master_info->dma_filter, | |
1107 | pl022->master_info->dma_rx_param); | |
1108 | if (!pl022->dma_rx_channel) { | |
43c64015 | 1109 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); |
b1b6b9aa LW |
1110 | goto err_no_rxchan; |
1111 | } | |
1112 | ||
1113 | pl022->dma_tx_channel = dma_request_channel(mask, | |
1114 | pl022->master_info->dma_filter, | |
1115 | pl022->master_info->dma_tx_param); | |
1116 | if (!pl022->dma_tx_channel) { | |
43c64015 | 1117 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); |
b1b6b9aa LW |
1118 | goto err_no_txchan; |
1119 | } | |
1120 | ||
1121 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
1122 | if (!pl022->dummypage) { | |
43c64015 | 1123 | dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); |
b1b6b9aa LW |
1124 | goto err_no_dummypage; |
1125 | } | |
1126 | ||
1127 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", | |
1128 | dma_chan_name(pl022->dma_rx_channel), | |
1129 | dma_chan_name(pl022->dma_tx_channel)); | |
1130 | ||
1131 | return 0; | |
1132 | ||
1133 | err_no_dummypage: | |
1134 | dma_release_channel(pl022->dma_tx_channel); | |
1135 | err_no_txchan: | |
1136 | dma_release_channel(pl022->dma_rx_channel); | |
1137 | pl022->dma_rx_channel = NULL; | |
1138 | err_no_rxchan: | |
43c64015 VK |
1139 | dev_err(&pl022->adev->dev, |
1140 | "Failed to work in dma mode, work without dma!\n"); | |
b1b6b9aa LW |
1141 | return -ENODEV; |
1142 | } | |
1143 | ||
1144 | static void terminate_dma(struct pl022 *pl022) | |
1145 | { | |
1146 | struct dma_chan *rxchan = pl022->dma_rx_channel; | |
1147 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
1148 | ||
ecd442fd LW |
1149 | dmaengine_terminate_all(rxchan); |
1150 | dmaengine_terminate_all(txchan); | |
b1b6b9aa LW |
1151 | unmap_free_dma_scatter(pl022); |
1152 | } | |
1153 | ||
1154 | static void pl022_dma_remove(struct pl022 *pl022) | |
1155 | { | |
1156 | if (pl022->busy) | |
1157 | terminate_dma(pl022); | |
1158 | if (pl022->dma_tx_channel) | |
1159 | dma_release_channel(pl022->dma_tx_channel); | |
1160 | if (pl022->dma_rx_channel) | |
1161 | dma_release_channel(pl022->dma_rx_channel); | |
1162 | kfree(pl022->dummypage); | |
1163 | } | |
1164 | ||
1165 | #else | |
1166 | static inline int configure_dma(struct pl022 *pl022) | |
1167 | { | |
1168 | return -ENODEV; | |
1169 | } | |
1170 | ||
1171 | static inline int pl022_dma_probe(struct pl022 *pl022) | |
1172 | { | |
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | static inline void pl022_dma_remove(struct pl022 *pl022) | |
1177 | { | |
1178 | } | |
1179 | #endif | |
1180 | ||
b43d65f7 LW |
1181 | /** |
1182 | * pl022_interrupt_handler - Interrupt handler for SSP controller | |
1183 | * | |
1184 | * This function handles interrupts generated for an interrupt based transfer. | |
1185 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the | |
1186 | * current message's state as STATE_ERROR and schedule the tasklet | |
1187 | * pump_transfers which will do the postprocessing of the current message by | |
1188 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no | |
1189 | * more data, and writes data in TX FIFO till it is not full. If we complete | |
1190 | * the transfer we move to the next transfer and schedule the tasklet. | |
1191 | */ | |
1192 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |
1193 | { | |
1194 | struct pl022 *pl022 = dev_id; | |
1195 | struct spi_message *msg = pl022->cur_msg; | |
1196 | u16 irq_status = 0; | |
1197 | u16 flag = 0; | |
1198 | ||
1199 | if (unlikely(!msg)) { | |
1200 | dev_err(&pl022->adev->dev, | |
1201 | "bad message state in interrupt handler"); | |
1202 | /* Never fail */ | |
1203 | return IRQ_HANDLED; | |
1204 | } | |
1205 | ||
1206 | /* Read the Interrupt Status Register */ | |
1207 | irq_status = readw(SSP_MIS(pl022->virtbase)); | |
1208 | ||
1209 | if (unlikely(!irq_status)) | |
1210 | return IRQ_NONE; | |
1211 | ||
b1b6b9aa LW |
1212 | /* |
1213 | * This handles the FIFO interrupts, the timeout | |
1214 | * interrupts are flatly ignored, they cannot be | |
1215 | * trusted. | |
1216 | */ | |
b43d65f7 LW |
1217 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1218 | /* | |
1219 | * Overrun interrupt - bail out since our Data has been | |
1220 | * corrupted | |
1221 | */ | |
b1b6b9aa | 1222 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
b43d65f7 LW |
1223 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1224 | dev_err(&pl022->adev->dev, | |
1225 | "RXFIFO is full\n"); | |
1226 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | |
1227 | dev_err(&pl022->adev->dev, | |
1228 | "TXFIFO is full\n"); | |
1229 | ||
1230 | /* | |
1231 | * Disable and clear interrupts, disable SSP, | |
1232 | * mark message with bad status so it can be | |
1233 | * retried. | |
1234 | */ | |
1235 | writew(DISABLE_ALL_INTERRUPTS, | |
1236 | SSP_IMSC(pl022->virtbase)); | |
1237 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1238 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1239 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
1240 | msg->state = STATE_ERROR; | |
1241 | ||
1242 | /* Schedule message queue handler */ | |
1243 | tasklet_schedule(&pl022->pump_transfers); | |
1244 | return IRQ_HANDLED; | |
1245 | } | |
1246 | ||
1247 | readwriter(pl022); | |
1248 | ||
1249 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { | |
1250 | flag = 1; | |
1251 | /* Disable Transmit interrupt */ | |
1252 | writew(readw(SSP_IMSC(pl022->virtbase)) & | |
1253 | (~SSP_IMSC_MASK_TXIM), | |
1254 | SSP_IMSC(pl022->virtbase)); | |
1255 | } | |
1256 | ||
1257 | /* | |
1258 | * Since all transactions must write as much as shall be read, | |
1259 | * we can conclude the entire transaction once RX is complete. | |
1260 | * At this point, all TX will always be finished. | |
1261 | */ | |
1262 | if (pl022->rx >= pl022->rx_end) { | |
1263 | writew(DISABLE_ALL_INTERRUPTS, | |
1264 | SSP_IMSC(pl022->virtbase)); | |
1265 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1266 | if (unlikely(pl022->rx > pl022->rx_end)) { | |
1267 | dev_warn(&pl022->adev->dev, "read %u surplus " | |
1268 | "bytes (did you request an odd " | |
1269 | "number of bytes on a 16bit bus?)\n", | |
1270 | (u32) (pl022->rx - pl022->rx_end)); | |
1271 | } | |
25985edc | 1272 | /* Update total bytes transferred */ |
b43d65f7 LW |
1273 | msg->actual_length += pl022->cur_transfer->len; |
1274 | if (pl022->cur_transfer->cs_change) | |
1275 | pl022->cur_chip-> | |
1276 | cs_control(SSP_CHIP_DESELECT); | |
1277 | /* Move to next transfer */ | |
1278 | msg->state = next_transfer(pl022); | |
1279 | tasklet_schedule(&pl022->pump_transfers); | |
1280 | return IRQ_HANDLED; | |
1281 | } | |
1282 | ||
1283 | return IRQ_HANDLED; | |
1284 | } | |
1285 | ||
1286 | /** | |
1287 | * This sets up the pointers to memory for the next message to | |
1288 | * send out on the SPI bus. | |
1289 | */ | |
1290 | static int set_up_next_transfer(struct pl022 *pl022, | |
1291 | struct spi_transfer *transfer) | |
1292 | { | |
1293 | int residue; | |
1294 | ||
1295 | /* Sanity check the message for this bus width */ | |
1296 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; | |
1297 | if (unlikely(residue != 0)) { | |
1298 | dev_err(&pl022->adev->dev, | |
1299 | "message of %u bytes to transmit but the current " | |
1300 | "chip bus has a data width of %u bytes!\n", | |
1301 | pl022->cur_transfer->len, | |
1302 | pl022->cur_chip->n_bytes); | |
1303 | dev_err(&pl022->adev->dev, "skipping this message\n"); | |
1304 | return -EIO; | |
1305 | } | |
1306 | pl022->tx = (void *)transfer->tx_buf; | |
1307 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; | |
1308 | pl022->rx = (void *)transfer->rx_buf; | |
1309 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; | |
1310 | pl022->write = | |
1311 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; | |
1312 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | /** | |
b1b6b9aa LW |
1317 | * pump_transfers - Tasklet function which schedules next transfer |
1318 | * when running in interrupt or DMA transfer mode. | |
b43d65f7 LW |
1319 | * @data: SSP driver private data structure |
1320 | * | |
1321 | */ | |
1322 | static void pump_transfers(unsigned long data) | |
1323 | { | |
1324 | struct pl022 *pl022 = (struct pl022 *) data; | |
1325 | struct spi_message *message = NULL; | |
1326 | struct spi_transfer *transfer = NULL; | |
1327 | struct spi_transfer *previous = NULL; | |
1328 | ||
1329 | /* Get current state information */ | |
1330 | message = pl022->cur_msg; | |
1331 | transfer = pl022->cur_transfer; | |
1332 | ||
1333 | /* Handle for abort */ | |
1334 | if (message->state == STATE_ERROR) { | |
1335 | message->status = -EIO; | |
1336 | giveback(pl022); | |
1337 | return; | |
1338 | } | |
1339 | ||
1340 | /* Handle end of message */ | |
1341 | if (message->state == STATE_DONE) { | |
1342 | message->status = 0; | |
1343 | giveback(pl022); | |
1344 | return; | |
1345 | } | |
1346 | ||
1347 | /* Delay if requested at end of transfer before CS change */ | |
1348 | if (message->state == STATE_RUNNING) { | |
1349 | previous = list_entry(transfer->transfer_list.prev, | |
1350 | struct spi_transfer, | |
1351 | transfer_list); | |
1352 | if (previous->delay_usecs) | |
1353 | /* | |
1354 | * FIXME: This runs in interrupt context. | |
1355 | * Is this really smart? | |
1356 | */ | |
1357 | udelay(previous->delay_usecs); | |
1358 | ||
1359 | /* Drop chip select only if cs_change is requested */ | |
1360 | if (previous->cs_change) | |
1361 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1362 | } else { | |
1363 | /* STATE_START */ | |
1364 | message->state = STATE_RUNNING; | |
1365 | } | |
1366 | ||
1367 | if (set_up_next_transfer(pl022, transfer)) { | |
1368 | message->state = STATE_ERROR; | |
1369 | message->status = -EIO; | |
1370 | giveback(pl022); | |
1371 | return; | |
1372 | } | |
1373 | /* Flush the FIFOs and let's go! */ | |
1374 | flush(pl022); | |
b43d65f7 | 1375 | |
b1b6b9aa LW |
1376 | if (pl022->cur_chip->enable_dma) { |
1377 | if (configure_dma(pl022)) { | |
1378 | dev_dbg(&pl022->adev->dev, | |
1379 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1380 | goto err_config_dma; | |
1381 | } | |
b43d65f7 LW |
1382 | return; |
1383 | } | |
b43d65f7 | 1384 | |
b1b6b9aa LW |
1385 | err_config_dma: |
1386 | writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
b43d65f7 LW |
1387 | } |
1388 | ||
b1b6b9aa | 1389 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
b43d65f7 | 1390 | { |
b1b6b9aa | 1391 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
b43d65f7 LW |
1392 | |
1393 | /* Enable target chip */ | |
1394 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1395 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { | |
1396 | /* Error path */ | |
1397 | pl022->cur_msg->state = STATE_ERROR; | |
1398 | pl022->cur_msg->status = -EIO; | |
1399 | giveback(pl022); | |
1400 | return; | |
1401 | } | |
b1b6b9aa LW |
1402 | /* If we're using DMA, set up DMA here */ |
1403 | if (pl022->cur_chip->enable_dma) { | |
1404 | /* Configure DMA transfer */ | |
1405 | if (configure_dma(pl022)) { | |
1406 | dev_dbg(&pl022->adev->dev, | |
1407 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1408 | goto err_config_dma; | |
1409 | } | |
1410 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ | |
1411 | irqflags = DISABLE_ALL_INTERRUPTS; | |
1412 | } | |
1413 | err_config_dma: | |
b43d65f7 LW |
1414 | /* Enable SSP, turn on interrupts */ |
1415 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1416 | SSP_CR1(pl022->virtbase)); | |
b1b6b9aa | 1417 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
b43d65f7 LW |
1418 | } |
1419 | ||
b1b6b9aa | 1420 | static void do_polling_transfer(struct pl022 *pl022) |
b43d65f7 | 1421 | { |
b43d65f7 LW |
1422 | struct spi_message *message = NULL; |
1423 | struct spi_transfer *transfer = NULL; | |
1424 | struct spi_transfer *previous = NULL; | |
1425 | struct chip_data *chip; | |
a18c266f | 1426 | unsigned long time, timeout; |
b43d65f7 LW |
1427 | |
1428 | chip = pl022->cur_chip; | |
1429 | message = pl022->cur_msg; | |
1430 | ||
1431 | while (message->state != STATE_DONE) { | |
1432 | /* Handle for abort */ | |
1433 | if (message->state == STATE_ERROR) | |
1434 | break; | |
1435 | transfer = pl022->cur_transfer; | |
1436 | ||
1437 | /* Delay if requested at end of transfer */ | |
1438 | if (message->state == STATE_RUNNING) { | |
1439 | previous = | |
1440 | list_entry(transfer->transfer_list.prev, | |
1441 | struct spi_transfer, transfer_list); | |
1442 | if (previous->delay_usecs) | |
1443 | udelay(previous->delay_usecs); | |
1444 | if (previous->cs_change) | |
1445 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1446 | } else { | |
1447 | /* STATE_START */ | |
1448 | message->state = STATE_RUNNING; | |
1449 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1450 | } | |
1451 | ||
1452 | /* Configuration Changing Per Transfer */ | |
1453 | if (set_up_next_transfer(pl022, transfer)) { | |
1454 | /* Error path */ | |
1455 | message->state = STATE_ERROR; | |
1456 | break; | |
1457 | } | |
1458 | /* Flush FIFOs and enable SSP */ | |
1459 | flush(pl022); | |
1460 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1461 | SSP_CR1(pl022->virtbase)); | |
1462 | ||
556f4aeb | 1463 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
a18c266f MT |
1464 | |
1465 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); | |
1466 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { | |
1467 | time = jiffies; | |
b43d65f7 | 1468 | readwriter(pl022); |
a18c266f MT |
1469 | if (time_after(time, timeout)) { |
1470 | dev_warn(&pl022->adev->dev, | |
1471 | "%s: timeout!\n", __func__); | |
1472 | message->state = STATE_ERROR; | |
1473 | goto out; | |
1474 | } | |
521999bd | 1475 | cpu_relax(); |
a18c266f | 1476 | } |
b43d65f7 | 1477 | |
25985edc | 1478 | /* Update total byte transferred */ |
b43d65f7 LW |
1479 | message->actual_length += pl022->cur_transfer->len; |
1480 | if (pl022->cur_transfer->cs_change) | |
1481 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); | |
1482 | /* Move to next transfer */ | |
1483 | message->state = next_transfer(pl022); | |
1484 | } | |
a18c266f | 1485 | out: |
b43d65f7 LW |
1486 | /* Handle end of message */ |
1487 | if (message->state == STATE_DONE) | |
1488 | message->status = 0; | |
1489 | else | |
1490 | message->status = -EIO; | |
1491 | ||
1492 | giveback(pl022); | |
1493 | return; | |
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * pump_messages - Workqueue function which processes spi message queue | |
1498 | * @data: pointer to private data of SSP driver | |
1499 | * | |
1500 | * This function checks if there is any spi message in the queue that | |
1501 | * needs processing and delegate control to appropriate function | |
b1b6b9aa | 1502 | * do_polling_transfer()/do_interrupt_dma_transfer() |
b43d65f7 LW |
1503 | * based on the kind of the transfer |
1504 | * | |
1505 | */ | |
1506 | static void pump_messages(struct work_struct *work) | |
1507 | { | |
1508 | struct pl022 *pl022 = | |
1509 | container_of(work, struct pl022, pump_messages); | |
1510 | unsigned long flags; | |
1511 | ||
1512 | /* Lock queue and check for queue work */ | |
1513 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
5e8b821d | 1514 | if (list_empty(&pl022->queue) || !pl022->running) { |
dec5a581 | 1515 | pl022->busy = false; |
b43d65f7 LW |
1516 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1517 | return; | |
1518 | } | |
1519 | /* Make sure we are not already running a message */ | |
1520 | if (pl022->cur_msg) { | |
1521 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1522 | return; | |
1523 | } | |
1524 | /* Extract head of queue */ | |
1525 | pl022->cur_msg = | |
1526 | list_entry(pl022->queue.next, struct spi_message, queue); | |
1527 | ||
1528 | list_del_init(&pl022->cur_msg->queue); | |
dec5a581 | 1529 | pl022->busy = true; |
b43d65f7 LW |
1530 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1531 | ||
1532 | /* Initial message state */ | |
1533 | pl022->cur_msg->state = STATE_START; | |
1534 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, | |
1535 | struct spi_transfer, | |
1536 | transfer_list); | |
1537 | ||
1538 | /* Setup the SPI using the per chip configuration */ | |
1539 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); | |
1540 | /* | |
808f1037 LW |
1541 | * We enable the core voltage and clocks here, then the clocks |
1542 | * and core will be disabled when giveback() is called in each method | |
1543 | * (poll/interrupt/DMA) | |
b43d65f7 | 1544 | */ |
808f1037 | 1545 | amba_vcore_enable(pl022->adev); |
545074fb | 1546 | amba_pclk_enable(pl022->adev); |
b43d65f7 LW |
1547 | clk_enable(pl022->clk); |
1548 | restore_state(pl022); | |
1549 | flush(pl022); | |
1550 | ||
1551 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) | |
1552 | do_polling_transfer(pl022); | |
b43d65f7 | 1553 | else |
b1b6b9aa | 1554 | do_interrupt_dma_transfer(pl022); |
b43d65f7 LW |
1555 | } |
1556 | ||
1557 | ||
1558 | static int __init init_queue(struct pl022 *pl022) | |
1559 | { | |
1560 | INIT_LIST_HEAD(&pl022->queue); | |
1561 | spin_lock_init(&pl022->queue_lock); | |
1562 | ||
5e8b821d | 1563 | pl022->running = false; |
dec5a581 | 1564 | pl022->busy = false; |
b43d65f7 LW |
1565 | |
1566 | tasklet_init(&pl022->pump_transfers, | |
1567 | pump_transfers, (unsigned long)pl022); | |
1568 | ||
1569 | INIT_WORK(&pl022->pump_messages, pump_messages); | |
1570 | pl022->workqueue = create_singlethread_workqueue( | |
1571 | dev_name(pl022->master->dev.parent)); | |
1572 | if (pl022->workqueue == NULL) | |
1573 | return -EBUSY; | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
1578 | ||
1579 | static int start_queue(struct pl022 *pl022) | |
1580 | { | |
1581 | unsigned long flags; | |
1582 | ||
1583 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1584 | ||
5e8b821d | 1585 | if (pl022->running || pl022->busy) { |
b43d65f7 LW |
1586 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1587 | return -EBUSY; | |
1588 | } | |
1589 | ||
5e8b821d | 1590 | pl022->running = true; |
b43d65f7 LW |
1591 | pl022->cur_msg = NULL; |
1592 | pl022->cur_transfer = NULL; | |
1593 | pl022->cur_chip = NULL; | |
1594 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1595 | ||
1596 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | ||
1602 | static int stop_queue(struct pl022 *pl022) | |
1603 | { | |
1604 | unsigned long flags; | |
1605 | unsigned limit = 500; | |
1606 | int status = 0; | |
1607 | ||
1608 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1609 | ||
1610 | /* This is a bit lame, but is optimized for the common execution path. | |
1611 | * A wait_queue on the pl022->busy could be used, but then the common | |
1612 | * execution path (pump_messages) would be required to call wake_up or | |
1613 | * friends on every SPI message. Do this instead */ | |
850a28ec | 1614 | while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) { |
b43d65f7 LW |
1615 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1616 | msleep(10); | |
1617 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1618 | } | |
1619 | ||
1620 | if (!list_empty(&pl022->queue) || pl022->busy) | |
1621 | status = -EBUSY; | |
5e8b821d LW |
1622 | else |
1623 | pl022->running = false; | |
b43d65f7 LW |
1624 | |
1625 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1626 | ||
1627 | return status; | |
1628 | } | |
1629 | ||
1630 | static int destroy_queue(struct pl022 *pl022) | |
1631 | { | |
1632 | int status; | |
1633 | ||
1634 | status = stop_queue(pl022); | |
1635 | /* we are unloading the module or failing to load (only two calls | |
1636 | * to this routine), and neither call can handle a return value. | |
1637 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1638 | * block until all work is done. If the reason that stop_queue | |
1639 | * timed out is that the work will never finish, then it does no | |
1640 | * good to call destroy_workqueue, so return anyway. */ | |
1641 | if (status != 0) | |
1642 | return status; | |
1643 | ||
1644 | destroy_workqueue(pl022->workqueue); | |
1645 | ||
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | static int verify_controller_parameters(struct pl022 *pl022, | |
f9d629c7 | 1650 | struct pl022_config_chip const *chip_info) |
b43d65f7 | 1651 | { |
b43d65f7 LW |
1652 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1653 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { | |
5a1c98be | 1654 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1655 | "interface is configured incorrectly\n"); |
1656 | return -EINVAL; | |
1657 | } | |
1658 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && | |
1659 | (!pl022->vendor->unidir)) { | |
5a1c98be | 1660 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1661 | "unidirectional mode not supported in this " |
1662 | "hardware version\n"); | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | if ((chip_info->hierarchy != SSP_MASTER) | |
1666 | && (chip_info->hierarchy != SSP_SLAVE)) { | |
5a1c98be | 1667 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1668 | "hierarchy is configured incorrectly\n"); |
1669 | return -EINVAL; | |
1670 | } | |
b43d65f7 LW |
1671 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1672 | && (chip_info->com_mode != DMA_TRANSFER) | |
1673 | && (chip_info->com_mode != POLLING_TRANSFER)) { | |
5a1c98be | 1674 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1675 | "Communication mode is configured incorrectly\n"); |
1676 | return -EINVAL; | |
1677 | } | |
1678 | if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM) | |
1679 | || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) { | |
5a1c98be | 1680 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1681 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1682 | return -EINVAL; | |
1683 | } | |
1684 | if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC) | |
1685 | || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) { | |
5a1c98be | 1686 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1687 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1688 | return -EINVAL; | |
1689 | } | |
b43d65f7 LW |
1690 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1691 | if ((chip_info->ctrl_len < SSP_BITS_4) | |
1692 | || (chip_info->ctrl_len > SSP_BITS_32)) { | |
5a1c98be | 1693 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1694 | "CTRL LEN is configured incorrectly\n"); |
1695 | return -EINVAL; | |
1696 | } | |
1697 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) | |
1698 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { | |
5a1c98be | 1699 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1700 | "Wait State is configured incorrectly\n"); |
1701 | return -EINVAL; | |
1702 | } | |
556f4aeb LW |
1703 | /* Half duplex is only available in the ST Micro version */ |
1704 | if (pl022->vendor->extended_cr) { | |
1705 | if ((chip_info->duplex != | |
1706 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
1707 | && (chip_info->duplex != | |
4a4fd471 | 1708 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
5a1c98be | 1709 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1710 | "Microwire duplex mode is configured incorrectly\n"); |
1711 | return -EINVAL; | |
4a4fd471 | 1712 | } |
556f4aeb LW |
1713 | } else { |
1714 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
5a1c98be | 1715 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1716 | "Microwire half duplex mode requested," |
1717 | " but this is only available in the" | |
1718 | " ST version of PL022\n"); | |
b43d65f7 LW |
1719 | return -EINVAL; |
1720 | } | |
1721 | } | |
b43d65f7 LW |
1722 | return 0; |
1723 | } | |
1724 | ||
1725 | /** | |
1726 | * pl022_transfer - transfer function registered to SPI master framework | |
1727 | * @spi: spi device which is requesting transfer | |
1728 | * @msg: spi message which is to handled is queued to driver queue | |
1729 | * | |
1730 | * This function is registered to the SPI framework for this SPI master | |
1731 | * controller. It will queue the spi_message in the queue of driver if | |
1732 | * the queue is not stopped and return. | |
1733 | */ | |
1734 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) | |
1735 | { | |
1736 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
1737 | unsigned long flags; | |
1738 | ||
1739 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1740 | ||
5e8b821d | 1741 | if (!pl022->running) { |
b43d65f7 LW |
1742 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1743 | return -ESHUTDOWN; | |
1744 | } | |
1745 | msg->actual_length = 0; | |
1746 | msg->status = -EINPROGRESS; | |
1747 | msg->state = STATE_START; | |
1748 | ||
1749 | list_add_tail(&msg->queue, &pl022->queue); | |
5e8b821d | 1750 | if (pl022->running && !pl022->busy) |
b43d65f7 LW |
1751 | queue_work(pl022->workqueue, &pl022->pump_messages); |
1752 | ||
1753 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | static int calculate_effective_freq(struct pl022 *pl022, | |
1758 | int freq, | |
1759 | struct ssp_clock_params *clk_freq) | |
1760 | { | |
1761 | /* Lets calculate the frequency parameters */ | |
1762 | u16 cpsdvsr = 2; | |
1763 | u16 scr = 0; | |
1764 | bool freq_found = false; | |
1765 | u32 rate; | |
1766 | u32 max_tclk; | |
1767 | u32 min_tclk; | |
1768 | ||
1769 | rate = clk_get_rate(pl022->clk); | |
1770 | /* cpsdvscr = 2 & scr 0 */ | |
1771 | max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); | |
1772 | /* cpsdvsr = 254 & scr = 255 */ | |
1773 | min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); | |
1774 | ||
1775 | if ((freq <= max_tclk) && (freq >= min_tclk)) { | |
1776 | while (cpsdvsr <= CPSDVR_MAX && !freq_found) { | |
1777 | while (scr <= SCR_MAX && !freq_found) { | |
1778 | if ((rate / | |
1779 | (cpsdvsr * (1 + scr))) > freq) | |
1780 | scr += 1; | |
1781 | else { | |
1782 | /* | |
1783 | * This bool is made true when | |
1784 | * effective frequency >= | |
1785 | * target frequency is found | |
1786 | */ | |
1787 | freq_found = true; | |
1788 | if ((rate / | |
1789 | (cpsdvsr * (1 + scr))) != freq) { | |
1790 | if (scr == SCR_MIN) { | |
1791 | cpsdvsr -= 2; | |
1792 | scr = SCR_MAX; | |
1793 | } else | |
1794 | scr -= 1; | |
1795 | } | |
1796 | } | |
1797 | } | |
1798 | if (!freq_found) { | |
1799 | cpsdvsr += 2; | |
1800 | scr = SCR_MIN; | |
1801 | } | |
1802 | } | |
1803 | if (cpsdvsr != 0) { | |
1804 | dev_dbg(&pl022->adev->dev, | |
1805 | "SSP Effective Frequency is %u\n", | |
1806 | (rate / (cpsdvsr * (1 + scr)))); | |
1807 | clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); | |
1808 | clk_freq->scr = (u8) (scr & 0xFF); | |
1809 | dev_dbg(&pl022->adev->dev, | |
1810 | "SSP cpsdvsr = %d, scr = %d\n", | |
1811 | clk_freq->cpsdvsr, clk_freq->scr); | |
1812 | } | |
1813 | } else { | |
1814 | dev_err(&pl022->adev->dev, | |
1815 | "controller data is incorrect: out of range frequency"); | |
1816 | return -EINVAL; | |
1817 | } | |
1818 | return 0; | |
1819 | } | |
1820 | ||
f9d629c7 LW |
1821 | |
1822 | /* | |
1823 | * A piece of default chip info unless the platform | |
1824 | * supplies it. | |
1825 | */ | |
1826 | static const struct pl022_config_chip pl022_default_chip_info = { | |
1827 | .com_mode = POLLING_TRANSFER, | |
1828 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | |
1829 | .hierarchy = SSP_SLAVE, | |
1830 | .slave_tx_disable = DO_NOT_DRIVE_TX, | |
1831 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | |
1832 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | |
1833 | .ctrl_len = SSP_BITS_8, | |
1834 | .wait_state = SSP_MWIRE_WAIT_ZERO, | |
1835 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | |
1836 | .cs_control = null_cs_control, | |
1837 | }; | |
1838 | ||
1839 | ||
b43d65f7 LW |
1840 | /** |
1841 | * pl022_setup - setup function registered to SPI master framework | |
1842 | * @spi: spi device which is requesting setup | |
1843 | * | |
1844 | * This function is registered to the SPI framework for this SPI master | |
1845 | * controller. If it is the first time when setup is called by this device, | |
1846 | * this function will initialize the runtime state for this chip and save | |
1847 | * the same in the device structure. Else it will update the runtime info | |
1848 | * with the updated chip info. Nothing is really being written to the | |
1849 | * controller hardware here, that is not done until the actual transfer | |
1850 | * commence. | |
1851 | */ | |
b43d65f7 LW |
1852 | static int pl022_setup(struct spi_device *spi) |
1853 | { | |
f9d629c7 | 1854 | struct pl022_config_chip const *chip_info; |
b43d65f7 | 1855 | struct chip_data *chip; |
94a1b6d8 | 1856 | struct ssp_clock_params clk_freq = {0, }; |
b43d65f7 LW |
1857 | int status = 0; |
1858 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
bde435a9 KW |
1859 | unsigned int bits = spi->bits_per_word; |
1860 | u32 tmp; | |
b43d65f7 LW |
1861 | |
1862 | if (!spi->max_speed_hz) | |
1863 | return -EINVAL; | |
1864 | ||
1865 | /* Get controller_state if one is supplied */ | |
1866 | chip = spi_get_ctldata(spi); | |
1867 | ||
1868 | if (chip == NULL) { | |
1869 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1870 | if (!chip) { | |
1871 | dev_err(&spi->dev, | |
1872 | "cannot allocate controller state\n"); | |
1873 | return -ENOMEM; | |
1874 | } | |
1875 | dev_dbg(&spi->dev, | |
1876 | "allocated memory for controller's runtime state\n"); | |
1877 | } | |
1878 | ||
1879 | /* Get controller data if one is supplied */ | |
1880 | chip_info = spi->controller_data; | |
1881 | ||
1882 | if (chip_info == NULL) { | |
f9d629c7 | 1883 | chip_info = &pl022_default_chip_info; |
b43d65f7 LW |
1884 | /* spi_board_info.controller_data not is supplied */ |
1885 | dev_dbg(&spi->dev, | |
1886 | "using default controller_data settings\n"); | |
f9d629c7 | 1887 | } else |
b43d65f7 LW |
1888 | dev_dbg(&spi->dev, |
1889 | "using user supplied controller_data settings\n"); | |
b43d65f7 LW |
1890 | |
1891 | /* | |
1892 | * We can override with custom divisors, else we use the board | |
1893 | * frequency setting | |
1894 | */ | |
1895 | if ((0 == chip_info->clk_freq.cpsdvsr) | |
1896 | && (0 == chip_info->clk_freq.scr)) { | |
1897 | status = calculate_effective_freq(pl022, | |
1898 | spi->max_speed_hz, | |
f9d629c7 | 1899 | &clk_freq); |
b43d65f7 LW |
1900 | if (status < 0) |
1901 | goto err_config_params; | |
1902 | } else { | |
f9d629c7 LW |
1903 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1904 | if ((clk_freq.cpsdvsr % 2) != 0) | |
1905 | clk_freq.cpsdvsr = | |
1906 | clk_freq.cpsdvsr - 1; | |
b43d65f7 | 1907 | } |
f9d629c7 LW |
1908 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1909 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { | |
1910 | dev_err(&spi->dev, | |
1911 | "cpsdvsr is configured incorrectly\n"); | |
1912 | goto err_config_params; | |
1913 | } | |
1914 | ||
1915 | ||
b43d65f7 LW |
1916 | status = verify_controller_parameters(pl022, chip_info); |
1917 | if (status) { | |
1918 | dev_err(&spi->dev, "controller data is incorrect"); | |
1919 | goto err_config_params; | |
1920 | } | |
f9d629c7 | 1921 | |
083be3f0 LW |
1922 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
1923 | pl022->tx_lev_trig = chip_info->tx_lev_trig; | |
1924 | ||
b43d65f7 LW |
1925 | /* Now set controller state based on controller data */ |
1926 | chip->xfer_type = chip_info->com_mode; | |
f9d629c7 LW |
1927 | if (!chip_info->cs_control) { |
1928 | chip->cs_control = null_cs_control; | |
1929 | dev_warn(&spi->dev, | |
1930 | "chip select function is NULL for this chip\n"); | |
1931 | } else | |
1932 | chip->cs_control = chip_info->cs_control; | |
b43d65f7 | 1933 | |
bde435a9 KW |
1934 | if (bits <= 3) { |
1935 | /* PL022 doesn't support less than 4-bits */ | |
1936 | status = -ENOTSUPP; | |
1937 | goto err_config_params; | |
1938 | } else if (bits <= 8) { | |
1939 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | |
b43d65f7 LW |
1940 | chip->n_bytes = 1; |
1941 | chip->read = READING_U8; | |
1942 | chip->write = WRITING_U8; | |
bde435a9 | 1943 | } else if (bits <= 16) { |
b43d65f7 LW |
1944 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1945 | chip->n_bytes = 2; | |
1946 | chip->read = READING_U16; | |
1947 | chip->write = WRITING_U16; | |
1948 | } else { | |
1949 | if (pl022->vendor->max_bpw >= 32) { | |
1950 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); | |
1951 | chip->n_bytes = 4; | |
1952 | chip->read = READING_U32; | |
1953 | chip->write = WRITING_U32; | |
1954 | } else { | |
1955 | dev_err(&spi->dev, | |
1956 | "illegal data size for this controller!\n"); | |
1957 | dev_err(&spi->dev, | |
1958 | "a standard pl022 can only handle " | |
1959 | "1 <= n <= 16 bit words\n"); | |
bde435a9 | 1960 | status = -ENOTSUPP; |
b43d65f7 LW |
1961 | goto err_config_params; |
1962 | } | |
1963 | } | |
1964 | ||
1965 | /* Now Initialize all register settings required for this chip */ | |
1966 | chip->cr0 = 0; | |
1967 | chip->cr1 = 0; | |
1968 | chip->dmacr = 0; | |
1969 | chip->cpsr = 0; | |
1970 | if ((chip_info->com_mode == DMA_TRANSFER) | |
1971 | && ((pl022->master_info)->enable_dma)) { | |
b1b6b9aa | 1972 | chip->enable_dma = true; |
b43d65f7 | 1973 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
b43d65f7 LW |
1974 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1975 | SSP_DMACR_MASK_RXDMAE, 0); | |
1976 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, | |
1977 | SSP_DMACR_MASK_TXDMAE, 1); | |
1978 | } else { | |
b1b6b9aa | 1979 | chip->enable_dma = false; |
b43d65f7 LW |
1980 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
1981 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1982 | SSP_DMACR_MASK_RXDMAE, 0); | |
1983 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1984 | SSP_DMACR_MASK_TXDMAE, 1); | |
1985 | } | |
1986 | ||
f9d629c7 | 1987 | chip->cpsr = clk_freq.cpsdvsr; |
b43d65f7 | 1988 | |
556f4aeb LW |
1989 | /* Special setup for the ST micro extended control registers */ |
1990 | if (pl022->vendor->extended_cr) { | |
bde435a9 KW |
1991 | u32 etx; |
1992 | ||
781c7b12 LW |
1993 | if (pl022->vendor->pl023) { |
1994 | /* These bits are only in the PL023 */ | |
1995 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, | |
1996 | SSP_CR1_MASK_FBCLKDEL_ST, 13); | |
1997 | } else { | |
1998 | /* These bits are in the PL022 but not PL023 */ | |
1999 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, | |
2000 | SSP_CR0_MASK_HALFDUP_ST, 5); | |
2001 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, | |
2002 | SSP_CR0_MASK_CSS_ST, 16); | |
2003 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2004 | SSP_CR0_MASK_FRF_ST, 21); | |
2005 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, | |
2006 | SSP_CR1_MASK_MWAIT_ST, 6); | |
2007 | } | |
bde435a9 | 2008 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb | 2009 | SSP_CR0_MASK_DSS_ST, 0); |
bde435a9 KW |
2010 | |
2011 | if (spi->mode & SPI_LSB_FIRST) { | |
2012 | tmp = SSP_RX_LSB; | |
2013 | etx = SSP_TX_LSB; | |
2014 | } else { | |
2015 | tmp = SSP_RX_MSB; | |
2016 | etx = SSP_TX_MSB; | |
2017 | } | |
2018 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); | |
2019 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); | |
556f4aeb LW |
2020 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
2021 | SSP_CR1_MASK_RXIFLSEL_ST, 7); | |
2022 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, | |
2023 | SSP_CR1_MASK_TXIFLSEL_ST, 10); | |
2024 | } else { | |
bde435a9 | 2025 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb LW |
2026 | SSP_CR0_MASK_DSS, 0); |
2027 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
2028 | SSP_CR0_MASK_FRF, 4); | |
2029 | } | |
bde435a9 | 2030 | |
556f4aeb | 2031 | /* Stuff that is common for all versions */ |
bde435a9 KW |
2032 | if (spi->mode & SPI_CPOL) |
2033 | tmp = SSP_CLK_POL_IDLE_HIGH; | |
2034 | else | |
2035 | tmp = SSP_CLK_POL_IDLE_LOW; | |
2036 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); | |
2037 | ||
2038 | if (spi->mode & SPI_CPHA) | |
2039 | tmp = SSP_CLK_SECOND_EDGE; | |
2040 | else | |
2041 | tmp = SSP_CLK_FIRST_EDGE; | |
2042 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); | |
2043 | ||
f9d629c7 | 2044 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
781c7b12 | 2045 | /* Loopback is available on all versions except PL023 */ |
06fb01fd | 2046 | if (pl022->vendor->loopback) { |
bde435a9 KW |
2047 | if (spi->mode & SPI_LOOP) |
2048 | tmp = LOOPBACK_ENABLED; | |
2049 | else | |
2050 | tmp = LOOPBACK_DISABLED; | |
2051 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); | |
2052 | } | |
b43d65f7 LW |
2053 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
2054 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | |
2055 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); | |
b43d65f7 LW |
2056 | |
2057 | /* Save controller_state */ | |
2058 | spi_set_ctldata(spi, chip); | |
2059 | return status; | |
2060 | err_config_params: | |
bde435a9 | 2061 | spi_set_ctldata(spi, NULL); |
b43d65f7 LW |
2062 | kfree(chip); |
2063 | return status; | |
2064 | } | |
2065 | ||
2066 | /** | |
2067 | * pl022_cleanup - cleanup function registered to SPI master framework | |
2068 | * @spi: spi device which is requesting cleanup | |
2069 | * | |
2070 | * This function is registered to the SPI framework for this SPI master | |
2071 | * controller. It will free the runtime state of chip. | |
2072 | */ | |
2073 | static void pl022_cleanup(struct spi_device *spi) | |
2074 | { | |
2075 | struct chip_data *chip = spi_get_ctldata(spi); | |
2076 | ||
2077 | spi_set_ctldata(spi, NULL); | |
2078 | kfree(chip); | |
2079 | } | |
2080 | ||
2081 | ||
b4225885 | 2082 | static int __devinit |
aa25afad | 2083 | pl022_probe(struct amba_device *adev, const struct amba_id *id) |
b43d65f7 LW |
2084 | { |
2085 | struct device *dev = &adev->dev; | |
2086 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; | |
2087 | struct spi_master *master; | |
2088 | struct pl022 *pl022 = NULL; /*Data for this driver */ | |
2089 | int status = 0; | |
2090 | ||
2091 | dev_info(&adev->dev, | |
2092 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | |
2093 | if (platform_info == NULL) { | |
2094 | dev_err(&adev->dev, "probe - no platform data supplied\n"); | |
2095 | status = -ENODEV; | |
2096 | goto err_no_pdata; | |
2097 | } | |
2098 | ||
2099 | /* Allocate master with space for data */ | |
2100 | master = spi_alloc_master(dev, sizeof(struct pl022)); | |
2101 | if (master == NULL) { | |
2102 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | |
2103 | status = -ENOMEM; | |
2104 | goto err_no_master; | |
2105 | } | |
2106 | ||
2107 | pl022 = spi_master_get_devdata(master); | |
2108 | pl022->master = master; | |
2109 | pl022->master_info = platform_info; | |
2110 | pl022->adev = adev; | |
2111 | pl022->vendor = id->data; | |
2112 | ||
2113 | /* | |
2114 | * Bus Number Which has been Assigned to this SSP controller | |
2115 | * on this board | |
2116 | */ | |
2117 | master->bus_num = platform_info->bus_id; | |
2118 | master->num_chipselect = platform_info->num_chipselect; | |
2119 | master->cleanup = pl022_cleanup; | |
2120 | master->setup = pl022_setup; | |
2121 | master->transfer = pl022_transfer; | |
2122 | ||
bde435a9 KW |
2123 | /* |
2124 | * Supports mode 0-3, loopback, and active low CS. Transfers are | |
2125 | * always MS bit first on the original pl022. | |
2126 | */ | |
2127 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
2128 | if (pl022->vendor->extended_cr) | |
2129 | master->mode_bits |= SPI_LSB_FIRST; | |
2130 | ||
b43d65f7 LW |
2131 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2132 | ||
2133 | status = amba_request_regions(adev, NULL); | |
2134 | if (status) | |
2135 | goto err_no_ioregion; | |
2136 | ||
b1b6b9aa | 2137 | pl022->phybase = adev->res.start; |
b43d65f7 LW |
2138 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2139 | if (pl022->virtbase == NULL) { | |
2140 | status = -ENOMEM; | |
2141 | goto err_no_ioremap; | |
2142 | } | |
2143 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", | |
2144 | adev->res.start, pl022->virtbase); | |
2145 | ||
2146 | pl022->clk = clk_get(&adev->dev, NULL); | |
2147 | if (IS_ERR(pl022->clk)) { | |
2148 | status = PTR_ERR(pl022->clk); | |
2149 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | |
2150 | goto err_no_clk; | |
2151 | } | |
2152 | ||
2153 | /* Disable SSP */ | |
b43d65f7 LW |
2154 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2155 | SSP_CR1(pl022->virtbase)); | |
2156 | load_ssp_default_config(pl022); | |
b43d65f7 LW |
2157 | |
2158 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", | |
2159 | pl022); | |
2160 | if (status < 0) { | |
2161 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | |
2162 | goto err_no_irq; | |
2163 | } | |
b1b6b9aa LW |
2164 | |
2165 | /* Get DMA channels */ | |
2166 | if (platform_info->enable_dma) { | |
2167 | status = pl022_dma_probe(pl022); | |
2168 | if (status != 0) | |
43c64015 | 2169 | platform_info->enable_dma = 0; |
b1b6b9aa LW |
2170 | } |
2171 | ||
b43d65f7 LW |
2172 | /* Initialize and start queue */ |
2173 | status = init_queue(pl022); | |
2174 | if (status != 0) { | |
2175 | dev_err(&adev->dev, "probe - problem initializing queue\n"); | |
2176 | goto err_init_queue; | |
2177 | } | |
2178 | status = start_queue(pl022); | |
2179 | if (status != 0) { | |
2180 | dev_err(&adev->dev, "probe - problem starting queue\n"); | |
2181 | goto err_start_queue; | |
2182 | } | |
2183 | /* Register with the SPI framework */ | |
2184 | amba_set_drvdata(adev, pl022); | |
2185 | status = spi_register_master(master); | |
2186 | if (status != 0) { | |
2187 | dev_err(&adev->dev, | |
2188 | "probe - problem registering spi master\n"); | |
2189 | goto err_spi_register; | |
2190 | } | |
25985edc | 2191 | dev_dbg(dev, "probe succeeded\n"); |
808f1037 LW |
2192 | /* |
2193 | * Disable the silicon block pclk and any voltage domain and just | |
2194 | * power it up and clock it when it's needed | |
2195 | */ | |
545074fb | 2196 | amba_pclk_disable(adev); |
808f1037 | 2197 | amba_vcore_disable(adev); |
b43d65f7 LW |
2198 | return 0; |
2199 | ||
2200 | err_spi_register: | |
2201 | err_start_queue: | |
2202 | err_init_queue: | |
2203 | destroy_queue(pl022); | |
b1b6b9aa | 2204 | pl022_dma_remove(pl022); |
b43d65f7 LW |
2205 | free_irq(adev->irq[0], pl022); |
2206 | err_no_irq: | |
2207 | clk_put(pl022->clk); | |
2208 | err_no_clk: | |
2209 | iounmap(pl022->virtbase); | |
2210 | err_no_ioremap: | |
2211 | amba_release_regions(adev); | |
2212 | err_no_ioregion: | |
2213 | spi_master_put(master); | |
2214 | err_no_master: | |
2215 | err_no_pdata: | |
2216 | return status; | |
2217 | } | |
2218 | ||
b4225885 | 2219 | static int __devexit |
b43d65f7 LW |
2220 | pl022_remove(struct amba_device *adev) |
2221 | { | |
2222 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2223 | int status = 0; | |
2224 | if (!pl022) | |
2225 | return 0; | |
2226 | ||
2227 | /* Remove the queue */ | |
2228 | status = destroy_queue(pl022); | |
2229 | if (status != 0) { | |
2230 | dev_err(&adev->dev, | |
2231 | "queue remove failed (%d)\n", status); | |
2232 | return status; | |
2233 | } | |
2234 | load_ssp_default_config(pl022); | |
b1b6b9aa | 2235 | pl022_dma_remove(pl022); |
b43d65f7 LW |
2236 | free_irq(adev->irq[0], pl022); |
2237 | clk_disable(pl022->clk); | |
2238 | clk_put(pl022->clk); | |
2239 | iounmap(pl022->virtbase); | |
2240 | amba_release_regions(adev); | |
2241 | tasklet_disable(&pl022->pump_transfers); | |
2242 | spi_unregister_master(pl022->master); | |
2243 | spi_master_put(pl022->master); | |
2244 | amba_set_drvdata(adev, NULL); | |
25985edc | 2245 | dev_dbg(&adev->dev, "remove succeeded\n"); |
b43d65f7 LW |
2246 | return 0; |
2247 | } | |
2248 | ||
2249 | #ifdef CONFIG_PM | |
2250 | static int pl022_suspend(struct amba_device *adev, pm_message_t state) | |
2251 | { | |
2252 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2253 | int status = 0; | |
2254 | ||
2255 | status = stop_queue(pl022); | |
2256 | if (status) { | |
2257 | dev_warn(&adev->dev, "suspend cannot stop queue\n"); | |
2258 | return status; | |
2259 | } | |
2260 | ||
808f1037 | 2261 | amba_vcore_enable(adev); |
545074fb | 2262 | amba_pclk_enable(adev); |
b43d65f7 | 2263 | load_ssp_default_config(pl022); |
545074fb | 2264 | amba_pclk_disable(adev); |
808f1037 | 2265 | amba_vcore_disable(adev); |
b43d65f7 LW |
2266 | dev_dbg(&adev->dev, "suspended\n"); |
2267 | return 0; | |
2268 | } | |
2269 | ||
2270 | static int pl022_resume(struct amba_device *adev) | |
2271 | { | |
2272 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2273 | int status = 0; | |
2274 | ||
2275 | /* Start the queue running */ | |
2276 | status = start_queue(pl022); | |
2277 | if (status) | |
2278 | dev_err(&adev->dev, "problem starting queue (%d)\n", status); | |
2279 | else | |
2280 | dev_dbg(&adev->dev, "resumed\n"); | |
2281 | ||
2282 | return status; | |
2283 | } | |
2284 | #else | |
2285 | #define pl022_suspend NULL | |
2286 | #define pl022_resume NULL | |
2287 | #endif /* CONFIG_PM */ | |
2288 | ||
2289 | static struct vendor_data vendor_arm = { | |
2290 | .fifodepth = 8, | |
2291 | .max_bpw = 16, | |
2292 | .unidir = false, | |
556f4aeb | 2293 | .extended_cr = false, |
781c7b12 | 2294 | .pl023 = false, |
06fb01fd | 2295 | .loopback = true, |
b43d65f7 LW |
2296 | }; |
2297 | ||
2298 | ||
2299 | static struct vendor_data vendor_st = { | |
2300 | .fifodepth = 32, | |
2301 | .max_bpw = 32, | |
2302 | .unidir = false, | |
556f4aeb | 2303 | .extended_cr = true, |
781c7b12 | 2304 | .pl023 = false, |
06fb01fd | 2305 | .loopback = true, |
781c7b12 LW |
2306 | }; |
2307 | ||
2308 | static struct vendor_data vendor_st_pl023 = { | |
2309 | .fifodepth = 32, | |
2310 | .max_bpw = 32, | |
2311 | .unidir = false, | |
2312 | .extended_cr = true, | |
2313 | .pl023 = true, | |
06fb01fd PL |
2314 | .loopback = false, |
2315 | }; | |
2316 | ||
2317 | static struct vendor_data vendor_db5500_pl023 = { | |
2318 | .fifodepth = 32, | |
2319 | .max_bpw = 32, | |
2320 | .unidir = false, | |
2321 | .extended_cr = true, | |
2322 | .pl023 = true, | |
2323 | .loopback = true, | |
b43d65f7 LW |
2324 | }; |
2325 | ||
2326 | static struct amba_id pl022_ids[] = { | |
2327 | { | |
2328 | /* | |
2329 | * ARM PL022 variant, this has a 16bit wide | |
2330 | * and 8 locations deep TX/RX FIFO | |
2331 | */ | |
2332 | .id = 0x00041022, | |
2333 | .mask = 0x000fffff, | |
2334 | .data = &vendor_arm, | |
2335 | }, | |
2336 | { | |
2337 | /* | |
2338 | * ST Micro derivative, this has 32bit wide | |
2339 | * and 32 locations deep TX/RX FIFO | |
2340 | */ | |
e89e04fc | 2341 | .id = 0x01080022, |
b43d65f7 LW |
2342 | .mask = 0xffffffff, |
2343 | .data = &vendor_st, | |
2344 | }, | |
781c7b12 LW |
2345 | { |
2346 | /* | |
2347 | * ST-Ericsson derivative "PL023" (this is not | |
2348 | * an official ARM number), this is a PL022 SSP block | |
2349 | * stripped to SPI mode only, it has 32bit wide | |
2350 | * and 32 locations deep TX/RX FIFO but no extended | |
2351 | * CR0/CR1 register | |
2352 | */ | |
2353 | .id = 0x00080023, | |
2354 | .mask = 0xffffffff, | |
2355 | .data = &vendor_st_pl023, | |
2356 | }, | |
06fb01fd PL |
2357 | { |
2358 | .id = 0x10080023, | |
2359 | .mask = 0xffffffff, | |
2360 | .data = &vendor_db5500_pl023, | |
2361 | }, | |
b43d65f7 LW |
2362 | { 0, 0 }, |
2363 | }; | |
2364 | ||
2365 | static struct amba_driver pl022_driver = { | |
2366 | .drv = { | |
2367 | .name = "ssp-pl022", | |
2368 | }, | |
2369 | .id_table = pl022_ids, | |
2370 | .probe = pl022_probe, | |
b4225885 | 2371 | .remove = __devexit_p(pl022_remove), |
b43d65f7 LW |
2372 | .suspend = pl022_suspend, |
2373 | .resume = pl022_resume, | |
2374 | }; | |
2375 | ||
2376 | ||
2377 | static int __init pl022_init(void) | |
2378 | { | |
2379 | return amba_driver_register(&pl022_driver); | |
2380 | } | |
2381 | ||
25c8e03b | 2382 | subsys_initcall(pl022_init); |
b43d65f7 LW |
2383 | |
2384 | static void __exit pl022_exit(void) | |
2385 | { | |
2386 | amba_driver_unregister(&pl022_driver); | |
2387 | } | |
2388 | ||
2389 | module_exit(pl022_exit); | |
2390 | ||
2391 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
2392 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); | |
2393 | MODULE_LICENSE("GPL"); |