Commit | Line | Data |
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b43d65f7 | 1 | /* |
b43d65f7 LW |
2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
3 | * | |
4 | * Copyright (C) 2008-2009 ST-Ericsson AB | |
5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. | |
6 | * | |
7 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
8 | * | |
9 | * Initial version inspired by: | |
10 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c | |
11 | * Initial adoption to PL022 by: | |
12 | * Sachin Verma <sachin.verma@st.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | */ | |
24 | ||
b43d65f7 LW |
25 | #include <linux/init.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/spi/spi.h> | |
b43d65f7 LW |
32 | #include <linux/delay.h> |
33 | #include <linux/clk.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/amba/bus.h> | |
36 | #include <linux/amba/pl022.h> | |
37 | #include <linux/io.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
b1b6b9aa LW |
39 | #include <linux/dmaengine.h> |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/scatterlist.h> | |
bcda6ff8 | 42 | #include <linux/pm_runtime.h> |
f6f46de1 | 43 | #include <linux/gpio.h> |
6d3952a7 | 44 | #include <linux/of_gpio.h> |
4f5e1b37 | 45 | #include <linux/pinctrl/consumer.h> |
b43d65f7 LW |
46 | |
47 | /* | |
48 | * This macro is used to define some register default values. | |
49 | * reg is masked with mask, the OR:ed with an (again masked) | |
50 | * val shifted sb steps to the left. | |
51 | */ | |
52 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ | |
53 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) | |
54 | ||
55 | /* | |
56 | * This macro is also used to define some default values. | |
57 | * It will just shift val by sb steps to the left and mask | |
58 | * the result with mask. | |
59 | */ | |
60 | #define GEN_MASK_BITS(val, mask, sb) \ | |
61 | (((val)<<(sb)) & (mask)) | |
62 | ||
63 | #define DRIVE_TX 0 | |
64 | #define DO_NOT_DRIVE_TX 1 | |
65 | ||
66 | #define DO_NOT_QUEUE_DMA 0 | |
67 | #define QUEUE_DMA 1 | |
68 | ||
69 | #define RX_TRANSFER 1 | |
70 | #define TX_TRANSFER 2 | |
71 | ||
72 | /* | |
73 | * Macros to access SSP Registers with their offsets | |
74 | */ | |
75 | #define SSP_CR0(r) (r + 0x000) | |
76 | #define SSP_CR1(r) (r + 0x004) | |
77 | #define SSP_DR(r) (r + 0x008) | |
78 | #define SSP_SR(r) (r + 0x00C) | |
79 | #define SSP_CPSR(r) (r + 0x010) | |
80 | #define SSP_IMSC(r) (r + 0x014) | |
81 | #define SSP_RIS(r) (r + 0x018) | |
82 | #define SSP_MIS(r) (r + 0x01C) | |
83 | #define SSP_ICR(r) (r + 0x020) | |
84 | #define SSP_DMACR(r) (r + 0x024) | |
85 | #define SSP_ITCR(r) (r + 0x080) | |
86 | #define SSP_ITIP(r) (r + 0x084) | |
87 | #define SSP_ITOP(r) (r + 0x088) | |
88 | #define SSP_TDR(r) (r + 0x08C) | |
89 | ||
90 | #define SSP_PID0(r) (r + 0xFE0) | |
91 | #define SSP_PID1(r) (r + 0xFE4) | |
92 | #define SSP_PID2(r) (r + 0xFE8) | |
93 | #define SSP_PID3(r) (r + 0xFEC) | |
94 | ||
95 | #define SSP_CID0(r) (r + 0xFF0) | |
96 | #define SSP_CID1(r) (r + 0xFF4) | |
97 | #define SSP_CID2(r) (r + 0xFF8) | |
98 | #define SSP_CID3(r) (r + 0xFFC) | |
99 | ||
100 | /* | |
101 | * SSP Control Register 0 - SSP_CR0 | |
102 | */ | |
556f4aeb LW |
103 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
104 | #define SSP_CR0_MASK_FRF (0x3UL << 4) | |
b43d65f7 LW |
105 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
106 | #define SSP_CR0_MASK_SPH (0x1UL << 7) | |
107 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) | |
556f4aeb LW |
108 | |
109 | /* | |
110 | * The ST version of this block moves som bits | |
111 | * in SSP_CR0 and extends it to 32 bits | |
112 | */ | |
113 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) | |
114 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) | |
115 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | |
116 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | |
117 | ||
b43d65f7 LW |
118 | /* |
119 | * SSP Control Register 0 - SSP_CR1 | |
120 | */ | |
121 | #define SSP_CR1_MASK_LBM (0x1UL << 0) | |
122 | #define SSP_CR1_MASK_SSE (0x1UL << 1) | |
123 | #define SSP_CR1_MASK_MS (0x1UL << 2) | |
124 | #define SSP_CR1_MASK_SOD (0x1UL << 3) | |
b43d65f7 LW |
125 | |
126 | /* | |
556f4aeb LW |
127 | * The ST version of this block adds some bits |
128 | * in SSP_CR1 | |
b43d65f7 | 129 | */ |
556f4aeb LW |
130 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
131 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) | |
132 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) | |
133 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) | |
134 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) | |
781c7b12 LW |
135 | /* This one is only in the PL023 variant */ |
136 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) | |
b43d65f7 LW |
137 | |
138 | /* | |
139 | * SSP Status Register - SSP_SR | |
140 | */ | |
141 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ | |
142 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ | |
143 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ | |
556f4aeb | 144 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
b43d65f7 LW |
145 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
146 | ||
147 | /* | |
148 | * SSP Clock Prescale Register - SSP_CPSR | |
149 | */ | |
150 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) | |
151 | ||
152 | /* | |
153 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC | |
154 | */ | |
155 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ | |
156 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ | |
157 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ | |
158 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ | |
159 | ||
160 | /* | |
161 | * SSP Raw Interrupt Status Register - SSP_RIS | |
162 | */ | |
163 | /* Receive Overrun Raw Interrupt status */ | |
164 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) | |
165 | /* Receive Timeout Raw Interrupt status */ | |
166 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) | |
167 | /* Receive FIFO Raw Interrupt status */ | |
168 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) | |
169 | /* Transmit FIFO Raw Interrupt status */ | |
170 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) | |
171 | ||
172 | /* | |
173 | * SSP Masked Interrupt Status Register - SSP_MIS | |
174 | */ | |
175 | /* Receive Overrun Masked Interrupt status */ | |
176 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) | |
177 | /* Receive Timeout Masked Interrupt status */ | |
178 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) | |
179 | /* Receive FIFO Masked Interrupt status */ | |
180 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) | |
181 | /* Transmit FIFO Masked Interrupt status */ | |
182 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) | |
183 | ||
184 | /* | |
185 | * SSP Interrupt Clear Register - SSP_ICR | |
186 | */ | |
187 | /* Receive Overrun Raw Clear Interrupt bit */ | |
188 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) | |
189 | /* Receive Timeout Clear Interrupt bit */ | |
190 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) | |
191 | ||
192 | /* | |
193 | * SSP DMA Control Register - SSP_DMACR | |
194 | */ | |
195 | /* Receive DMA Enable bit */ | |
196 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) | |
197 | /* Transmit DMA Enable bit */ | |
198 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) | |
199 | ||
200 | /* | |
201 | * SSP Integration Test control Register - SSP_ITCR | |
202 | */ | |
203 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) | |
204 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) | |
205 | ||
206 | /* | |
207 | * SSP Integration Test Input Register - SSP_ITIP | |
208 | */ | |
209 | #define ITIP_MASK_SSPRXD (0x1UL << 0) | |
210 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) | |
211 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) | |
212 | #define ITIP_MASK_RXDMAC (0x1UL << 3) | |
213 | #define ITIP_MASK_TXDMAC (0x1UL << 4) | |
214 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) | |
215 | ||
216 | /* | |
217 | * SSP Integration Test output Register - SSP_ITOP | |
218 | */ | |
219 | #define ITOP_MASK_SSPTXD (0x1UL << 0) | |
220 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) | |
221 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) | |
222 | #define ITOP_MASK_SSPOEn (0x1UL << 3) | |
223 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) | |
224 | #define ITOP_MASK_RORINTR (0x1UL << 5) | |
225 | #define ITOP_MASK_RTINTR (0x1UL << 6) | |
226 | #define ITOP_MASK_RXINTR (0x1UL << 7) | |
227 | #define ITOP_MASK_TXINTR (0x1UL << 8) | |
228 | #define ITOP_MASK_INTR (0x1UL << 9) | |
229 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) | |
230 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) | |
231 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) | |
232 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) | |
233 | ||
234 | /* | |
235 | * SSP Test Data Register - SSP_TDR | |
236 | */ | |
556f4aeb | 237 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
b43d65f7 LW |
238 | |
239 | /* | |
240 | * Message State | |
241 | * we use the spi_message.state (void *) pointer to | |
242 | * hold a single state value, that's why all this | |
243 | * (void *) casting is done here. | |
244 | */ | |
556f4aeb LW |
245 | #define STATE_START ((void *) 0) |
246 | #define STATE_RUNNING ((void *) 1) | |
247 | #define STATE_DONE ((void *) 2) | |
248 | #define STATE_ERROR ((void *) -1) | |
b43d65f7 | 249 | |
b43d65f7 LW |
250 | /* |
251 | * SSP State - Whether Enabled or Disabled | |
252 | */ | |
556f4aeb LW |
253 | #define SSP_DISABLED (0) |
254 | #define SSP_ENABLED (1) | |
b43d65f7 LW |
255 | |
256 | /* | |
257 | * SSP DMA State - Whether DMA Enabled or Disabled | |
258 | */ | |
556f4aeb LW |
259 | #define SSP_DMA_DISABLED (0) |
260 | #define SSP_DMA_ENABLED (1) | |
b43d65f7 LW |
261 | |
262 | /* | |
263 | * SSP Clock Defaults | |
264 | */ | |
556f4aeb LW |
265 | #define SSP_DEFAULT_CLKRATE 0x2 |
266 | #define SSP_DEFAULT_PRESCALE 0x40 | |
b43d65f7 LW |
267 | |
268 | /* | |
269 | * SSP Clock Parameter ranges | |
270 | */ | |
271 | #define CPSDVR_MIN 0x02 | |
272 | #define CPSDVR_MAX 0xFE | |
273 | #define SCR_MIN 0x00 | |
274 | #define SCR_MAX 0xFF | |
275 | ||
276 | /* | |
277 | * SSP Interrupt related Macros | |
278 | */ | |
279 | #define DEFAULT_SSP_REG_IMSC 0x0UL | |
280 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC | |
281 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) | |
282 | ||
283 | #define CLEAR_ALL_INTERRUPTS 0x3 | |
284 | ||
a18c266f MT |
285 | #define SPI_POLLING_TIMEOUT 1000 |
286 | ||
b43d65f7 LW |
287 | /* |
288 | * The type of reading going on on this chip | |
289 | */ | |
290 | enum ssp_reading { | |
291 | READING_NULL, | |
292 | READING_U8, | |
293 | READING_U16, | |
294 | READING_U32 | |
295 | }; | |
296 | ||
297 | /** | |
298 | * The type of writing going on on this chip | |
299 | */ | |
300 | enum ssp_writing { | |
301 | WRITING_NULL, | |
302 | WRITING_U8, | |
303 | WRITING_U16, | |
304 | WRITING_U32 | |
305 | }; | |
306 | ||
307 | /** | |
308 | * struct vendor_data - vendor-specific config parameters | |
309 | * for PL022 derivates | |
310 | * @fifodepth: depth of FIFOs (both) | |
311 | * @max_bpw: maximum number of bits per word | |
312 | * @unidir: supports unidirection transfers | |
556f4aeb LW |
313 | * @extended_cr: 32 bit wide control register 0 with extra |
314 | * features and extra features in CR1 as found in the ST variants | |
781c7b12 | 315 | * @pl023: supports a subset of the ST extensions called "PL023" |
b43d65f7 LW |
316 | */ |
317 | struct vendor_data { | |
318 | int fifodepth; | |
319 | int max_bpw; | |
320 | bool unidir; | |
556f4aeb | 321 | bool extended_cr; |
781c7b12 | 322 | bool pl023; |
06fb01fd | 323 | bool loopback; |
b43d65f7 LW |
324 | }; |
325 | ||
326 | /** | |
327 | * struct pl022 - This is the private SSP driver data structure | |
328 | * @adev: AMBA device model hookup | |
12e8b325 LW |
329 | * @vendor: vendor data for the IP block |
330 | * @phybase: the physical memory where the SSP device resides | |
331 | * @virtbase: the virtual memory where the SSP is mapped | |
332 | * @clk: outgoing clock "SPICLK" for the SPI bus | |
b43d65f7 LW |
333 | * @master: SPI framework hookup |
334 | * @master_info: controller-specific data from machine setup | |
14af60b6 CB |
335 | * @kworker: thread struct for message pump |
336 | * @kworker_task: pointer to task for message pump kworker thread | |
337 | * @pump_messages: work struct for scheduling work to the message pump | |
12e8b325 LW |
338 | * @queue_lock: spinlock to syncronise access to message queue |
339 | * @queue: message queue | |
14af60b6 CB |
340 | * @busy: message pump is busy |
341 | * @running: message pump is running | |
b43d65f7 LW |
342 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
343 | * @cur_msg: Pointer to current spi_message being processed | |
344 | * @cur_transfer: Pointer to current spi_transfer | |
345 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | |
8b8d7191 VS |
346 | * @next_msg_cs_active: the next message in the queue has been examined |
347 | * and it was found that it uses the same chip select as the previous | |
348 | * message, so we left it active after the previous transfer, and it's | |
349 | * active already. | |
b43d65f7 LW |
350 | * @tx: current position in TX buffer to be read |
351 | * @tx_end: end position in TX buffer to be read | |
352 | * @rx: current position in RX buffer to be written | |
353 | * @rx_end: end position in RX buffer to be written | |
12e8b325 LW |
354 | * @read: the type of read currently going on |
355 | * @write: the type of write currently going on | |
356 | * @exp_fifo_level: expected FIFO level | |
357 | * @dma_rx_channel: optional channel for RX DMA | |
358 | * @dma_tx_channel: optional channel for TX DMA | |
359 | * @sgt_rx: scattertable for the RX transfer | |
360 | * @sgt_tx: scattertable for the TX transfer | |
361 | * @dummypage: a dummy page used for driving data on the bus with DMA | |
f6f46de1 RS |
362 | * @cur_cs: current chip select (gpio) |
363 | * @chipselects: list of chipselects (gpios) | |
b43d65f7 LW |
364 | */ |
365 | struct pl022 { | |
366 | struct amba_device *adev; | |
367 | struct vendor_data *vendor; | |
368 | resource_size_t phybase; | |
369 | void __iomem *virtbase; | |
370 | struct clk *clk; | |
4f5e1b37 PC |
371 | /* Two optional pin states - default & sleep */ |
372 | struct pinctrl *pinctrl; | |
373 | struct pinctrl_state *pins_default; | |
374 | struct pinctrl_state *pins_sleep; | |
b43d65f7 LW |
375 | struct spi_master *master; |
376 | struct pl022_ssp_controller *master_info; | |
ffbbdd21 | 377 | /* Message per-transfer pump */ |
b43d65f7 LW |
378 | struct tasklet_struct pump_transfers; |
379 | struct spi_message *cur_msg; | |
380 | struct spi_transfer *cur_transfer; | |
381 | struct chip_data *cur_chip; | |
8b8d7191 | 382 | bool next_msg_cs_active; |
b43d65f7 LW |
383 | void *tx; |
384 | void *tx_end; | |
385 | void *rx; | |
386 | void *rx_end; | |
387 | enum ssp_reading read; | |
388 | enum ssp_writing write; | |
fc05475f | 389 | u32 exp_fifo_level; |
083be3f0 LW |
390 | enum ssp_rx_level_trig rx_lev_trig; |
391 | enum ssp_tx_level_trig tx_lev_trig; | |
b1b6b9aa LW |
392 | /* DMA settings */ |
393 | #ifdef CONFIG_DMA_ENGINE | |
394 | struct dma_chan *dma_rx_channel; | |
395 | struct dma_chan *dma_tx_channel; | |
396 | struct sg_table sgt_rx; | |
397 | struct sg_table sgt_tx; | |
398 | char *dummypage; | |
ffbbdd21 | 399 | bool dma_running; |
b1b6b9aa | 400 | #endif |
f6f46de1 RS |
401 | int cur_cs; |
402 | int *chipselects; | |
b43d65f7 LW |
403 | }; |
404 | ||
405 | /** | |
406 | * struct chip_data - To maintain runtime state of SSP for each client chip | |
556f4aeb LW |
407 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
408 | * register is 32 bits wide rather than just 16 | |
b43d65f7 LW |
409 | * @cr1: Value of control register CR1 of SSP |
410 | * @dmacr: Value of DMA control Register of SSP | |
411 | * @cpsr: Value of Clock prescale register | |
412 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client | |
413 | * @enable_dma: Whether to enable DMA or not | |
b43d65f7 | 414 | * @read: function ptr to be used to read when doing xfer for this chip |
12e8b325 | 415 | * @write: function ptr to be used to write when doing xfer for this chip |
b43d65f7 LW |
416 | * @cs_control: chip select callback provided by chip |
417 | * @xfer_type: polling/interrupt/DMA | |
418 | * | |
419 | * Runtime state of the SSP controller, maintained per chip, | |
420 | * This would be set according to the current message that would be served | |
421 | */ | |
422 | struct chip_data { | |
556f4aeb | 423 | u32 cr0; |
b43d65f7 LW |
424 | u16 cr1; |
425 | u16 dmacr; | |
426 | u16 cpsr; | |
427 | u8 n_bytes; | |
b1b6b9aa | 428 | bool enable_dma; |
b43d65f7 LW |
429 | enum ssp_reading read; |
430 | enum ssp_writing write; | |
431 | void (*cs_control) (u32 command); | |
432 | int xfer_type; | |
433 | }; | |
434 | ||
435 | /** | |
436 | * null_cs_control - Dummy chip select function | |
437 | * @command: select/delect the chip | |
438 | * | |
439 | * If no chip select function is provided by client this is used as dummy | |
440 | * chip select | |
441 | */ | |
442 | static void null_cs_control(u32 command) | |
443 | { | |
444 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | |
445 | } | |
446 | ||
f6f46de1 RS |
447 | static void pl022_cs_control(struct pl022 *pl022, u32 command) |
448 | { | |
449 | if (gpio_is_valid(pl022->cur_cs)) | |
450 | gpio_set_value(pl022->cur_cs, command); | |
451 | else | |
452 | pl022->cur_chip->cs_control(command); | |
453 | } | |
454 | ||
b43d65f7 LW |
455 | /** |
456 | * giveback - current spi_message is over, schedule next message and call | |
457 | * callback of this message. Assumes that caller already | |
458 | * set message->status; dma and pio irqs are blocked | |
459 | * @pl022: SSP driver private data structure | |
460 | */ | |
461 | static void giveback(struct pl022 *pl022) | |
462 | { | |
463 | struct spi_transfer *last_transfer; | |
8b8d7191 | 464 | pl022->next_msg_cs_active = false; |
b43d65f7 | 465 | |
8b8d7191 | 466 | last_transfer = list_entry(pl022->cur_msg->transfers.prev, |
b43d65f7 LW |
467 | struct spi_transfer, |
468 | transfer_list); | |
469 | ||
470 | /* Delay if requested before any change in chip select */ | |
471 | if (last_transfer->delay_usecs) | |
472 | /* | |
473 | * FIXME: This runs in interrupt context. | |
474 | * Is this really smart? | |
475 | */ | |
476 | udelay(last_transfer->delay_usecs); | |
477 | ||
8b8d7191 | 478 | if (!last_transfer->cs_change) { |
b43d65f7 LW |
479 | struct spi_message *next_msg; |
480 | ||
8b8d7191 VS |
481 | /* |
482 | * cs_change was not set. We can keep the chip select | |
483 | * enabled if there is message in the queue and it is | |
484 | * for the same spi device. | |
b43d65f7 LW |
485 | * |
486 | * We cannot postpone this until pump_messages, because | |
487 | * after calling msg->complete (below) the driver that | |
488 | * sent the current message could be unloaded, which | |
489 | * could invalidate the cs_control() callback... | |
490 | */ | |
b43d65f7 | 491 | /* get a pointer to the next message, if any */ |
ffbbdd21 | 492 | next_msg = spi_get_next_queued_message(pl022->master); |
b43d65f7 | 493 | |
8b8d7191 VS |
494 | /* |
495 | * see if the next and current messages point | |
496 | * to the same spi device. | |
b43d65f7 | 497 | */ |
8b8d7191 | 498 | if (next_msg && next_msg->spi != pl022->cur_msg->spi) |
b43d65f7 | 499 | next_msg = NULL; |
8b8d7191 | 500 | if (!next_msg || pl022->cur_msg->state == STATE_ERROR) |
f6f46de1 | 501 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
8b8d7191 VS |
502 | else |
503 | pl022->next_msg_cs_active = true; | |
ffbbdd21 | 504 | |
b43d65f7 | 505 | } |
8b8d7191 | 506 | |
8b8d7191 VS |
507 | pl022->cur_msg = NULL; |
508 | pl022->cur_transfer = NULL; | |
509 | pl022->cur_chip = NULL; | |
ffbbdd21 | 510 | spi_finalize_current_message(pl022->master); |
fd316941 VS |
511 | |
512 | /* disable the SPI/SSP operation */ | |
513 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
514 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
515 | ||
b43d65f7 LW |
516 | } |
517 | ||
518 | /** | |
519 | * flush - flush the FIFO to reach a clean state | |
520 | * @pl022: SSP driver private data structure | |
521 | */ | |
522 | static int flush(struct pl022 *pl022) | |
523 | { | |
524 | unsigned long limit = loops_per_jiffy << 1; | |
525 | ||
526 | dev_dbg(&pl022->adev->dev, "flush\n"); | |
527 | do { | |
528 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
529 | readw(SSP_DR(pl022->virtbase)); | |
530 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | |
fc05475f LW |
531 | |
532 | pl022->exp_fifo_level = 0; | |
533 | ||
b43d65f7 LW |
534 | return limit; |
535 | } | |
536 | ||
537 | /** | |
538 | * restore_state - Load configuration of current chip | |
539 | * @pl022: SSP driver private data structure | |
540 | */ | |
541 | static void restore_state(struct pl022 *pl022) | |
542 | { | |
543 | struct chip_data *chip = pl022->cur_chip; | |
544 | ||
556f4aeb LW |
545 | if (pl022->vendor->extended_cr) |
546 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); | |
547 | else | |
548 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); | |
b43d65f7 LW |
549 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
550 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); | |
551 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); | |
552 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
553 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
554 | } | |
555 | ||
b43d65f7 LW |
556 | /* |
557 | * Default SSP Register Values | |
558 | */ | |
559 | #define DEFAULT_SSP_REG_CR0 ( \ | |
560 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | |
556f4aeb LW |
561 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
562 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
563 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
564 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
565 | ) | |
566 | ||
567 | /* ST versions have slightly different bit layout */ | |
568 | #define DEFAULT_SSP_REG_CR0_ST ( \ | |
569 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
570 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ | |
b43d65f7 | 571 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
ee2b805c | 572 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
556f4aeb LW |
573 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
574 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ | |
575 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ | |
b43d65f7 LW |
576 | ) |
577 | ||
781c7b12 LW |
578 | /* The PL023 version is slightly different again */ |
579 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ | |
580 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
581 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
582 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
583 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
584 | ) | |
585 | ||
b43d65f7 LW |
586 | #define DEFAULT_SSP_REG_CR1 ( \ |
587 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ | |
588 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
589 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
556f4aeb | 590 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
b43d65f7 LW |
591 | ) |
592 | ||
556f4aeb LW |
593 | /* ST versions extend this register to use all 16 bits */ |
594 | #define DEFAULT_SSP_REG_CR1_ST ( \ | |
595 | DEFAULT_SSP_REG_CR1 | \ | |
596 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
597 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
598 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ | |
599 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
600 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ | |
601 | ) | |
602 | ||
781c7b12 LW |
603 | /* |
604 | * The PL023 variant has further differences: no loopback mode, no microwire | |
605 | * support, and a new clock feedback delay setting. | |
606 | */ | |
607 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ | |
608 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
609 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
610 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ | |
611 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
612 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
613 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
614 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ | |
615 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ | |
616 | ) | |
556f4aeb | 617 | |
b43d65f7 | 618 | #define DEFAULT_SSP_REG_CPSR ( \ |
556f4aeb | 619 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
b43d65f7 LW |
620 | ) |
621 | ||
622 | #define DEFAULT_SSP_REG_DMACR (\ | |
623 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ | |
624 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ | |
625 | ) | |
626 | ||
781c7b12 LW |
627 | /** |
628 | * load_ssp_default_config - Load default configuration for SSP | |
629 | * @pl022: SSP driver private data structure | |
630 | */ | |
b43d65f7 LW |
631 | static void load_ssp_default_config(struct pl022 *pl022) |
632 | { | |
781c7b12 LW |
633 | if (pl022->vendor->pl023) { |
634 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); | |
635 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); | |
636 | } else if (pl022->vendor->extended_cr) { | |
556f4aeb LW |
637 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
638 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); | |
639 | } else { | |
640 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); | |
641 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); | |
642 | } | |
b43d65f7 LW |
643 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
644 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); | |
645 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
646 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
647 | } | |
648 | ||
649 | /** | |
650 | * This will write to TX and read from RX according to the parameters | |
651 | * set in pl022. | |
652 | */ | |
653 | static void readwriter(struct pl022 *pl022) | |
654 | { | |
655 | ||
656 | /* | |
25985edc | 657 | * The FIFO depth is different between primecell variants. |
b43d65f7 LW |
658 | * I believe filling in too much in the FIFO might cause |
659 | * errons in 8bit wide transfers on ARM variants (just 8 words | |
660 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | |
661 | * | |
fc05475f LW |
662 | * To prevent this issue, the TX FIFO is only filled to the |
663 | * unused RX FIFO fill length, regardless of what the TX | |
664 | * FIFO status flag indicates. | |
b43d65f7 LW |
665 | */ |
666 | dev_dbg(&pl022->adev->dev, | |
667 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | |
668 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); | |
669 | ||
670 | /* Read as much as you can */ | |
671 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
672 | && (pl022->rx < pl022->rx_end)) { | |
673 | switch (pl022->read) { | |
674 | case READING_NULL: | |
675 | readw(SSP_DR(pl022->virtbase)); | |
676 | break; | |
677 | case READING_U8: | |
678 | *(u8 *) (pl022->rx) = | |
679 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
680 | break; | |
681 | case READING_U16: | |
682 | *(u16 *) (pl022->rx) = | |
683 | (u16) readw(SSP_DR(pl022->virtbase)); | |
684 | break; | |
685 | case READING_U32: | |
686 | *(u32 *) (pl022->rx) = | |
687 | readl(SSP_DR(pl022->virtbase)); | |
688 | break; | |
689 | } | |
690 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 691 | pl022->exp_fifo_level--; |
b43d65f7 LW |
692 | } |
693 | /* | |
fc05475f | 694 | * Write as much as possible up to the RX FIFO size |
b43d65f7 | 695 | */ |
fc05475f | 696 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
b43d65f7 LW |
697 | && (pl022->tx < pl022->tx_end)) { |
698 | switch (pl022->write) { | |
699 | case WRITING_NULL: | |
700 | writew(0x0, SSP_DR(pl022->virtbase)); | |
701 | break; | |
702 | case WRITING_U8: | |
703 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
704 | break; | |
705 | case WRITING_U16: | |
706 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); | |
707 | break; | |
708 | case WRITING_U32: | |
709 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
710 | break; | |
711 | } | |
712 | pl022->tx += (pl022->cur_chip->n_bytes); | |
fc05475f | 713 | pl022->exp_fifo_level++; |
b43d65f7 LW |
714 | /* |
715 | * This inner reader takes care of things appearing in the RX | |
716 | * FIFO as we're transmitting. This will happen a lot since the | |
717 | * clock starts running when you put things into the TX FIFO, | |
25985edc | 718 | * and then things are continuously clocked into the RX FIFO. |
b43d65f7 LW |
719 | */ |
720 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
721 | && (pl022->rx < pl022->rx_end)) { | |
722 | switch (pl022->read) { | |
723 | case READING_NULL: | |
724 | readw(SSP_DR(pl022->virtbase)); | |
725 | break; | |
726 | case READING_U8: | |
727 | *(u8 *) (pl022->rx) = | |
728 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
729 | break; | |
730 | case READING_U16: | |
731 | *(u16 *) (pl022->rx) = | |
732 | (u16) readw(SSP_DR(pl022->virtbase)); | |
733 | break; | |
734 | case READING_U32: | |
735 | *(u32 *) (pl022->rx) = | |
736 | readl(SSP_DR(pl022->virtbase)); | |
737 | break; | |
738 | } | |
739 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 740 | pl022->exp_fifo_level--; |
b43d65f7 LW |
741 | } |
742 | } | |
743 | /* | |
744 | * When we exit here the TX FIFO should be full and the RX FIFO | |
745 | * should be empty | |
746 | */ | |
747 | } | |
748 | ||
b43d65f7 LW |
749 | /** |
750 | * next_transfer - Move to the Next transfer in the current spi message | |
751 | * @pl022: SSP driver private data structure | |
752 | * | |
753 | * This function moves though the linked list of spi transfers in the | |
754 | * current spi message and returns with the state of current spi | |
755 | * message i.e whether its last transfer is done(STATE_DONE) or | |
756 | * Next transfer is ready(STATE_RUNNING) | |
757 | */ | |
758 | static void *next_transfer(struct pl022 *pl022) | |
759 | { | |
760 | struct spi_message *msg = pl022->cur_msg; | |
761 | struct spi_transfer *trans = pl022->cur_transfer; | |
762 | ||
763 | /* Move to next transfer */ | |
764 | if (trans->transfer_list.next != &msg->transfers) { | |
765 | pl022->cur_transfer = | |
766 | list_entry(trans->transfer_list.next, | |
767 | struct spi_transfer, transfer_list); | |
768 | return STATE_RUNNING; | |
769 | } | |
770 | return STATE_DONE; | |
771 | } | |
b1b6b9aa LW |
772 | |
773 | /* | |
774 | * This DMA functionality is only compiled in if we have | |
775 | * access to the generic DMA devices/DMA engine. | |
776 | */ | |
777 | #ifdef CONFIG_DMA_ENGINE | |
778 | static void unmap_free_dma_scatter(struct pl022 *pl022) | |
779 | { | |
780 | /* Unmap and free the SG tables */ | |
b7298896 | 781 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 782 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
b7298896 | 783 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
784 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
785 | sg_free_table(&pl022->sgt_rx); | |
786 | sg_free_table(&pl022->sgt_tx); | |
787 | } | |
788 | ||
789 | static void dma_callback(void *data) | |
790 | { | |
791 | struct pl022 *pl022 = data; | |
792 | struct spi_message *msg = pl022->cur_msg; | |
793 | ||
794 | BUG_ON(!pl022->sgt_rx.sgl); | |
795 | ||
796 | #ifdef VERBOSE_DEBUG | |
797 | /* | |
798 | * Optionally dump out buffers to inspect contents, this is | |
799 | * good if you want to convince yourself that the loopback | |
800 | * read/write contents are the same, when adopting to a new | |
801 | * DMA engine. | |
802 | */ | |
803 | { | |
804 | struct scatterlist *sg; | |
805 | unsigned int i; | |
806 | ||
807 | dma_sync_sg_for_cpu(&pl022->adev->dev, | |
808 | pl022->sgt_rx.sgl, | |
809 | pl022->sgt_rx.nents, | |
810 | DMA_FROM_DEVICE); | |
811 | ||
812 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { | |
813 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); | |
814 | print_hex_dump(KERN_ERR, "SPI RX: ", | |
815 | DUMP_PREFIX_OFFSET, | |
816 | 16, | |
817 | 1, | |
818 | sg_virt(sg), | |
819 | sg_dma_len(sg), | |
820 | 1); | |
821 | } | |
822 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { | |
823 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); | |
824 | print_hex_dump(KERN_ERR, "SPI TX: ", | |
825 | DUMP_PREFIX_OFFSET, | |
826 | 16, | |
827 | 1, | |
828 | sg_virt(sg), | |
829 | sg_dma_len(sg), | |
830 | 1); | |
831 | } | |
832 | } | |
833 | #endif | |
834 | ||
835 | unmap_free_dma_scatter(pl022); | |
836 | ||
25985edc | 837 | /* Update total bytes transferred */ |
b1b6b9aa LW |
838 | msg->actual_length += pl022->cur_transfer->len; |
839 | if (pl022->cur_transfer->cs_change) | |
f6f46de1 | 840 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
b1b6b9aa LW |
841 | |
842 | /* Move to next transfer */ | |
843 | msg->state = next_transfer(pl022); | |
844 | tasklet_schedule(&pl022->pump_transfers); | |
845 | } | |
846 | ||
847 | static void setup_dma_scatter(struct pl022 *pl022, | |
848 | void *buffer, | |
849 | unsigned int length, | |
850 | struct sg_table *sgtab) | |
851 | { | |
852 | struct scatterlist *sg; | |
853 | int bytesleft = length; | |
854 | void *bufp = buffer; | |
855 | int mapbytes; | |
856 | int i; | |
857 | ||
858 | if (buffer) { | |
859 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
860 | /* | |
861 | * If there are less bytes left than what fits | |
862 | * in the current page (plus page alignment offset) | |
863 | * we just feed in this, else we stuff in as much | |
864 | * as we can. | |
865 | */ | |
866 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) | |
867 | mapbytes = bytesleft; | |
868 | else | |
869 | mapbytes = PAGE_SIZE - offset_in_page(bufp); | |
870 | sg_set_page(sg, virt_to_page(bufp), | |
871 | mapbytes, offset_in_page(bufp)); | |
872 | bufp += mapbytes; | |
873 | bytesleft -= mapbytes; | |
874 | dev_dbg(&pl022->adev->dev, | |
875 | "set RX/TX target page @ %p, %d bytes, %d left\n", | |
876 | bufp, mapbytes, bytesleft); | |
877 | } | |
878 | } else { | |
879 | /* Map the dummy buffer on every page */ | |
880 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
881 | if (bytesleft < PAGE_SIZE) | |
882 | mapbytes = bytesleft; | |
883 | else | |
884 | mapbytes = PAGE_SIZE; | |
885 | sg_set_page(sg, virt_to_page(pl022->dummypage), | |
886 | mapbytes, 0); | |
887 | bytesleft -= mapbytes; | |
888 | dev_dbg(&pl022->adev->dev, | |
889 | "set RX/TX to dummy page %d bytes, %d left\n", | |
890 | mapbytes, bytesleft); | |
891 | ||
892 | } | |
893 | } | |
894 | BUG_ON(bytesleft); | |
895 | } | |
896 | ||
897 | /** | |
898 | * configure_dma - configures the channels for the next transfer | |
899 | * @pl022: SSP driver's private data structure | |
900 | */ | |
901 | static int configure_dma(struct pl022 *pl022) | |
902 | { | |
903 | struct dma_slave_config rx_conf = { | |
904 | .src_addr = SSP_DR(pl022->phybase), | |
a485df4b | 905 | .direction = DMA_DEV_TO_MEM, |
258aea76 | 906 | .device_fc = false, |
b1b6b9aa LW |
907 | }; |
908 | struct dma_slave_config tx_conf = { | |
909 | .dst_addr = SSP_DR(pl022->phybase), | |
a485df4b | 910 | .direction = DMA_MEM_TO_DEV, |
258aea76 | 911 | .device_fc = false, |
b1b6b9aa LW |
912 | }; |
913 | unsigned int pages; | |
914 | int ret; | |
082086f2 | 915 | int rx_sglen, tx_sglen; |
b1b6b9aa LW |
916 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
917 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
918 | struct dma_async_tx_descriptor *rxdesc; | |
919 | struct dma_async_tx_descriptor *txdesc; | |
b1b6b9aa LW |
920 | |
921 | /* Check that the channels are available */ | |
922 | if (!rxchan || !txchan) | |
923 | return -ENODEV; | |
924 | ||
083be3f0 LW |
925 | /* |
926 | * If supplied, the DMA burstsize should equal the FIFO trigger level. | |
927 | * Notice that the DMA engine uses one-to-one mapping. Since we can | |
928 | * not trigger on 2 elements this needs explicit mapping rather than | |
929 | * calculation. | |
930 | */ | |
931 | switch (pl022->rx_lev_trig) { | |
932 | case SSP_RX_1_OR_MORE_ELEM: | |
933 | rx_conf.src_maxburst = 1; | |
934 | break; | |
935 | case SSP_RX_4_OR_MORE_ELEM: | |
936 | rx_conf.src_maxburst = 4; | |
937 | break; | |
938 | case SSP_RX_8_OR_MORE_ELEM: | |
939 | rx_conf.src_maxburst = 8; | |
940 | break; | |
941 | case SSP_RX_16_OR_MORE_ELEM: | |
942 | rx_conf.src_maxburst = 16; | |
943 | break; | |
944 | case SSP_RX_32_OR_MORE_ELEM: | |
945 | rx_conf.src_maxburst = 32; | |
946 | break; | |
947 | default: | |
948 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; | |
949 | break; | |
950 | } | |
951 | ||
952 | switch (pl022->tx_lev_trig) { | |
953 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
954 | tx_conf.dst_maxburst = 1; | |
955 | break; | |
956 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
957 | tx_conf.dst_maxburst = 4; | |
958 | break; | |
959 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
960 | tx_conf.dst_maxburst = 8; | |
961 | break; | |
962 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
963 | tx_conf.dst_maxburst = 16; | |
964 | break; | |
965 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
966 | tx_conf.dst_maxburst = 32; | |
967 | break; | |
968 | default: | |
969 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; | |
970 | break; | |
971 | } | |
972 | ||
b1b6b9aa LW |
973 | switch (pl022->read) { |
974 | case READING_NULL: | |
975 | /* Use the same as for writing */ | |
976 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
977 | break; | |
978 | case READING_U8: | |
979 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
980 | break; | |
981 | case READING_U16: | |
982 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
983 | break; | |
984 | case READING_U32: | |
985 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
986 | break; | |
987 | } | |
988 | ||
989 | switch (pl022->write) { | |
990 | case WRITING_NULL: | |
991 | /* Use the same as for reading */ | |
992 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
993 | break; | |
994 | case WRITING_U8: | |
995 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
996 | break; | |
997 | case WRITING_U16: | |
998 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
999 | break; | |
1000 | case WRITING_U32: | |
bc3f67a3 | 1001 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
b1b6b9aa LW |
1002 | break; |
1003 | } | |
1004 | ||
1005 | /* SPI pecularity: we need to read and write the same width */ | |
1006 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1007 | rx_conf.src_addr_width = tx_conf.dst_addr_width; | |
1008 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
1009 | tx_conf.dst_addr_width = rx_conf.src_addr_width; | |
1010 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); | |
1011 | ||
ecd442fd LW |
1012 | dmaengine_slave_config(rxchan, &rx_conf); |
1013 | dmaengine_slave_config(txchan, &tx_conf); | |
b1b6b9aa LW |
1014 | |
1015 | /* Create sglists for the transfers */ | |
b181565e | 1016 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); |
b1b6b9aa LW |
1017 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
1018 | ||
538a18dc | 1019 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1020 | if (ret) |
1021 | goto err_alloc_rx_sg; | |
1022 | ||
538a18dc | 1023 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); |
b1b6b9aa LW |
1024 | if (ret) |
1025 | goto err_alloc_tx_sg; | |
1026 | ||
1027 | /* Fill in the scatterlists for the RX+TX buffers */ | |
1028 | setup_dma_scatter(pl022, pl022->rx, | |
1029 | pl022->cur_transfer->len, &pl022->sgt_rx); | |
1030 | setup_dma_scatter(pl022, pl022->tx, | |
1031 | pl022->cur_transfer->len, &pl022->sgt_tx); | |
1032 | ||
1033 | /* Map DMA buffers */ | |
082086f2 | 1034 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa | 1035 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
082086f2 | 1036 | if (!rx_sglen) |
b1b6b9aa LW |
1037 | goto err_rx_sgmap; |
1038 | ||
082086f2 | 1039 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 1040 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
082086f2 | 1041 | if (!tx_sglen) |
b1b6b9aa LW |
1042 | goto err_tx_sgmap; |
1043 | ||
1044 | /* Send both scatterlists */ | |
16052827 | 1045 | rxdesc = dmaengine_prep_slave_sg(rxchan, |
b1b6b9aa | 1046 | pl022->sgt_rx.sgl, |
082086f2 | 1047 | rx_sglen, |
a485df4b | 1048 | DMA_DEV_TO_MEM, |
b1b6b9aa LW |
1049 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1050 | if (!rxdesc) | |
1051 | goto err_rxdesc; | |
1052 | ||
16052827 | 1053 | txdesc = dmaengine_prep_slave_sg(txchan, |
b1b6b9aa | 1054 | pl022->sgt_tx.sgl, |
082086f2 | 1055 | tx_sglen, |
a485df4b | 1056 | DMA_MEM_TO_DEV, |
b1b6b9aa LW |
1057 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1058 | if (!txdesc) | |
1059 | goto err_txdesc; | |
1060 | ||
1061 | /* Put the callback on the RX transfer only, that should finish last */ | |
1062 | rxdesc->callback = dma_callback; | |
1063 | rxdesc->callback_param = pl022; | |
1064 | ||
1065 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
ecd442fd LW |
1066 | dmaengine_submit(rxdesc); |
1067 | dmaengine_submit(txdesc); | |
1068 | dma_async_issue_pending(rxchan); | |
1069 | dma_async_issue_pending(txchan); | |
ffbbdd21 | 1070 | pl022->dma_running = true; |
b1b6b9aa LW |
1071 | |
1072 | return 0; | |
1073 | ||
b1b6b9aa | 1074 | err_txdesc: |
ecd442fd | 1075 | dmaengine_terminate_all(txchan); |
b1b6b9aa | 1076 | err_rxdesc: |
ecd442fd | 1077 | dmaengine_terminate_all(rxchan); |
b7298896 | 1078 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa LW |
1079 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1080 | err_tx_sgmap: | |
b7298896 | 1081 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
1082 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
1083 | err_rx_sgmap: | |
1084 | sg_free_table(&pl022->sgt_tx); | |
1085 | err_alloc_tx_sg: | |
1086 | sg_free_table(&pl022->sgt_rx); | |
1087 | err_alloc_rx_sg: | |
1088 | return -ENOMEM; | |
1089 | } | |
1090 | ||
a5ab6291 | 1091 | static int __devinit pl022_dma_probe(struct pl022 *pl022) |
b1b6b9aa LW |
1092 | { |
1093 | dma_cap_mask_t mask; | |
1094 | ||
1095 | /* Try to acquire a generic DMA engine slave channel */ | |
1096 | dma_cap_zero(mask); | |
1097 | dma_cap_set(DMA_SLAVE, mask); | |
1098 | /* | |
1099 | * We need both RX and TX channels to do DMA, else do none | |
1100 | * of them. | |
1101 | */ | |
1102 | pl022->dma_rx_channel = dma_request_channel(mask, | |
1103 | pl022->master_info->dma_filter, | |
1104 | pl022->master_info->dma_rx_param); | |
1105 | if (!pl022->dma_rx_channel) { | |
43c64015 | 1106 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); |
b1b6b9aa LW |
1107 | goto err_no_rxchan; |
1108 | } | |
1109 | ||
1110 | pl022->dma_tx_channel = dma_request_channel(mask, | |
1111 | pl022->master_info->dma_filter, | |
1112 | pl022->master_info->dma_tx_param); | |
1113 | if (!pl022->dma_tx_channel) { | |
43c64015 | 1114 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); |
b1b6b9aa LW |
1115 | goto err_no_txchan; |
1116 | } | |
1117 | ||
1118 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
1119 | if (!pl022->dummypage) { | |
43c64015 | 1120 | dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n"); |
b1b6b9aa LW |
1121 | goto err_no_dummypage; |
1122 | } | |
1123 | ||
1124 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", | |
1125 | dma_chan_name(pl022->dma_rx_channel), | |
1126 | dma_chan_name(pl022->dma_tx_channel)); | |
1127 | ||
1128 | return 0; | |
1129 | ||
1130 | err_no_dummypage: | |
1131 | dma_release_channel(pl022->dma_tx_channel); | |
1132 | err_no_txchan: | |
1133 | dma_release_channel(pl022->dma_rx_channel); | |
1134 | pl022->dma_rx_channel = NULL; | |
1135 | err_no_rxchan: | |
43c64015 VK |
1136 | dev_err(&pl022->adev->dev, |
1137 | "Failed to work in dma mode, work without dma!\n"); | |
b1b6b9aa LW |
1138 | return -ENODEV; |
1139 | } | |
1140 | ||
1141 | static void terminate_dma(struct pl022 *pl022) | |
1142 | { | |
1143 | struct dma_chan *rxchan = pl022->dma_rx_channel; | |
1144 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
1145 | ||
ecd442fd LW |
1146 | dmaengine_terminate_all(rxchan); |
1147 | dmaengine_terminate_all(txchan); | |
b1b6b9aa | 1148 | unmap_free_dma_scatter(pl022); |
ffbbdd21 | 1149 | pl022->dma_running = false; |
b1b6b9aa LW |
1150 | } |
1151 | ||
1152 | static void pl022_dma_remove(struct pl022 *pl022) | |
1153 | { | |
ffbbdd21 | 1154 | if (pl022->dma_running) |
b1b6b9aa LW |
1155 | terminate_dma(pl022); |
1156 | if (pl022->dma_tx_channel) | |
1157 | dma_release_channel(pl022->dma_tx_channel); | |
1158 | if (pl022->dma_rx_channel) | |
1159 | dma_release_channel(pl022->dma_rx_channel); | |
1160 | kfree(pl022->dummypage); | |
1161 | } | |
1162 | ||
1163 | #else | |
1164 | static inline int configure_dma(struct pl022 *pl022) | |
1165 | { | |
1166 | return -ENODEV; | |
1167 | } | |
1168 | ||
1169 | static inline int pl022_dma_probe(struct pl022 *pl022) | |
1170 | { | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static inline void pl022_dma_remove(struct pl022 *pl022) | |
1175 | { | |
1176 | } | |
1177 | #endif | |
1178 | ||
b43d65f7 LW |
1179 | /** |
1180 | * pl022_interrupt_handler - Interrupt handler for SSP controller | |
1181 | * | |
1182 | * This function handles interrupts generated for an interrupt based transfer. | |
1183 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the | |
1184 | * current message's state as STATE_ERROR and schedule the tasklet | |
1185 | * pump_transfers which will do the postprocessing of the current message by | |
1186 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no | |
1187 | * more data, and writes data in TX FIFO till it is not full. If we complete | |
1188 | * the transfer we move to the next transfer and schedule the tasklet. | |
1189 | */ | |
1190 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |
1191 | { | |
1192 | struct pl022 *pl022 = dev_id; | |
1193 | struct spi_message *msg = pl022->cur_msg; | |
1194 | u16 irq_status = 0; | |
1195 | u16 flag = 0; | |
1196 | ||
1197 | if (unlikely(!msg)) { | |
1198 | dev_err(&pl022->adev->dev, | |
1199 | "bad message state in interrupt handler"); | |
1200 | /* Never fail */ | |
1201 | return IRQ_HANDLED; | |
1202 | } | |
1203 | ||
1204 | /* Read the Interrupt Status Register */ | |
1205 | irq_status = readw(SSP_MIS(pl022->virtbase)); | |
1206 | ||
1207 | if (unlikely(!irq_status)) | |
1208 | return IRQ_NONE; | |
1209 | ||
b1b6b9aa LW |
1210 | /* |
1211 | * This handles the FIFO interrupts, the timeout | |
1212 | * interrupts are flatly ignored, they cannot be | |
1213 | * trusted. | |
1214 | */ | |
b43d65f7 LW |
1215 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1216 | /* | |
1217 | * Overrun interrupt - bail out since our Data has been | |
1218 | * corrupted | |
1219 | */ | |
b1b6b9aa | 1220 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
b43d65f7 LW |
1221 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1222 | dev_err(&pl022->adev->dev, | |
1223 | "RXFIFO is full\n"); | |
1224 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | |
1225 | dev_err(&pl022->adev->dev, | |
1226 | "TXFIFO is full\n"); | |
1227 | ||
1228 | /* | |
1229 | * Disable and clear interrupts, disable SSP, | |
1230 | * mark message with bad status so it can be | |
1231 | * retried. | |
1232 | */ | |
1233 | writew(DISABLE_ALL_INTERRUPTS, | |
1234 | SSP_IMSC(pl022->virtbase)); | |
1235 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1236 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1237 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
1238 | msg->state = STATE_ERROR; | |
1239 | ||
1240 | /* Schedule message queue handler */ | |
1241 | tasklet_schedule(&pl022->pump_transfers); | |
1242 | return IRQ_HANDLED; | |
1243 | } | |
1244 | ||
1245 | readwriter(pl022); | |
1246 | ||
1247 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { | |
1248 | flag = 1; | |
172289df CB |
1249 | /* Disable Transmit interrupt, enable receive interrupt */ |
1250 | writew((readw(SSP_IMSC(pl022->virtbase)) & | |
1251 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, | |
b43d65f7 LW |
1252 | SSP_IMSC(pl022->virtbase)); |
1253 | } | |
1254 | ||
1255 | /* | |
1256 | * Since all transactions must write as much as shall be read, | |
1257 | * we can conclude the entire transaction once RX is complete. | |
1258 | * At this point, all TX will always be finished. | |
1259 | */ | |
1260 | if (pl022->rx >= pl022->rx_end) { | |
1261 | writew(DISABLE_ALL_INTERRUPTS, | |
1262 | SSP_IMSC(pl022->virtbase)); | |
1263 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1264 | if (unlikely(pl022->rx > pl022->rx_end)) { | |
1265 | dev_warn(&pl022->adev->dev, "read %u surplus " | |
1266 | "bytes (did you request an odd " | |
1267 | "number of bytes on a 16bit bus?)\n", | |
1268 | (u32) (pl022->rx - pl022->rx_end)); | |
1269 | } | |
25985edc | 1270 | /* Update total bytes transferred */ |
b43d65f7 LW |
1271 | msg->actual_length += pl022->cur_transfer->len; |
1272 | if (pl022->cur_transfer->cs_change) | |
f6f46de1 | 1273 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
b43d65f7 LW |
1274 | /* Move to next transfer */ |
1275 | msg->state = next_transfer(pl022); | |
1276 | tasklet_schedule(&pl022->pump_transfers); | |
1277 | return IRQ_HANDLED; | |
1278 | } | |
1279 | ||
1280 | return IRQ_HANDLED; | |
1281 | } | |
1282 | ||
1283 | /** | |
1284 | * This sets up the pointers to memory for the next message to | |
1285 | * send out on the SPI bus. | |
1286 | */ | |
1287 | static int set_up_next_transfer(struct pl022 *pl022, | |
1288 | struct spi_transfer *transfer) | |
1289 | { | |
1290 | int residue; | |
1291 | ||
1292 | /* Sanity check the message for this bus width */ | |
1293 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; | |
1294 | if (unlikely(residue != 0)) { | |
1295 | dev_err(&pl022->adev->dev, | |
1296 | "message of %u bytes to transmit but the current " | |
1297 | "chip bus has a data width of %u bytes!\n", | |
1298 | pl022->cur_transfer->len, | |
1299 | pl022->cur_chip->n_bytes); | |
1300 | dev_err(&pl022->adev->dev, "skipping this message\n"); | |
1301 | return -EIO; | |
1302 | } | |
1303 | pl022->tx = (void *)transfer->tx_buf; | |
1304 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; | |
1305 | pl022->rx = (void *)transfer->rx_buf; | |
1306 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; | |
1307 | pl022->write = | |
1308 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; | |
1309 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; | |
1310 | return 0; | |
1311 | } | |
1312 | ||
1313 | /** | |
b1b6b9aa LW |
1314 | * pump_transfers - Tasklet function which schedules next transfer |
1315 | * when running in interrupt or DMA transfer mode. | |
b43d65f7 LW |
1316 | * @data: SSP driver private data structure |
1317 | * | |
1318 | */ | |
1319 | static void pump_transfers(unsigned long data) | |
1320 | { | |
1321 | struct pl022 *pl022 = (struct pl022 *) data; | |
1322 | struct spi_message *message = NULL; | |
1323 | struct spi_transfer *transfer = NULL; | |
1324 | struct spi_transfer *previous = NULL; | |
1325 | ||
1326 | /* Get current state information */ | |
1327 | message = pl022->cur_msg; | |
1328 | transfer = pl022->cur_transfer; | |
1329 | ||
1330 | /* Handle for abort */ | |
1331 | if (message->state == STATE_ERROR) { | |
1332 | message->status = -EIO; | |
1333 | giveback(pl022); | |
1334 | return; | |
1335 | } | |
1336 | ||
1337 | /* Handle end of message */ | |
1338 | if (message->state == STATE_DONE) { | |
1339 | message->status = 0; | |
1340 | giveback(pl022); | |
1341 | return; | |
1342 | } | |
1343 | ||
1344 | /* Delay if requested at end of transfer before CS change */ | |
1345 | if (message->state == STATE_RUNNING) { | |
1346 | previous = list_entry(transfer->transfer_list.prev, | |
1347 | struct spi_transfer, | |
1348 | transfer_list); | |
1349 | if (previous->delay_usecs) | |
1350 | /* | |
1351 | * FIXME: This runs in interrupt context. | |
1352 | * Is this really smart? | |
1353 | */ | |
1354 | udelay(previous->delay_usecs); | |
1355 | ||
8b8d7191 | 1356 | /* Reselect chip select only if cs_change was requested */ |
b43d65f7 | 1357 | if (previous->cs_change) |
f6f46de1 | 1358 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1359 | } else { |
1360 | /* STATE_START */ | |
1361 | message->state = STATE_RUNNING; | |
1362 | } | |
1363 | ||
1364 | if (set_up_next_transfer(pl022, transfer)) { | |
1365 | message->state = STATE_ERROR; | |
1366 | message->status = -EIO; | |
1367 | giveback(pl022); | |
1368 | return; | |
1369 | } | |
1370 | /* Flush the FIFOs and let's go! */ | |
1371 | flush(pl022); | |
b43d65f7 | 1372 | |
b1b6b9aa LW |
1373 | if (pl022->cur_chip->enable_dma) { |
1374 | if (configure_dma(pl022)) { | |
1375 | dev_dbg(&pl022->adev->dev, | |
1376 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1377 | goto err_config_dma; | |
1378 | } | |
b43d65f7 LW |
1379 | return; |
1380 | } | |
b43d65f7 | 1381 | |
b1b6b9aa | 1382 | err_config_dma: |
172289df CB |
1383 | /* enable all interrupts except RX */ |
1384 | writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); | |
b43d65f7 LW |
1385 | } |
1386 | ||
b1b6b9aa | 1387 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
b43d65f7 | 1388 | { |
172289df CB |
1389 | /* |
1390 | * Default is to enable all interrupts except RX - | |
1391 | * this will be enabled once TX is complete | |
1392 | */ | |
1393 | u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM; | |
b43d65f7 | 1394 | |
8b8d7191 VS |
1395 | /* Enable target chip, if not already active */ |
1396 | if (!pl022->next_msg_cs_active) | |
f6f46de1 | 1397 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 | 1398 | |
b43d65f7 LW |
1399 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
1400 | /* Error path */ | |
1401 | pl022->cur_msg->state = STATE_ERROR; | |
1402 | pl022->cur_msg->status = -EIO; | |
1403 | giveback(pl022); | |
1404 | return; | |
1405 | } | |
b1b6b9aa LW |
1406 | /* If we're using DMA, set up DMA here */ |
1407 | if (pl022->cur_chip->enable_dma) { | |
1408 | /* Configure DMA transfer */ | |
1409 | if (configure_dma(pl022)) { | |
1410 | dev_dbg(&pl022->adev->dev, | |
1411 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1412 | goto err_config_dma; | |
1413 | } | |
1414 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ | |
1415 | irqflags = DISABLE_ALL_INTERRUPTS; | |
1416 | } | |
1417 | err_config_dma: | |
b43d65f7 LW |
1418 | /* Enable SSP, turn on interrupts */ |
1419 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1420 | SSP_CR1(pl022->virtbase)); | |
b1b6b9aa | 1421 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
b43d65f7 LW |
1422 | } |
1423 | ||
b1b6b9aa | 1424 | static void do_polling_transfer(struct pl022 *pl022) |
b43d65f7 | 1425 | { |
b43d65f7 LW |
1426 | struct spi_message *message = NULL; |
1427 | struct spi_transfer *transfer = NULL; | |
1428 | struct spi_transfer *previous = NULL; | |
1429 | struct chip_data *chip; | |
a18c266f | 1430 | unsigned long time, timeout; |
b43d65f7 LW |
1431 | |
1432 | chip = pl022->cur_chip; | |
1433 | message = pl022->cur_msg; | |
1434 | ||
1435 | while (message->state != STATE_DONE) { | |
1436 | /* Handle for abort */ | |
1437 | if (message->state == STATE_ERROR) | |
1438 | break; | |
1439 | transfer = pl022->cur_transfer; | |
1440 | ||
1441 | /* Delay if requested at end of transfer */ | |
1442 | if (message->state == STATE_RUNNING) { | |
1443 | previous = | |
1444 | list_entry(transfer->transfer_list.prev, | |
1445 | struct spi_transfer, transfer_list); | |
1446 | if (previous->delay_usecs) | |
1447 | udelay(previous->delay_usecs); | |
1448 | if (previous->cs_change) | |
f6f46de1 | 1449 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1450 | } else { |
1451 | /* STATE_START */ | |
1452 | message->state = STATE_RUNNING; | |
8b8d7191 | 1453 | if (!pl022->next_msg_cs_active) |
f6f46de1 | 1454 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
b43d65f7 LW |
1455 | } |
1456 | ||
1457 | /* Configuration Changing Per Transfer */ | |
1458 | if (set_up_next_transfer(pl022, transfer)) { | |
1459 | /* Error path */ | |
1460 | message->state = STATE_ERROR; | |
1461 | break; | |
1462 | } | |
1463 | /* Flush FIFOs and enable SSP */ | |
1464 | flush(pl022); | |
1465 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1466 | SSP_CR1(pl022->virtbase)); | |
1467 | ||
556f4aeb | 1468 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
a18c266f MT |
1469 | |
1470 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); | |
1471 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { | |
1472 | time = jiffies; | |
b43d65f7 | 1473 | readwriter(pl022); |
a18c266f MT |
1474 | if (time_after(time, timeout)) { |
1475 | dev_warn(&pl022->adev->dev, | |
1476 | "%s: timeout!\n", __func__); | |
1477 | message->state = STATE_ERROR; | |
1478 | goto out; | |
1479 | } | |
521999bd | 1480 | cpu_relax(); |
a18c266f | 1481 | } |
b43d65f7 | 1482 | |
25985edc | 1483 | /* Update total byte transferred */ |
b43d65f7 LW |
1484 | message->actual_length += pl022->cur_transfer->len; |
1485 | if (pl022->cur_transfer->cs_change) | |
f6f46de1 | 1486 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
b43d65f7 LW |
1487 | /* Move to next transfer */ |
1488 | message->state = next_transfer(pl022); | |
1489 | } | |
a18c266f | 1490 | out: |
b43d65f7 LW |
1491 | /* Handle end of message */ |
1492 | if (message->state == STATE_DONE) | |
1493 | message->status = 0; | |
1494 | else | |
1495 | message->status = -EIO; | |
1496 | ||
1497 | giveback(pl022); | |
1498 | return; | |
1499 | } | |
1500 | ||
ffbbdd21 LW |
1501 | static int pl022_transfer_one_message(struct spi_master *master, |
1502 | struct spi_message *msg) | |
b43d65f7 | 1503 | { |
ffbbdd21 | 1504 | struct pl022 *pl022 = spi_master_get_devdata(master); |
b43d65f7 LW |
1505 | |
1506 | /* Initial message state */ | |
ffbbdd21 LW |
1507 | pl022->cur_msg = msg; |
1508 | msg->state = STATE_START; | |
1509 | ||
1510 | pl022->cur_transfer = list_entry(msg->transfers.next, | |
1511 | struct spi_transfer, transfer_list); | |
b43d65f7 LW |
1512 | |
1513 | /* Setup the SPI using the per chip configuration */ | |
ffbbdd21 | 1514 | pl022->cur_chip = spi_get_ctldata(msg->spi); |
f6f46de1 | 1515 | pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; |
d4b6af2e | 1516 | |
b43d65f7 LW |
1517 | restore_state(pl022); |
1518 | flush(pl022); | |
1519 | ||
1520 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) | |
1521 | do_polling_transfer(pl022); | |
b43d65f7 | 1522 | else |
b1b6b9aa | 1523 | do_interrupt_dma_transfer(pl022); |
b43d65f7 LW |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
ffbbdd21 | 1528 | static int pl022_prepare_transfer_hardware(struct spi_master *master) |
b43d65f7 | 1529 | { |
ffbbdd21 | 1530 | struct pl022 *pl022 = spi_master_get_devdata(master); |
b43d65f7 | 1531 | |
ffbbdd21 LW |
1532 | /* |
1533 | * Just make sure we have all we need to run the transfer by syncing | |
1534 | * with the runtime PM framework. | |
1535 | */ | |
1536 | pm_runtime_get_sync(&pl022->adev->dev); | |
b43d65f7 LW |
1537 | return 0; |
1538 | } | |
1539 | ||
ffbbdd21 | 1540 | static int pl022_unprepare_transfer_hardware(struct spi_master *master) |
b43d65f7 | 1541 | { |
ffbbdd21 | 1542 | struct pl022 *pl022 = spi_master_get_devdata(master); |
b43d65f7 | 1543 | |
ffbbdd21 LW |
1544 | /* nothing more to do - disable spi/ssp and power off */ |
1545 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1546 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
b43d65f7 | 1547 | |
ffbbdd21 LW |
1548 | if (pl022->master_info->autosuspend_delay > 0) { |
1549 | pm_runtime_mark_last_busy(&pl022->adev->dev); | |
1550 | pm_runtime_put_autosuspend(&pl022->adev->dev); | |
1551 | } else { | |
1552 | pm_runtime_put(&pl022->adev->dev); | |
b43d65f7 LW |
1553 | } |
1554 | ||
b43d65f7 LW |
1555 | return 0; |
1556 | } | |
1557 | ||
1558 | static int verify_controller_parameters(struct pl022 *pl022, | |
f9d629c7 | 1559 | struct pl022_config_chip const *chip_info) |
b43d65f7 | 1560 | { |
b43d65f7 LW |
1561 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1562 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { | |
5a1c98be | 1563 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1564 | "interface is configured incorrectly\n"); |
1565 | return -EINVAL; | |
1566 | } | |
1567 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && | |
1568 | (!pl022->vendor->unidir)) { | |
5a1c98be | 1569 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1570 | "unidirectional mode not supported in this " |
1571 | "hardware version\n"); | |
1572 | return -EINVAL; | |
1573 | } | |
1574 | if ((chip_info->hierarchy != SSP_MASTER) | |
1575 | && (chip_info->hierarchy != SSP_SLAVE)) { | |
5a1c98be | 1576 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1577 | "hierarchy is configured incorrectly\n"); |
1578 | return -EINVAL; | |
1579 | } | |
b43d65f7 LW |
1580 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1581 | && (chip_info->com_mode != DMA_TRANSFER) | |
1582 | && (chip_info->com_mode != POLLING_TRANSFER)) { | |
5a1c98be | 1583 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1584 | "Communication mode is configured incorrectly\n"); |
1585 | return -EINVAL; | |
1586 | } | |
78b2b911 LW |
1587 | switch (chip_info->rx_lev_trig) { |
1588 | case SSP_RX_1_OR_MORE_ELEM: | |
1589 | case SSP_RX_4_OR_MORE_ELEM: | |
1590 | case SSP_RX_8_OR_MORE_ELEM: | |
1591 | /* These are always OK, all variants can handle this */ | |
1592 | break; | |
1593 | case SSP_RX_16_OR_MORE_ELEM: | |
1594 | if (pl022->vendor->fifodepth < 16) { | |
1595 | dev_err(&pl022->adev->dev, | |
1596 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1597 | return -EINVAL; | |
1598 | } | |
1599 | break; | |
1600 | case SSP_RX_32_OR_MORE_ELEM: | |
1601 | if (pl022->vendor->fifodepth < 32) { | |
1602 | dev_err(&pl022->adev->dev, | |
1603 | "RX FIFO Trigger Level is configured incorrectly\n"); | |
1604 | return -EINVAL; | |
1605 | } | |
1606 | break; | |
1607 | default: | |
5a1c98be | 1608 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1609 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1610 | return -EINVAL; | |
78b2b911 | 1611 | break; |
b43d65f7 | 1612 | } |
78b2b911 LW |
1613 | switch (chip_info->tx_lev_trig) { |
1614 | case SSP_TX_1_OR_MORE_EMPTY_LOC: | |
1615 | case SSP_TX_4_OR_MORE_EMPTY_LOC: | |
1616 | case SSP_TX_8_OR_MORE_EMPTY_LOC: | |
1617 | /* These are always OK, all variants can handle this */ | |
1618 | break; | |
1619 | case SSP_TX_16_OR_MORE_EMPTY_LOC: | |
1620 | if (pl022->vendor->fifodepth < 16) { | |
1621 | dev_err(&pl022->adev->dev, | |
1622 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | break; | |
1626 | case SSP_TX_32_OR_MORE_EMPTY_LOC: | |
1627 | if (pl022->vendor->fifodepth < 32) { | |
1628 | dev_err(&pl022->adev->dev, | |
1629 | "TX FIFO Trigger Level is configured incorrectly\n"); | |
1630 | return -EINVAL; | |
1631 | } | |
1632 | break; | |
1633 | default: | |
5a1c98be | 1634 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1635 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1636 | return -EINVAL; | |
78b2b911 | 1637 | break; |
b43d65f7 | 1638 | } |
b43d65f7 LW |
1639 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1640 | if ((chip_info->ctrl_len < SSP_BITS_4) | |
1641 | || (chip_info->ctrl_len > SSP_BITS_32)) { | |
5a1c98be | 1642 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1643 | "CTRL LEN is configured incorrectly\n"); |
1644 | return -EINVAL; | |
1645 | } | |
1646 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) | |
1647 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { | |
5a1c98be | 1648 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1649 | "Wait State is configured incorrectly\n"); |
1650 | return -EINVAL; | |
1651 | } | |
556f4aeb LW |
1652 | /* Half duplex is only available in the ST Micro version */ |
1653 | if (pl022->vendor->extended_cr) { | |
1654 | if ((chip_info->duplex != | |
1655 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
1656 | && (chip_info->duplex != | |
4a4fd471 | 1657 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
5a1c98be | 1658 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1659 | "Microwire duplex mode is configured incorrectly\n"); |
1660 | return -EINVAL; | |
4a4fd471 | 1661 | } |
556f4aeb LW |
1662 | } else { |
1663 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
5a1c98be | 1664 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1665 | "Microwire half duplex mode requested," |
1666 | " but this is only available in the" | |
1667 | " ST version of PL022\n"); | |
b43d65f7 LW |
1668 | return -EINVAL; |
1669 | } | |
1670 | } | |
b43d65f7 LW |
1671 | return 0; |
1672 | } | |
1673 | ||
0379b2a3 VK |
1674 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
1675 | { | |
1676 | return rate / (cpsdvsr * (1 + scr)); | |
1677 | } | |
1678 | ||
1679 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct | |
1680 | ssp_clock_params * clk_freq) | |
b43d65f7 LW |
1681 | { |
1682 | /* Lets calculate the frequency parameters */ | |
0379b2a3 VK |
1683 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; |
1684 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, | |
1685 | best_scr = 0, tmp, found = 0; | |
b43d65f7 LW |
1686 | |
1687 | rate = clk_get_rate(pl022->clk); | |
1688 | /* cpsdvscr = 2 & scr 0 */ | |
0379b2a3 | 1689 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); |
b43d65f7 | 1690 | /* cpsdvsr = 254 & scr = 255 */ |
0379b2a3 VK |
1691 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); |
1692 | ||
ea505bc9 VK |
1693 | if (freq > max_tclk) |
1694 | dev_warn(&pl022->adev->dev, | |
1695 | "Max speed that can be programmed is %d Hz, you requested %d\n", | |
1696 | max_tclk, freq); | |
1697 | ||
1698 | if (freq < min_tclk) { | |
b43d65f7 | 1699 | dev_err(&pl022->adev->dev, |
ea505bc9 VK |
1700 | "Requested frequency: %d Hz is less than minimum possible %d Hz\n", |
1701 | freq, min_tclk); | |
b43d65f7 LW |
1702 | return -EINVAL; |
1703 | } | |
0379b2a3 VK |
1704 | |
1705 | /* | |
1706 | * best_freq will give closest possible available rate (<= requested | |
1707 | * freq) for all values of scr & cpsdvsr. | |
1708 | */ | |
1709 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { | |
1710 | while (scr <= SCR_MAX) { | |
1711 | tmp = spi_rate(rate, cpsdvsr, scr); | |
1712 | ||
5eb806a3 VK |
1713 | if (tmp > freq) { |
1714 | /* we need lower freq */ | |
0379b2a3 | 1715 | scr++; |
5eb806a3 VK |
1716 | continue; |
1717 | } | |
1718 | ||
0379b2a3 | 1719 | /* |
5eb806a3 VK |
1720 | * If found exact value, mark found and break. |
1721 | * If found more closer value, update and break. | |
0379b2a3 | 1722 | */ |
5eb806a3 | 1723 | if (tmp > best_freq) { |
0379b2a3 VK |
1724 | best_freq = tmp; |
1725 | best_cpsdvsr = cpsdvsr; | |
1726 | best_scr = scr; | |
1727 | ||
1728 | if (tmp == freq) | |
5eb806a3 | 1729 | found = 1; |
0379b2a3 | 1730 | } |
5eb806a3 VK |
1731 | /* |
1732 | * increased scr will give lower rates, which are not | |
1733 | * required | |
1734 | */ | |
1735 | break; | |
0379b2a3 VK |
1736 | } |
1737 | cpsdvsr += 2; | |
1738 | scr = SCR_MIN; | |
1739 | } | |
1740 | ||
5eb806a3 VK |
1741 | WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", |
1742 | freq); | |
1743 | ||
0379b2a3 VK |
1744 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); |
1745 | clk_freq->scr = (u8) (best_scr & 0xFF); | |
1746 | dev_dbg(&pl022->adev->dev, | |
1747 | "SSP Target Frequency is: %u, Effective Frequency is %u\n", | |
1748 | freq, best_freq); | |
1749 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", | |
1750 | clk_freq->cpsdvsr, clk_freq->scr); | |
1751 | ||
b43d65f7 LW |
1752 | return 0; |
1753 | } | |
1754 | ||
f9d629c7 LW |
1755 | /* |
1756 | * A piece of default chip info unless the platform | |
1757 | * supplies it. | |
1758 | */ | |
1759 | static const struct pl022_config_chip pl022_default_chip_info = { | |
1760 | .com_mode = POLLING_TRANSFER, | |
1761 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | |
1762 | .hierarchy = SSP_SLAVE, | |
1763 | .slave_tx_disable = DO_NOT_DRIVE_TX, | |
1764 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | |
1765 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | |
1766 | .ctrl_len = SSP_BITS_8, | |
1767 | .wait_state = SSP_MWIRE_WAIT_ZERO, | |
1768 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | |
1769 | .cs_control = null_cs_control, | |
1770 | }; | |
1771 | ||
b43d65f7 LW |
1772 | /** |
1773 | * pl022_setup - setup function registered to SPI master framework | |
1774 | * @spi: spi device which is requesting setup | |
1775 | * | |
1776 | * This function is registered to the SPI framework for this SPI master | |
1777 | * controller. If it is the first time when setup is called by this device, | |
1778 | * this function will initialize the runtime state for this chip and save | |
1779 | * the same in the device structure. Else it will update the runtime info | |
1780 | * with the updated chip info. Nothing is really being written to the | |
1781 | * controller hardware here, that is not done until the actual transfer | |
1782 | * commence. | |
1783 | */ | |
b43d65f7 LW |
1784 | static int pl022_setup(struct spi_device *spi) |
1785 | { | |
f9d629c7 | 1786 | struct pl022_config_chip const *chip_info; |
6d3952a7 | 1787 | struct pl022_config_chip chip_info_dt; |
b43d65f7 | 1788 | struct chip_data *chip; |
c4a47843 | 1789 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; |
b43d65f7 LW |
1790 | int status = 0; |
1791 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
bde435a9 KW |
1792 | unsigned int bits = spi->bits_per_word; |
1793 | u32 tmp; | |
6d3952a7 | 1794 | struct device_node *np = spi->dev.of_node; |
b43d65f7 LW |
1795 | |
1796 | if (!spi->max_speed_hz) | |
1797 | return -EINVAL; | |
1798 | ||
1799 | /* Get controller_state if one is supplied */ | |
1800 | chip = spi_get_ctldata(spi); | |
1801 | ||
1802 | if (chip == NULL) { | |
1803 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1804 | if (!chip) { | |
1805 | dev_err(&spi->dev, | |
1806 | "cannot allocate controller state\n"); | |
1807 | return -ENOMEM; | |
1808 | } | |
1809 | dev_dbg(&spi->dev, | |
1810 | "allocated memory for controller's runtime state\n"); | |
1811 | } | |
1812 | ||
1813 | /* Get controller data if one is supplied */ | |
1814 | chip_info = spi->controller_data; | |
1815 | ||
1816 | if (chip_info == NULL) { | |
6d3952a7 RS |
1817 | if (np) { |
1818 | chip_info_dt = pl022_default_chip_info; | |
1819 | ||
1820 | chip_info_dt.hierarchy = SSP_MASTER; | |
1821 | of_property_read_u32(np, "pl022,interface", | |
1822 | &chip_info_dt.iface); | |
1823 | of_property_read_u32(np, "pl022,com-mode", | |
1824 | &chip_info_dt.com_mode); | |
1825 | of_property_read_u32(np, "pl022,rx-level-trig", | |
1826 | &chip_info_dt.rx_lev_trig); | |
1827 | of_property_read_u32(np, "pl022,tx-level-trig", | |
1828 | &chip_info_dt.tx_lev_trig); | |
1829 | of_property_read_u32(np, "pl022,ctrl-len", | |
1830 | &chip_info_dt.ctrl_len); | |
1831 | of_property_read_u32(np, "pl022,wait-state", | |
1832 | &chip_info_dt.wait_state); | |
1833 | of_property_read_u32(np, "pl022,duplex", | |
1834 | &chip_info_dt.duplex); | |
1835 | ||
1836 | chip_info = &chip_info_dt; | |
1837 | } else { | |
1838 | chip_info = &pl022_default_chip_info; | |
1839 | /* spi_board_info.controller_data not is supplied */ | |
1840 | dev_dbg(&spi->dev, | |
1841 | "using default controller_data settings\n"); | |
1842 | } | |
f9d629c7 | 1843 | } else |
b43d65f7 LW |
1844 | dev_dbg(&spi->dev, |
1845 | "using user supplied controller_data settings\n"); | |
b43d65f7 LW |
1846 | |
1847 | /* | |
1848 | * We can override with custom divisors, else we use the board | |
1849 | * frequency setting | |
1850 | */ | |
1851 | if ((0 == chip_info->clk_freq.cpsdvsr) | |
1852 | && (0 == chip_info->clk_freq.scr)) { | |
1853 | status = calculate_effective_freq(pl022, | |
1854 | spi->max_speed_hz, | |
f9d629c7 | 1855 | &clk_freq); |
b43d65f7 LW |
1856 | if (status < 0) |
1857 | goto err_config_params; | |
1858 | } else { | |
f9d629c7 LW |
1859 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1860 | if ((clk_freq.cpsdvsr % 2) != 0) | |
1861 | clk_freq.cpsdvsr = | |
1862 | clk_freq.cpsdvsr - 1; | |
b43d65f7 | 1863 | } |
f9d629c7 LW |
1864 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1865 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { | |
e3f88ae9 | 1866 | status = -EINVAL; |
f9d629c7 LW |
1867 | dev_err(&spi->dev, |
1868 | "cpsdvsr is configured incorrectly\n"); | |
1869 | goto err_config_params; | |
1870 | } | |
1871 | ||
b43d65f7 LW |
1872 | status = verify_controller_parameters(pl022, chip_info); |
1873 | if (status) { | |
1874 | dev_err(&spi->dev, "controller data is incorrect"); | |
1875 | goto err_config_params; | |
1876 | } | |
f9d629c7 | 1877 | |
083be3f0 LW |
1878 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
1879 | pl022->tx_lev_trig = chip_info->tx_lev_trig; | |
1880 | ||
b43d65f7 LW |
1881 | /* Now set controller state based on controller data */ |
1882 | chip->xfer_type = chip_info->com_mode; | |
f9d629c7 LW |
1883 | if (!chip_info->cs_control) { |
1884 | chip->cs_control = null_cs_control; | |
f6f46de1 RS |
1885 | if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) |
1886 | dev_warn(&spi->dev, | |
1887 | "invalid chip select\n"); | |
f9d629c7 LW |
1888 | } else |
1889 | chip->cs_control = chip_info->cs_control; | |
b43d65f7 | 1890 | |
eb798c64 VS |
1891 | /* Check bits per word with vendor specific range */ |
1892 | if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { | |
bde435a9 | 1893 | status = -ENOTSUPP; |
eb798c64 VS |
1894 | dev_err(&spi->dev, "illegal data size for this controller!\n"); |
1895 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", | |
1896 | pl022->vendor->max_bpw); | |
bde435a9 KW |
1897 | goto err_config_params; |
1898 | } else if (bits <= 8) { | |
1899 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | |
b43d65f7 LW |
1900 | chip->n_bytes = 1; |
1901 | chip->read = READING_U8; | |
1902 | chip->write = WRITING_U8; | |
bde435a9 | 1903 | } else if (bits <= 16) { |
b43d65f7 LW |
1904 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1905 | chip->n_bytes = 2; | |
1906 | chip->read = READING_U16; | |
1907 | chip->write = WRITING_U16; | |
1908 | } else { | |
eb798c64 VS |
1909 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
1910 | chip->n_bytes = 4; | |
1911 | chip->read = READING_U32; | |
1912 | chip->write = WRITING_U32; | |
b43d65f7 LW |
1913 | } |
1914 | ||
1915 | /* Now Initialize all register settings required for this chip */ | |
1916 | chip->cr0 = 0; | |
1917 | chip->cr1 = 0; | |
1918 | chip->dmacr = 0; | |
1919 | chip->cpsr = 0; | |
1920 | if ((chip_info->com_mode == DMA_TRANSFER) | |
1921 | && ((pl022->master_info)->enable_dma)) { | |
b1b6b9aa | 1922 | chip->enable_dma = true; |
b43d65f7 | 1923 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
b43d65f7 LW |
1924 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1925 | SSP_DMACR_MASK_RXDMAE, 0); | |
1926 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, | |
1927 | SSP_DMACR_MASK_TXDMAE, 1); | |
1928 | } else { | |
b1b6b9aa | 1929 | chip->enable_dma = false; |
b43d65f7 LW |
1930 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
1931 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1932 | SSP_DMACR_MASK_RXDMAE, 0); | |
1933 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1934 | SSP_DMACR_MASK_TXDMAE, 1); | |
1935 | } | |
1936 | ||
f9d629c7 | 1937 | chip->cpsr = clk_freq.cpsdvsr; |
b43d65f7 | 1938 | |
556f4aeb LW |
1939 | /* Special setup for the ST micro extended control registers */ |
1940 | if (pl022->vendor->extended_cr) { | |
bde435a9 KW |
1941 | u32 etx; |
1942 | ||
781c7b12 LW |
1943 | if (pl022->vendor->pl023) { |
1944 | /* These bits are only in the PL023 */ | |
1945 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, | |
1946 | SSP_CR1_MASK_FBCLKDEL_ST, 13); | |
1947 | } else { | |
1948 | /* These bits are in the PL022 but not PL023 */ | |
1949 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, | |
1950 | SSP_CR0_MASK_HALFDUP_ST, 5); | |
1951 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, | |
1952 | SSP_CR0_MASK_CSS_ST, 16); | |
1953 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
1954 | SSP_CR0_MASK_FRF_ST, 21); | |
1955 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, | |
1956 | SSP_CR1_MASK_MWAIT_ST, 6); | |
1957 | } | |
bde435a9 | 1958 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb | 1959 | SSP_CR0_MASK_DSS_ST, 0); |
bde435a9 KW |
1960 | |
1961 | if (spi->mode & SPI_LSB_FIRST) { | |
1962 | tmp = SSP_RX_LSB; | |
1963 | etx = SSP_TX_LSB; | |
1964 | } else { | |
1965 | tmp = SSP_RX_MSB; | |
1966 | etx = SSP_TX_MSB; | |
1967 | } | |
1968 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); | |
1969 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); | |
556f4aeb LW |
1970 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
1971 | SSP_CR1_MASK_RXIFLSEL_ST, 7); | |
1972 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, | |
1973 | SSP_CR1_MASK_TXIFLSEL_ST, 10); | |
1974 | } else { | |
bde435a9 | 1975 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb LW |
1976 | SSP_CR0_MASK_DSS, 0); |
1977 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
1978 | SSP_CR0_MASK_FRF, 4); | |
1979 | } | |
bde435a9 | 1980 | |
556f4aeb | 1981 | /* Stuff that is common for all versions */ |
bde435a9 KW |
1982 | if (spi->mode & SPI_CPOL) |
1983 | tmp = SSP_CLK_POL_IDLE_HIGH; | |
1984 | else | |
1985 | tmp = SSP_CLK_POL_IDLE_LOW; | |
1986 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); | |
1987 | ||
1988 | if (spi->mode & SPI_CPHA) | |
1989 | tmp = SSP_CLK_SECOND_EDGE; | |
1990 | else | |
1991 | tmp = SSP_CLK_FIRST_EDGE; | |
1992 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); | |
1993 | ||
f9d629c7 | 1994 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
781c7b12 | 1995 | /* Loopback is available on all versions except PL023 */ |
06fb01fd | 1996 | if (pl022->vendor->loopback) { |
bde435a9 KW |
1997 | if (spi->mode & SPI_LOOP) |
1998 | tmp = LOOPBACK_ENABLED; | |
1999 | else | |
2000 | tmp = LOOPBACK_DISABLED; | |
2001 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); | |
2002 | } | |
b43d65f7 LW |
2003 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
2004 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | |
f1e45f86 VK |
2005 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, |
2006 | 3); | |
b43d65f7 LW |
2007 | |
2008 | /* Save controller_state */ | |
2009 | spi_set_ctldata(spi, chip); | |
2010 | return status; | |
2011 | err_config_params: | |
bde435a9 | 2012 | spi_set_ctldata(spi, NULL); |
b43d65f7 LW |
2013 | kfree(chip); |
2014 | return status; | |
2015 | } | |
2016 | ||
2017 | /** | |
2018 | * pl022_cleanup - cleanup function registered to SPI master framework | |
2019 | * @spi: spi device which is requesting cleanup | |
2020 | * | |
2021 | * This function is registered to the SPI framework for this SPI master | |
2022 | * controller. It will free the runtime state of chip. | |
2023 | */ | |
2024 | static void pl022_cleanup(struct spi_device *spi) | |
2025 | { | |
2026 | struct chip_data *chip = spi_get_ctldata(spi); | |
2027 | ||
2028 | spi_set_ctldata(spi, NULL); | |
2029 | kfree(chip); | |
2030 | } | |
2031 | ||
b4225885 | 2032 | static int __devinit |
aa25afad | 2033 | pl022_probe(struct amba_device *adev, const struct amba_id *id) |
b43d65f7 LW |
2034 | { |
2035 | struct device *dev = &adev->dev; | |
2036 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; | |
2037 | struct spi_master *master; | |
2038 | struct pl022 *pl022 = NULL; /*Data for this driver */ | |
6d3952a7 RS |
2039 | struct device_node *np = adev->dev.of_node; |
2040 | int status = 0, i, num_cs; | |
b43d65f7 LW |
2041 | |
2042 | dev_info(&adev->dev, | |
2043 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | |
2044 | if (platform_info == NULL) { | |
2045 | dev_err(&adev->dev, "probe - no platform data supplied\n"); | |
2046 | status = -ENODEV; | |
2047 | goto err_no_pdata; | |
2048 | } | |
2049 | ||
6d3952a7 RS |
2050 | if (platform_info->num_chipselect) { |
2051 | num_cs = platform_info->num_chipselect; | |
2052 | } else if (IS_ENABLED(CONFIG_OF)) { | |
2053 | of_property_read_u32(np, "num-cs", &num_cs); | |
2054 | } else { | |
2055 | dev_err(&adev->dev, "probe: no chip select defined\n"); | |
2056 | status = -ENODEV; | |
2057 | goto err_no_pdata; | |
2058 | } | |
2059 | ||
b43d65f7 | 2060 | /* Allocate master with space for data */ |
b4b84826 | 2061 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
b43d65f7 LW |
2062 | if (master == NULL) { |
2063 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | |
2064 | status = -ENOMEM; | |
2065 | goto err_no_master; | |
2066 | } | |
2067 | ||
2068 | pl022 = spi_master_get_devdata(master); | |
2069 | pl022->master = master; | |
2070 | pl022->master_info = platform_info; | |
2071 | pl022->adev = adev; | |
2072 | pl022->vendor = id->data; | |
b4b84826 RS |
2073 | pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), |
2074 | GFP_KERNEL); | |
b43d65f7 | 2075 | |
4f5e1b37 PC |
2076 | pl022->pinctrl = devm_pinctrl_get(dev); |
2077 | if (IS_ERR(pl022->pinctrl)) { | |
2078 | status = PTR_ERR(pl022->pinctrl); | |
2079 | goto err_no_pinctrl; | |
2080 | } | |
2081 | ||
2082 | pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl, | |
2083 | PINCTRL_STATE_DEFAULT); | |
2084 | /* enable pins to be muxed in and configured */ | |
2085 | if (!IS_ERR(pl022->pins_default)) { | |
2086 | status = pinctrl_select_state(pl022->pinctrl, | |
2087 | pl022->pins_default); | |
2088 | if (status) | |
2089 | dev_err(dev, "could not set default pins\n"); | |
2090 | } else | |
2091 | dev_err(dev, "could not get default pinstate\n"); | |
2092 | ||
2093 | pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl, | |
2094 | PINCTRL_STATE_SLEEP); | |
2095 | if (IS_ERR(pl022->pins_sleep)) | |
2096 | dev_dbg(dev, "could not get sleep pinstate\n"); | |
2097 | ||
b43d65f7 LW |
2098 | /* |
2099 | * Bus Number Which has been Assigned to this SSP controller | |
2100 | * on this board | |
2101 | */ | |
2102 | master->bus_num = platform_info->bus_id; | |
6d3952a7 | 2103 | master->num_chipselect = num_cs; |
b43d65f7 LW |
2104 | master->cleanup = pl022_cleanup; |
2105 | master->setup = pl022_setup; | |
ffbbdd21 LW |
2106 | master->prepare_transfer_hardware = pl022_prepare_transfer_hardware; |
2107 | master->transfer_one_message = pl022_transfer_one_message; | |
2108 | master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; | |
2109 | master->rt = platform_info->rt; | |
6d3952a7 | 2110 | master->dev.of_node = dev->of_node; |
b43d65f7 | 2111 | |
6d3952a7 RS |
2112 | if (platform_info->num_chipselect && platform_info->chipselects) { |
2113 | for (i = 0; i < num_cs; i++) | |
f6f46de1 | 2114 | pl022->chipselects[i] = platform_info->chipselects[i]; |
6d3952a7 RS |
2115 | } else if (IS_ENABLED(CONFIG_OF)) { |
2116 | for (i = 0; i < num_cs; i++) { | |
2117 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); | |
2118 | ||
2119 | if (cs_gpio == -EPROBE_DEFER) { | |
2120 | status = -EPROBE_DEFER; | |
2121 | goto err_no_gpio; | |
2122 | } | |
2123 | ||
2124 | pl022->chipselects[i] = cs_gpio; | |
2125 | ||
2126 | if (gpio_is_valid(cs_gpio)) { | |
2127 | if (gpio_request(cs_gpio, "ssp-pl022")) | |
2128 | dev_err(&adev->dev, | |
2129 | "could not request %d gpio\n", | |
2130 | cs_gpio); | |
2131 | else if (gpio_direction_output(cs_gpio, 1)) | |
2132 | dev_err(&adev->dev, | |
2133 | "could set gpio %d as output\n", | |
2134 | cs_gpio); | |
2135 | } | |
2136 | } | |
2137 | } | |
f6f46de1 | 2138 | |
bde435a9 KW |
2139 | /* |
2140 | * Supports mode 0-3, loopback, and active low CS. Transfers are | |
2141 | * always MS bit first on the original pl022. | |
2142 | */ | |
2143 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
2144 | if (pl022->vendor->extended_cr) | |
2145 | master->mode_bits |= SPI_LSB_FIRST; | |
2146 | ||
b43d65f7 LW |
2147 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2148 | ||
2149 | status = amba_request_regions(adev, NULL); | |
2150 | if (status) | |
2151 | goto err_no_ioregion; | |
2152 | ||
b1b6b9aa | 2153 | pl022->phybase = adev->res.start; |
b43d65f7 LW |
2154 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2155 | if (pl022->virtbase == NULL) { | |
2156 | status = -ENOMEM; | |
2157 | goto err_no_ioremap; | |
2158 | } | |
2159 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", | |
2160 | adev->res.start, pl022->virtbase); | |
2161 | ||
2fb30d11 LW |
2162 | pm_runtime_enable(dev); |
2163 | pm_runtime_resume(dev); | |
2164 | ||
b43d65f7 LW |
2165 | pl022->clk = clk_get(&adev->dev, NULL); |
2166 | if (IS_ERR(pl022->clk)) { | |
2167 | status = PTR_ERR(pl022->clk); | |
2168 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | |
2169 | goto err_no_clk; | |
2170 | } | |
7ff6bcf0 RK |
2171 | |
2172 | status = clk_prepare(pl022->clk); | |
2173 | if (status) { | |
2174 | dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n"); | |
2175 | goto err_clk_prep; | |
2176 | } | |
2177 | ||
71e63e74 UH |
2178 | status = clk_enable(pl022->clk); |
2179 | if (status) { | |
2180 | dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); | |
2181 | goto err_no_clk_en; | |
2182 | } | |
2183 | ||
ffbbdd21 LW |
2184 | /* Initialize transfer pump */ |
2185 | tasklet_init(&pl022->pump_transfers, pump_transfers, | |
2186 | (unsigned long)pl022); | |
2187 | ||
b43d65f7 | 2188 | /* Disable SSP */ |
b43d65f7 LW |
2189 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2190 | SSP_CR1(pl022->virtbase)); | |
2191 | load_ssp_default_config(pl022); | |
b43d65f7 LW |
2192 | |
2193 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", | |
2194 | pl022); | |
2195 | if (status < 0) { | |
2196 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | |
2197 | goto err_no_irq; | |
2198 | } | |
b1b6b9aa LW |
2199 | |
2200 | /* Get DMA channels */ | |
2201 | if (platform_info->enable_dma) { | |
2202 | status = pl022_dma_probe(pl022); | |
2203 | if (status != 0) | |
43c64015 | 2204 | platform_info->enable_dma = 0; |
b1b6b9aa LW |
2205 | } |
2206 | ||
b43d65f7 LW |
2207 | /* Register with the SPI framework */ |
2208 | amba_set_drvdata(adev, pl022); | |
2209 | status = spi_register_master(master); | |
2210 | if (status != 0) { | |
2211 | dev_err(&adev->dev, | |
2212 | "probe - problem registering spi master\n"); | |
2213 | goto err_spi_register; | |
2214 | } | |
25985edc | 2215 | dev_dbg(dev, "probe succeeded\n"); |
92b97f0a RK |
2216 | |
2217 | /* let runtime pm put suspend */ | |
53e4acea CB |
2218 | if (platform_info->autosuspend_delay > 0) { |
2219 | dev_info(&adev->dev, | |
2220 | "will use autosuspend for runtime pm, delay %dms\n", | |
2221 | platform_info->autosuspend_delay); | |
2222 | pm_runtime_set_autosuspend_delay(dev, | |
2223 | platform_info->autosuspend_delay); | |
2224 | pm_runtime_use_autosuspend(dev); | |
2225 | pm_runtime_put_autosuspend(dev); | |
2226 | } else { | |
2227 | pm_runtime_put(dev); | |
2228 | } | |
b43d65f7 LW |
2229 | return 0; |
2230 | ||
2231 | err_spi_register: | |
3e3ea716 VK |
2232 | if (platform_info->enable_dma) |
2233 | pl022_dma_remove(pl022); | |
2234 | ||
b43d65f7 LW |
2235 | free_irq(adev->irq[0], pl022); |
2236 | err_no_irq: | |
71e63e74 UH |
2237 | clk_disable(pl022->clk); |
2238 | err_no_clk_en: | |
7ff6bcf0 RK |
2239 | clk_unprepare(pl022->clk); |
2240 | err_clk_prep: | |
b43d65f7 LW |
2241 | clk_put(pl022->clk); |
2242 | err_no_clk: | |
2243 | iounmap(pl022->virtbase); | |
2244 | err_no_ioremap: | |
2245 | amba_release_regions(adev); | |
2246 | err_no_ioregion: | |
6d3952a7 | 2247 | err_no_gpio: |
4f5e1b37 | 2248 | err_no_pinctrl: |
b43d65f7 LW |
2249 | spi_master_put(master); |
2250 | err_no_master: | |
2251 | err_no_pdata: | |
2252 | return status; | |
2253 | } | |
2254 | ||
b4225885 | 2255 | static int __devexit |
b43d65f7 LW |
2256 | pl022_remove(struct amba_device *adev) |
2257 | { | |
2258 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
50658b66 | 2259 | |
b43d65f7 LW |
2260 | if (!pl022) |
2261 | return 0; | |
2262 | ||
92b97f0a RK |
2263 | /* |
2264 | * undo pm_runtime_put() in probe. I assume that we're not | |
2265 | * accessing the primecell here. | |
2266 | */ | |
2267 | pm_runtime_get_noresume(&adev->dev); | |
2268 | ||
b43d65f7 | 2269 | load_ssp_default_config(pl022); |
3e3ea716 VK |
2270 | if (pl022->master_info->enable_dma) |
2271 | pl022_dma_remove(pl022); | |
2272 | ||
b43d65f7 LW |
2273 | free_irq(adev->irq[0], pl022); |
2274 | clk_disable(pl022->clk); | |
7ff6bcf0 | 2275 | clk_unprepare(pl022->clk); |
b43d65f7 | 2276 | clk_put(pl022->clk); |
2fb30d11 | 2277 | pm_runtime_disable(&adev->dev); |
b43d65f7 LW |
2278 | iounmap(pl022->virtbase); |
2279 | amba_release_regions(adev); | |
2280 | tasklet_disable(&pl022->pump_transfers); | |
2281 | spi_unregister_master(pl022->master); | |
b43d65f7 | 2282 | amba_set_drvdata(adev, NULL); |
b43d65f7 LW |
2283 | return 0; |
2284 | } | |
2285 | ||
92b97f0a | 2286 | #ifdef CONFIG_SUSPEND |
6cfa6279 | 2287 | static int pl022_suspend(struct device *dev) |
b43d65f7 | 2288 | { |
92b97f0a | 2289 | struct pl022 *pl022 = dev_get_drvdata(dev); |
ffbbdd21 | 2290 | int ret; |
b43d65f7 | 2291 | |
ffbbdd21 LW |
2292 | ret = spi_master_suspend(pl022->master); |
2293 | if (ret) { | |
2294 | dev_warn(dev, "cannot suspend master\n"); | |
2295 | return ret; | |
b43d65f7 LW |
2296 | } |
2297 | ||
6cfa6279 | 2298 | dev_dbg(dev, "suspended\n"); |
b43d65f7 LW |
2299 | return 0; |
2300 | } | |
2301 | ||
92b97f0a | 2302 | static int pl022_resume(struct device *dev) |
b43d65f7 | 2303 | { |
92b97f0a | 2304 | struct pl022 *pl022 = dev_get_drvdata(dev); |
ffbbdd21 | 2305 | int ret; |
b43d65f7 LW |
2306 | |
2307 | /* Start the queue running */ | |
ffbbdd21 LW |
2308 | ret = spi_master_resume(pl022->master); |
2309 | if (ret) | |
2310 | dev_err(dev, "problem starting queue (%d)\n", ret); | |
b43d65f7 | 2311 | else |
92b97f0a | 2312 | dev_dbg(dev, "resumed\n"); |
b43d65f7 | 2313 | |
ffbbdd21 | 2314 | return ret; |
b43d65f7 | 2315 | } |
b43d65f7 LW |
2316 | #endif /* CONFIG_PM */ |
2317 | ||
92b97f0a RK |
2318 | #ifdef CONFIG_PM_RUNTIME |
2319 | static int pl022_runtime_suspend(struct device *dev) | |
2320 | { | |
2321 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
4f5e1b37 | 2322 | int status = 0; |
92b97f0a RK |
2323 | |
2324 | clk_disable(pl022->clk); | |
92b97f0a | 2325 | |
4f5e1b37 PC |
2326 | /* Optionally let pins go into sleep states */ |
2327 | if (!IS_ERR(pl022->pins_sleep)) { | |
2328 | status = pinctrl_select_state(pl022->pinctrl, | |
2329 | pl022->pins_sleep); | |
2330 | if (status) | |
2331 | dev_err(dev, "could not set pins to sleep state\n"); | |
2332 | } | |
2333 | ||
92b97f0a RK |
2334 | return 0; |
2335 | } | |
2336 | ||
2337 | static int pl022_runtime_resume(struct device *dev) | |
2338 | { | |
2339 | struct pl022 *pl022 = dev_get_drvdata(dev); | |
4f5e1b37 PC |
2340 | int status = 0; |
2341 | ||
2342 | /* Optionaly enable pins to be muxed in and configured */ | |
2343 | if (!IS_ERR(pl022->pins_default)) { | |
2344 | status = pinctrl_select_state(pl022->pinctrl, | |
2345 | pl022->pins_default); | |
2346 | if (status) | |
2347 | dev_err(dev, "could not set default pins\n"); | |
2348 | } | |
92b97f0a | 2349 | |
92b97f0a RK |
2350 | clk_enable(pl022->clk); |
2351 | ||
2352 | return 0; | |
2353 | } | |
2354 | #endif | |
2355 | ||
2356 | static const struct dev_pm_ops pl022_dev_pm_ops = { | |
2357 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) | |
2358 | SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) | |
2359 | }; | |
2360 | ||
b43d65f7 LW |
2361 | static struct vendor_data vendor_arm = { |
2362 | .fifodepth = 8, | |
2363 | .max_bpw = 16, | |
2364 | .unidir = false, | |
556f4aeb | 2365 | .extended_cr = false, |
781c7b12 | 2366 | .pl023 = false, |
06fb01fd | 2367 | .loopback = true, |
b43d65f7 LW |
2368 | }; |
2369 | ||
b43d65f7 LW |
2370 | static struct vendor_data vendor_st = { |
2371 | .fifodepth = 32, | |
2372 | .max_bpw = 32, | |
2373 | .unidir = false, | |
556f4aeb | 2374 | .extended_cr = true, |
781c7b12 | 2375 | .pl023 = false, |
06fb01fd | 2376 | .loopback = true, |
781c7b12 LW |
2377 | }; |
2378 | ||
2379 | static struct vendor_data vendor_st_pl023 = { | |
2380 | .fifodepth = 32, | |
2381 | .max_bpw = 32, | |
2382 | .unidir = false, | |
2383 | .extended_cr = true, | |
2384 | .pl023 = true, | |
06fb01fd PL |
2385 | .loopback = false, |
2386 | }; | |
2387 | ||
b43d65f7 LW |
2388 | static struct amba_id pl022_ids[] = { |
2389 | { | |
2390 | /* | |
2391 | * ARM PL022 variant, this has a 16bit wide | |
2392 | * and 8 locations deep TX/RX FIFO | |
2393 | */ | |
2394 | .id = 0x00041022, | |
2395 | .mask = 0x000fffff, | |
2396 | .data = &vendor_arm, | |
2397 | }, | |
2398 | { | |
2399 | /* | |
2400 | * ST Micro derivative, this has 32bit wide | |
2401 | * and 32 locations deep TX/RX FIFO | |
2402 | */ | |
e89e04fc | 2403 | .id = 0x01080022, |
b43d65f7 LW |
2404 | .mask = 0xffffffff, |
2405 | .data = &vendor_st, | |
2406 | }, | |
781c7b12 LW |
2407 | { |
2408 | /* | |
2409 | * ST-Ericsson derivative "PL023" (this is not | |
2410 | * an official ARM number), this is a PL022 SSP block | |
2411 | * stripped to SPI mode only, it has 32bit wide | |
2412 | * and 32 locations deep TX/RX FIFO but no extended | |
2413 | * CR0/CR1 register | |
2414 | */ | |
f1e45f86 VK |
2415 | .id = 0x00080023, |
2416 | .mask = 0xffffffff, | |
2417 | .data = &vendor_st_pl023, | |
781c7b12 | 2418 | }, |
b43d65f7 LW |
2419 | { 0, 0 }, |
2420 | }; | |
2421 | ||
7eeac71b DM |
2422 | MODULE_DEVICE_TABLE(amba, pl022_ids); |
2423 | ||
b43d65f7 LW |
2424 | static struct amba_driver pl022_driver = { |
2425 | .drv = { | |
2426 | .name = "ssp-pl022", | |
92b97f0a | 2427 | .pm = &pl022_dev_pm_ops, |
b43d65f7 LW |
2428 | }, |
2429 | .id_table = pl022_ids, | |
2430 | .probe = pl022_probe, | |
b4225885 | 2431 | .remove = __devexit_p(pl022_remove), |
b43d65f7 LW |
2432 | }; |
2433 | ||
b43d65f7 LW |
2434 | static int __init pl022_init(void) |
2435 | { | |
2436 | return amba_driver_register(&pl022_driver); | |
2437 | } | |
25c8e03b | 2438 | subsys_initcall(pl022_init); |
b43d65f7 LW |
2439 | |
2440 | static void __exit pl022_exit(void) | |
2441 | { | |
2442 | amba_driver_unregister(&pl022_driver); | |
2443 | } | |
b43d65f7 LW |
2444 | module_exit(pl022_exit); |
2445 | ||
2446 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
2447 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); | |
2448 | MODULE_LICENSE("GPL"); |