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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/errno.h> | |
cbfd6a21 | 21 | #include <linux/err.h> |
e0c9905e | 22 | #include <linux/interrupt.h> |
9df461ec | 23 | #include <linux/kernel.h> |
e0c9905e | 24 | #include <linux/platform_device.h> |
8348c259 | 25 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 26 | #include <linux/spi/spi.h> |
e0c9905e | 27 | #include <linux/delay.h> |
a7bb3909 | 28 | #include <linux/gpio.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
3343b7a6 | 30 | #include <linux/clk.h> |
7d94a505 | 31 | #include <linux/pm_runtime.h> |
a3496855 | 32 | #include <linux/acpi.h> |
e0c9905e | 33 | |
cd7bed00 | 34 | #include "spi-pxa2xx.h" |
e0c9905e SS |
35 | |
36 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 37 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 38 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 39 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 40 | |
f1f640a9 VS |
41 | #define TIMOUT_DFLT 1000 |
42 | ||
b97c74bd NF |
43 | /* |
44 | * for testing SSCR1 changes that require SSP restart, basically | |
45 | * everything except the service and interrupt enables, the pxa270 developer | |
46 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
47 | * list, but the PXA255 dev man says all bits without really meaning the | |
48 | * service and interrupt enables | |
49 | */ | |
50 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 51 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
52 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
53 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
54 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
55 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 56 | |
e5262d05 WC |
57 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
58 | | QUARK_X1000_SSCR1_EFWR \ | |
59 | | QUARK_X1000_SSCR1_RFT \ | |
60 | | QUARK_X1000_SSCR1_TFT \ | |
61 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
62 | ||
a0d2642e MW |
63 | #define LPSS_RX_THRESH_DFLT 64 |
64 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
65 | #define LPSS_TX_HITHRESH_DFLT 224 | |
66 | ||
67 | /* Offset from drv_data->lpss_base */ | |
1de70612 MW |
68 | #define GENERAL_REG 0x08 |
69 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 70 | #define SSP_REG 0x0c |
a0d2642e MW |
71 | #define SPI_CS_CONTROL 0x18 |
72 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
73 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
74 | ||
75 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
76 | { | |
77 | return drv_data->ssp_type == LPSS_SSP; | |
78 | } | |
79 | ||
e5262d05 WC |
80 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
81 | { | |
82 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
83 | } | |
84 | ||
4fdb2424 WC |
85 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
86 | { | |
87 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
88 | case QUARK_X1000_SSP: |
89 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
90 | default: |
91 | return SSCR1_CHANGE_MASK; | |
92 | } | |
93 | } | |
94 | ||
95 | static u32 | |
96 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
97 | { | |
98 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
99 | case QUARK_X1000_SSP: |
100 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
101 | default: |
102 | return RX_THRESH_DFLT; | |
103 | } | |
104 | } | |
105 | ||
106 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
107 | { | |
4fdb2424 WC |
108 | u32 mask; |
109 | ||
110 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
111 | case QUARK_X1000_SSP: |
112 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
113 | break; | |
4fdb2424 WC |
114 | default: |
115 | mask = SSSR_TFL_MASK; | |
116 | break; | |
117 | } | |
118 | ||
c039dd27 | 119 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
120 | } |
121 | ||
122 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
123 | u32 *sccr1_reg) | |
124 | { | |
125 | u32 mask; | |
126 | ||
127 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
128 | case QUARK_X1000_SSP: |
129 | mask = QUARK_X1000_SSCR1_RFT; | |
130 | break; | |
4fdb2424 WC |
131 | default: |
132 | mask = SSCR1_RFT; | |
133 | break; | |
134 | } | |
135 | *sccr1_reg &= ~mask; | |
136 | } | |
137 | ||
138 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
139 | u32 *sccr1_reg, u32 threshold) | |
140 | { | |
141 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
142 | case QUARK_X1000_SSP: |
143 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
144 | break; | |
4fdb2424 WC |
145 | default: |
146 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
151 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
152 | u32 clk_div, u8 bits) | |
153 | { | |
154 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
155 | case QUARK_X1000_SSP: |
156 | return clk_div | |
157 | | QUARK_X1000_SSCR0_Motorola | |
158 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
159 | | SSCR0_SSE; | |
4fdb2424 WC |
160 | default: |
161 | return clk_div | |
162 | | SSCR0_Motorola | |
163 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
164 | | SSCR0_SSE | |
165 | | (bits > 16 ? SSCR0_EDSS : 0); | |
166 | } | |
167 | } | |
168 | ||
a0d2642e MW |
169 | /* |
170 | * Read and write LPSS SSP private registers. Caller must first check that | |
171 | * is_lpss_ssp() returns true before these can be called. | |
172 | */ | |
173 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
174 | { | |
175 | WARN_ON(!drv_data->lpss_base); | |
176 | return readl(drv_data->lpss_base + offset); | |
177 | } | |
178 | ||
179 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
180 | unsigned offset, u32 value) | |
181 | { | |
182 | WARN_ON(!drv_data->lpss_base); | |
183 | writel(value, drv_data->lpss_base + offset); | |
184 | } | |
185 | ||
186 | /* | |
187 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
188 | * @drv_data: pointer to the driver private data | |
189 | * | |
190 | * Perform LPSS SSP specific setup. This function must be called first if | |
191 | * one is going to use LPSS SSP private registers. | |
192 | */ | |
193 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
194 | { | |
195 | unsigned offset = 0x400; | |
196 | u32 value, orig; | |
197 | ||
a0d2642e MW |
198 | /* |
199 | * Perform auto-detection of the LPSS SSP private registers. They | |
200 | * can be either at 1k or 2k offset from the base address. | |
201 | */ | |
202 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
203 | ||
e61f487f | 204 | /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ |
a0d2642e MW |
205 | value = orig | SPI_CS_CONTROL_SW_MODE; |
206 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
207 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
208 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
209 | offset = 0x800; | |
210 | goto detection_done; | |
211 | } | |
212 | ||
e61f487f CCE |
213 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); |
214 | ||
215 | /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ | |
216 | value = orig & ~SPI_CS_CONTROL_SW_MODE; | |
a0d2642e MW |
217 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); |
218 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
e61f487f | 219 | if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { |
a0d2642e MW |
220 | offset = 0x800; |
221 | goto detection_done; | |
222 | } | |
223 | ||
224 | detection_done: | |
225 | /* Now set the LPSS base */ | |
226 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
227 | ||
228 | /* Enable software chip select control */ | |
229 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
230 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
231 | |
232 | /* Enable multiblock DMA transfers */ | |
1de70612 | 233 | if (drv_data->master_info->enable_dma) { |
0054e28d | 234 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
235 | |
236 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
237 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
238 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
239 | } | |
a0d2642e MW |
240 | } |
241 | ||
242 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
243 | { | |
244 | u32 value; | |
245 | ||
a0d2642e MW |
246 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); |
247 | if (enable) | |
248 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
249 | else | |
250 | value |= SPI_CS_CONTROL_CS_HIGH; | |
251 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
252 | } | |
253 | ||
a7bb3909 EM |
254 | static void cs_assert(struct driver_data *drv_data) |
255 | { | |
256 | struct chip_data *chip = drv_data->cur_chip; | |
257 | ||
2a8626a9 | 258 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 259 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
260 | return; |
261 | } | |
262 | ||
a7bb3909 EM |
263 | if (chip->cs_control) { |
264 | chip->cs_control(PXA2XX_CS_ASSERT); | |
265 | return; | |
266 | } | |
267 | ||
a0d2642e | 268 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 269 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
270 | return; |
271 | } | |
272 | ||
7566bcc7 JN |
273 | if (is_lpss_ssp(drv_data)) |
274 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
275 | } |
276 | ||
277 | static void cs_deassert(struct driver_data *drv_data) | |
278 | { | |
279 | struct chip_data *chip = drv_data->cur_chip; | |
280 | ||
2a8626a9 SAS |
281 | if (drv_data->ssp_type == CE4100_SSP) |
282 | return; | |
283 | ||
a7bb3909 | 284 | if (chip->cs_control) { |
2b2562d3 | 285 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
286 | return; |
287 | } | |
288 | ||
a0d2642e | 289 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 290 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
291 | return; |
292 | } | |
293 | ||
7566bcc7 JN |
294 | if (is_lpss_ssp(drv_data)) |
295 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
296 | } |
297 | ||
cd7bed00 | 298 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
299 | { |
300 | unsigned long limit = loops_per_jiffy << 1; | |
301 | ||
e0c9905e | 302 | do { |
c039dd27 JN |
303 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
304 | pxa2xx_spi_read(drv_data, SSDR); | |
305 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 306 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
307 | |
308 | return limit; | |
309 | } | |
310 | ||
8d94cc50 | 311 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 312 | { |
9708c121 | 313 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 314 | |
4fdb2424 | 315 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
316 | || (drv_data->tx == drv_data->tx_end)) |
317 | return 0; | |
318 | ||
c039dd27 | 319 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
320 | drv_data->tx += n_bytes; |
321 | ||
322 | return 1; | |
e0c9905e SS |
323 | } |
324 | ||
8d94cc50 | 325 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 326 | { |
9708c121 | 327 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 328 | |
c039dd27 JN |
329 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
330 | && (drv_data->rx < drv_data->rx_end)) { | |
331 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
332 | drv_data->rx += n_bytes; |
333 | } | |
8d94cc50 SS |
334 | |
335 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
336 | } |
337 | ||
8d94cc50 | 338 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 339 | { |
4fdb2424 | 340 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
341 | || (drv_data->tx == drv_data->tx_end)) |
342 | return 0; | |
343 | ||
c039dd27 | 344 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
345 | ++drv_data->tx; |
346 | ||
347 | return 1; | |
e0c9905e SS |
348 | } |
349 | ||
8d94cc50 | 350 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 351 | { |
c039dd27 JN |
352 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
353 | && (drv_data->rx < drv_data->rx_end)) { | |
354 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
355 | ++drv_data->rx; |
356 | } | |
8d94cc50 SS |
357 | |
358 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
359 | } |
360 | ||
8d94cc50 | 361 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 362 | { |
4fdb2424 | 363 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
364 | || (drv_data->tx == drv_data->tx_end)) |
365 | return 0; | |
366 | ||
c039dd27 | 367 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
368 | drv_data->tx += 2; |
369 | ||
370 | return 1; | |
e0c9905e SS |
371 | } |
372 | ||
8d94cc50 | 373 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 374 | { |
c039dd27 JN |
375 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
376 | && (drv_data->rx < drv_data->rx_end)) { | |
377 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
378 | drv_data->rx += 2; |
379 | } | |
8d94cc50 SS |
380 | |
381 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 382 | } |
8d94cc50 SS |
383 | |
384 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 385 | { |
4fdb2424 | 386 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
387 | || (drv_data->tx == drv_data->tx_end)) |
388 | return 0; | |
389 | ||
c039dd27 | 390 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
391 | drv_data->tx += 4; |
392 | ||
393 | return 1; | |
e0c9905e SS |
394 | } |
395 | ||
8d94cc50 | 396 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 397 | { |
c039dd27 JN |
398 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
399 | && (drv_data->rx < drv_data->rx_end)) { | |
400 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
401 | drv_data->rx += 4; |
402 | } | |
8d94cc50 SS |
403 | |
404 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
405 | } |
406 | ||
cd7bed00 | 407 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
408 | { |
409 | struct spi_message *msg = drv_data->cur_msg; | |
410 | struct spi_transfer *trans = drv_data->cur_transfer; | |
411 | ||
412 | /* Move to next transfer */ | |
413 | if (trans->transfer_list.next != &msg->transfers) { | |
414 | drv_data->cur_transfer = | |
415 | list_entry(trans->transfer_list.next, | |
416 | struct spi_transfer, | |
417 | transfer_list); | |
418 | return RUNNING_STATE; | |
419 | } else | |
420 | return DONE_STATE; | |
421 | } | |
422 | ||
e0c9905e | 423 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 424 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
425 | { |
426 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 427 | struct spi_message *msg; |
e0c9905e | 428 | |
5daa3ba0 SS |
429 | msg = drv_data->cur_msg; |
430 | drv_data->cur_msg = NULL; | |
431 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 432 | |
23e2c2aa | 433 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
434 | transfer_list); |
435 | ||
8423597d NF |
436 | /* Delay if requested before any change in chip select */ |
437 | if (last_transfer->delay_usecs) | |
438 | udelay(last_transfer->delay_usecs); | |
439 | ||
440 | /* Drop chip select UNLESS cs_change is true or we are returning | |
441 | * a message with an error, or next message is for another chip | |
442 | */ | |
e0c9905e | 443 | if (!last_transfer->cs_change) |
a7bb3909 | 444 | cs_deassert(drv_data); |
8423597d NF |
445 | else { |
446 | struct spi_message *next_msg; | |
447 | ||
448 | /* Holding of cs was hinted, but we need to make sure | |
449 | * the next message is for the same chip. Don't waste | |
450 | * time with the following tests unless this was hinted. | |
451 | * | |
452 | * We cannot postpone this until pump_messages, because | |
453 | * after calling msg->complete (below) the driver that | |
454 | * sent the current message could be unloaded, which | |
455 | * could invalidate the cs_control() callback... | |
456 | */ | |
457 | ||
458 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 459 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
460 | |
461 | /* see if the next and current messages point | |
462 | * to the same chip | |
463 | */ | |
464 | if (next_msg && next_msg->spi != msg->spi) | |
465 | next_msg = NULL; | |
466 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 467 | cs_deassert(drv_data); |
8423597d | 468 | } |
e0c9905e | 469 | |
a7bb3909 | 470 | drv_data->cur_chip = NULL; |
c957e8f0 | 471 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
472 | } |
473 | ||
579d3bb2 SAS |
474 | static void reset_sccr1(struct driver_data *drv_data) |
475 | { | |
579d3bb2 SAS |
476 | struct chip_data *chip = drv_data->cur_chip; |
477 | u32 sccr1_reg; | |
478 | ||
c039dd27 | 479 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
480 | sccr1_reg &= ~SSCR1_RFT; |
481 | sccr1_reg |= chip->threshold; | |
c039dd27 | 482 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
483 | } |
484 | ||
8d94cc50 | 485 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 486 | { |
8d94cc50 | 487 | /* Stop and reset SSP */ |
2a8626a9 | 488 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 489 | reset_sccr1(drv_data); |
2a8626a9 | 490 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 491 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 492 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
493 | pxa2xx_spi_write(drv_data, SSCR0, |
494 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 495 | |
8d94cc50 | 496 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 497 | |
8d94cc50 SS |
498 | drv_data->cur_msg->state = ERROR_STATE; |
499 | tasklet_schedule(&drv_data->pump_transfers); | |
500 | } | |
5daa3ba0 | 501 | |
8d94cc50 SS |
502 | static void int_transfer_complete(struct driver_data *drv_data) |
503 | { | |
8d94cc50 | 504 | /* Stop SSP */ |
2a8626a9 | 505 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 506 | reset_sccr1(drv_data); |
2a8626a9 | 507 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 508 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 509 | |
25985edc | 510 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
511 | drv_data->cur_msg->actual_length += drv_data->len - |
512 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 513 | |
8423597d NF |
514 | /* Transfer delays and chip select release are |
515 | * handled in pump_transfers or giveback | |
516 | */ | |
e0c9905e | 517 | |
8d94cc50 | 518 | /* Move to next transfer */ |
cd7bed00 | 519 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 520 | |
8d94cc50 SS |
521 | /* Schedule transfer tasklet */ |
522 | tasklet_schedule(&drv_data->pump_transfers); | |
523 | } | |
e0c9905e | 524 | |
8d94cc50 SS |
525 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
526 | { | |
c039dd27 JN |
527 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
528 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 529 | |
c039dd27 | 530 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 531 | |
8d94cc50 SS |
532 | if (irq_status & SSSR_ROR) { |
533 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
534 | return IRQ_HANDLED; | |
535 | } | |
e0c9905e | 536 | |
8d94cc50 | 537 | if (irq_status & SSSR_TINT) { |
c039dd27 | 538 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
539 | if (drv_data->read(drv_data)) { |
540 | int_transfer_complete(drv_data); | |
541 | return IRQ_HANDLED; | |
542 | } | |
543 | } | |
e0c9905e | 544 | |
8d94cc50 SS |
545 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
546 | do { | |
547 | if (drv_data->read(drv_data)) { | |
548 | int_transfer_complete(drv_data); | |
549 | return IRQ_HANDLED; | |
550 | } | |
551 | } while (drv_data->write(drv_data)); | |
e0c9905e | 552 | |
8d94cc50 SS |
553 | if (drv_data->read(drv_data)) { |
554 | int_transfer_complete(drv_data); | |
555 | return IRQ_HANDLED; | |
556 | } | |
e0c9905e | 557 | |
8d94cc50 | 558 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
559 | u32 bytes_left; |
560 | u32 sccr1_reg; | |
561 | ||
c039dd27 | 562 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
563 | sccr1_reg &= ~SSCR1_TIE; |
564 | ||
565 | /* | |
566 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 567 | * remaining RX bytes. |
579d3bb2 | 568 | */ |
2a8626a9 | 569 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 570 | u32 rx_thre; |
579d3bb2 | 571 | |
4fdb2424 | 572 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
573 | |
574 | bytes_left = drv_data->rx_end - drv_data->rx; | |
575 | switch (drv_data->n_bytes) { | |
576 | case 4: | |
577 | bytes_left >>= 1; | |
578 | case 2: | |
579 | bytes_left >>= 1; | |
8d94cc50 | 580 | } |
579d3bb2 | 581 | |
4fdb2424 WC |
582 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
583 | if (rx_thre > bytes_left) | |
584 | rx_thre = bytes_left; | |
579d3bb2 | 585 | |
4fdb2424 | 586 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 587 | } |
c039dd27 | 588 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
589 | } |
590 | ||
5daa3ba0 SS |
591 | /* We did something */ |
592 | return IRQ_HANDLED; | |
e0c9905e SS |
593 | } |
594 | ||
7d12e780 | 595 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 596 | { |
c7bec5ab | 597 | struct driver_data *drv_data = dev_id; |
7d94a505 | 598 | u32 sccr1_reg; |
49cbb1e0 SAS |
599 | u32 mask = drv_data->mask_sr; |
600 | u32 status; | |
601 | ||
7d94a505 MW |
602 | /* |
603 | * The IRQ might be shared with other peripherals so we must first | |
604 | * check that are we RPM suspended or not. If we are we assume that | |
605 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
606 | * interrupt is enabled). | |
607 | */ | |
608 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
609 | return IRQ_NONE; | |
610 | ||
269e4a41 MW |
611 | /* |
612 | * If the device is not yet in RPM suspended state and we get an | |
613 | * interrupt that is meant for another device, check if status bits | |
614 | * are all set to one. That means that the device is already | |
615 | * powered off. | |
616 | */ | |
c039dd27 | 617 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
618 | if (status == ~0) |
619 | return IRQ_NONE; | |
620 | ||
c039dd27 | 621 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
622 | |
623 | /* Ignore possible writes if we don't need to write */ | |
624 | if (!(sccr1_reg & SSCR1_TIE)) | |
625 | mask &= ~SSSR_TFS; | |
626 | ||
627 | if (!(status & mask)) | |
628 | return IRQ_NONE; | |
e0c9905e SS |
629 | |
630 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 631 | |
c039dd27 JN |
632 | pxa2xx_spi_write(drv_data, SSCR0, |
633 | pxa2xx_spi_read(drv_data, SSCR0) | |
634 | & ~SSCR0_SSE); | |
635 | pxa2xx_spi_write(drv_data, SSCR1, | |
636 | pxa2xx_spi_read(drv_data, SSCR1) | |
637 | & ~drv_data->int_cr1); | |
2a8626a9 | 638 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 639 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 640 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 641 | |
f6bd03a7 JN |
642 | dev_err(&drv_data->pdev->dev, |
643 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 644 | |
e0c9905e SS |
645 | /* Never fail */ |
646 | return IRQ_HANDLED; | |
647 | } | |
648 | ||
649 | return drv_data->transfer_handler(drv_data); | |
650 | } | |
651 | ||
e5262d05 | 652 | /* |
9df461ec AS |
653 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
654 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
655 | * | |
656 | * There are formulas to get baud rate value for given input frequency and | |
657 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
658 | * | |
659 | * Fsys = 200MHz | |
660 | * | |
661 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
662 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
663 | * | |
664 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
665 | * SCR is in range 0 .. 255 | |
666 | * | |
667 | * Divisor = 5^i * 2^j * 2 * k | |
668 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
669 | * j = [0, 23] j = 0 iff i = 1 | |
670 | * k = [1, 256] | |
671 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
672 | * | |
673 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
674 | * are: | |
675 | * Case 1: 2^n, n = [0, 23] | |
676 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
677 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
678 | * | |
679 | * In all cases the lowest possible value is better. | |
680 | * | |
681 | * The function calculates parameters for all cases and chooses the one closest | |
682 | * to the asked baud rate. | |
e5262d05 | 683 | */ |
9df461ec AS |
684 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
685 | { | |
686 | unsigned long xtal = 200000000; | |
687 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
688 | see (2) */ | |
689 | /* case 3 */ | |
690 | unsigned long fref1 = fref / 2; /* case 1 */ | |
691 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
692 | unsigned long scale; | |
693 | unsigned long q, q1, q2; | |
694 | long r, r1, r2; | |
695 | u32 mul; | |
696 | ||
697 | /* Case 1 */ | |
698 | ||
699 | /* Set initial value for DDS_CLK_RATE */ | |
700 | mul = (1 << 24) >> 1; | |
701 | ||
702 | /* Calculate initial quot */ | |
703 | q1 = DIV_ROUND_CLOSEST(fref1, rate); | |
704 | ||
705 | /* Scale q1 if it's too big */ | |
706 | if (q1 > 256) { | |
707 | /* Scale q1 to range [1, 512] */ | |
708 | scale = fls_long(q1 - 1); | |
709 | if (scale > 9) { | |
710 | q1 >>= scale - 9; | |
711 | mul >>= scale - 9; | |
e5262d05 | 712 | } |
9df461ec AS |
713 | |
714 | /* Round the result if we have a remainder */ | |
715 | q1 += q1 & 1; | |
716 | } | |
717 | ||
718 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
719 | scale = __ffs(q1); | |
720 | q1 >>= scale; | |
721 | mul >>= scale; | |
722 | ||
723 | /* Get the remainder */ | |
724 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
725 | ||
726 | /* Case 2 */ | |
727 | ||
728 | q2 = DIV_ROUND_CLOSEST(fref2, rate); | |
729 | r2 = abs(fref2 / q2 - rate); | |
730 | ||
731 | /* | |
732 | * Choose the best between two: less remainder we have the better. We | |
733 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
734 | * hold only values 0 .. 255. | |
735 | */ | |
736 | if (r2 >= r1 || q2 > 256) { | |
737 | /* case 1 is better */ | |
738 | r = r1; | |
739 | q = q1; | |
740 | } else { | |
741 | /* case 2 is better */ | |
742 | r = r2; | |
743 | q = q2; | |
744 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
745 | } |
746 | ||
9df461ec AS |
747 | /* Check case 3 only If the divisor is big enough */ |
748 | if (fref / rate >= 80) { | |
749 | u64 fssp; | |
750 | u32 m; | |
751 | ||
752 | /* Calculate initial quot */ | |
753 | q1 = DIV_ROUND_CLOSEST(fref, rate); | |
754 | m = (1 << 24) / q1; | |
755 | ||
756 | /* Get the remainder */ | |
757 | fssp = (u64)fref * m; | |
758 | do_div(fssp, 1 << 24); | |
759 | r1 = abs(fssp - rate); | |
760 | ||
761 | /* Choose this one if it suits better */ | |
762 | if (r1 < r) { | |
763 | /* case 3 is better */ | |
764 | q = 1; | |
765 | mul = m; | |
766 | } | |
767 | } | |
e5262d05 | 768 | |
9df461ec AS |
769 | *dds = mul; |
770 | return q - 1; | |
e5262d05 WC |
771 | } |
772 | ||
3343b7a6 | 773 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 774 | { |
3343b7a6 MW |
775 | unsigned long ssp_clk = drv_data->max_clk_rate; |
776 | const struct ssp_device *ssp = drv_data->ssp; | |
777 | ||
778 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 779 | |
2a8626a9 | 780 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 781 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 782 | else |
025ffe88 | 783 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 784 | } |
785 | ||
e5262d05 WC |
786 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
787 | struct chip_data *chip, int rate) | |
788 | { | |
025ffe88 | 789 | unsigned int clk_div; |
e5262d05 WC |
790 | |
791 | switch (drv_data->ssp_type) { | |
792 | case QUARK_X1000_SSP: | |
9df461ec | 793 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 794 | break; |
e5262d05 | 795 | default: |
025ffe88 | 796 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 797 | break; |
e5262d05 | 798 | } |
025ffe88 | 799 | return clk_div << 8; |
e5262d05 WC |
800 | } |
801 | ||
e0c9905e SS |
802 | static void pump_transfers(unsigned long data) |
803 | { | |
804 | struct driver_data *drv_data = (struct driver_data *)data; | |
805 | struct spi_message *message = NULL; | |
806 | struct spi_transfer *transfer = NULL; | |
807 | struct spi_transfer *previous = NULL; | |
808 | struct chip_data *chip = NULL; | |
9708c121 SS |
809 | u32 clk_div = 0; |
810 | u8 bits = 0; | |
811 | u32 speed = 0; | |
812 | u32 cr0; | |
8d94cc50 SS |
813 | u32 cr1; |
814 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
815 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 816 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
817 | |
818 | /* Get current state information */ | |
819 | message = drv_data->cur_msg; | |
820 | transfer = drv_data->cur_transfer; | |
821 | chip = drv_data->cur_chip; | |
822 | ||
823 | /* Handle for abort */ | |
824 | if (message->state == ERROR_STATE) { | |
825 | message->status = -EIO; | |
5daa3ba0 | 826 | giveback(drv_data); |
e0c9905e SS |
827 | return; |
828 | } | |
829 | ||
830 | /* Handle end of message */ | |
831 | if (message->state == DONE_STATE) { | |
832 | message->status = 0; | |
5daa3ba0 | 833 | giveback(drv_data); |
e0c9905e SS |
834 | return; |
835 | } | |
836 | ||
8423597d | 837 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
838 | if (message->state == RUNNING_STATE) { |
839 | previous = list_entry(transfer->transfer_list.prev, | |
840 | struct spi_transfer, | |
841 | transfer_list); | |
842 | if (previous->delay_usecs) | |
843 | udelay(previous->delay_usecs); | |
8423597d NF |
844 | |
845 | /* Drop chip select only if cs_change is requested */ | |
846 | if (previous->cs_change) | |
a7bb3909 | 847 | cs_deassert(drv_data); |
e0c9905e SS |
848 | } |
849 | ||
cd7bed00 MW |
850 | /* Check if we can DMA this transfer */ |
851 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
852 | |
853 | /* reject already-mapped transfers; PIO won't always work */ | |
854 | if (message->is_dma_mapped | |
855 | || transfer->rx_dma || transfer->tx_dma) { | |
856 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
857 | "pump_transfers: mapped transfer length of " |
858 | "%u is greater than %d\n", | |
7e964455 NF |
859 | transfer->len, MAX_DMA_LEN); |
860 | message->status = -EINVAL; | |
861 | giveback(drv_data); | |
862 | return; | |
863 | } | |
864 | ||
865 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
866 | dev_warn_ratelimited(&message->spi->dev, |
867 | "pump_transfers: DMA disabled for transfer length %ld " | |
868 | "greater than %d\n", | |
869 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
870 | } |
871 | ||
e0c9905e | 872 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 873 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
874 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
875 | message->status = -EIO; | |
5daa3ba0 | 876 | giveback(drv_data); |
e0c9905e SS |
877 | return; |
878 | } | |
9708c121 | 879 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
880 | drv_data->tx = (void *)transfer->tx_buf; |
881 | drv_data->tx_end = drv_data->tx + transfer->len; | |
882 | drv_data->rx = transfer->rx_buf; | |
883 | drv_data->rx_end = drv_data->rx + transfer->len; | |
884 | drv_data->rx_dma = transfer->rx_dma; | |
885 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 886 | drv_data->len = transfer->len; |
e0c9905e SS |
887 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
888 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
889 | |
890 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 891 | cr0 = chip->cr0; |
9708c121 SS |
892 | if (transfer->speed_hz || transfer->bits_per_word) { |
893 | ||
9708c121 SS |
894 | bits = chip->bits_per_word; |
895 | speed = chip->speed_hz; | |
896 | ||
897 | if (transfer->speed_hz) | |
898 | speed = transfer->speed_hz; | |
899 | ||
900 | if (transfer->bits_per_word) | |
901 | bits = transfer->bits_per_word; | |
902 | ||
e5262d05 | 903 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); |
9708c121 SS |
904 | |
905 | if (bits <= 8) { | |
906 | drv_data->n_bytes = 1; | |
9708c121 SS |
907 | drv_data->read = drv_data->read != null_reader ? |
908 | u8_reader : null_reader; | |
909 | drv_data->write = drv_data->write != null_writer ? | |
910 | u8_writer : null_writer; | |
911 | } else if (bits <= 16) { | |
912 | drv_data->n_bytes = 2; | |
9708c121 SS |
913 | drv_data->read = drv_data->read != null_reader ? |
914 | u16_reader : null_reader; | |
915 | drv_data->write = drv_data->write != null_writer ? | |
916 | u16_writer : null_writer; | |
917 | } else if (bits <= 32) { | |
918 | drv_data->n_bytes = 4; | |
9708c121 SS |
919 | drv_data->read = drv_data->read != null_reader ? |
920 | u32_reader : null_reader; | |
921 | drv_data->write = drv_data->write != null_writer ? | |
922 | u32_writer : null_writer; | |
923 | } | |
8d94cc50 SS |
924 | /* if bits/word is changed in dma mode, then must check the |
925 | * thresholds and burst also */ | |
926 | if (chip->enable_dma) { | |
cd7bed00 MW |
927 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
928 | message->spi, | |
8d94cc50 SS |
929 | bits, &dma_burst, |
930 | &dma_thresh)) | |
f6bd03a7 JN |
931 | dev_warn_ratelimited(&message->spi->dev, |
932 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 933 | } |
9708c121 | 934 | |
4fdb2424 | 935 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
9708c121 SS |
936 | } |
937 | ||
e0c9905e SS |
938 | message->state = RUNNING_STATE; |
939 | ||
7e964455 | 940 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
941 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
942 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 943 | if (drv_data->dma_mapped) { |
e0c9905e SS |
944 | |
945 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
946 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
947 | ||
948 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 949 | |
8d94cc50 SS |
950 | /* Clear status and start DMA engine */ |
951 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 952 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
953 | |
954 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
955 | } else { |
956 | /* Ensure we have the correct interrupt handler */ | |
957 | drv_data->transfer_handler = interrupt_transfer; | |
958 | ||
8d94cc50 SS |
959 | /* Clear status */ |
960 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 961 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
962 | } |
963 | ||
a0d2642e | 964 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
965 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
966 | != chip->lpss_rx_threshold) | |
967 | pxa2xx_spi_write(drv_data, SSIRF, | |
968 | chip->lpss_rx_threshold); | |
969 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
970 | != chip->lpss_tx_threshold) | |
971 | pxa2xx_spi_write(drv_data, SSITF, | |
972 | chip->lpss_tx_threshold); | |
a0d2642e MW |
973 | } |
974 | ||
e5262d05 | 975 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
976 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
977 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 978 | |
8d94cc50 | 979 | /* see if we need to reload the config registers */ |
c039dd27 JN |
980 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
981 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
982 | != (cr1 & change_mask)) { | |
b97c74bd | 983 | /* stop the SSP, and update the other bits */ |
c039dd27 | 984 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 985 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 986 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 987 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 988 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 989 | /* restart the SSP */ |
c039dd27 | 990 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 991 | |
8d94cc50 | 992 | } else { |
2a8626a9 | 993 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 994 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 995 | } |
b97c74bd | 996 | |
a7bb3909 | 997 | cs_assert(drv_data); |
b97c74bd NF |
998 | |
999 | /* after chip select, release the data by enabling service | |
1000 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1001 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1002 | } |
1003 | ||
7f86bde9 MW |
1004 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1005 | struct spi_message *msg) | |
e0c9905e | 1006 | { |
7f86bde9 | 1007 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1008 | |
7f86bde9 | 1009 | drv_data->cur_msg = msg; |
e0c9905e SS |
1010 | /* Initial message state*/ |
1011 | drv_data->cur_msg->state = START_STATE; | |
1012 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1013 | struct spi_transfer, | |
1014 | transfer_list); | |
1015 | ||
8d94cc50 SS |
1016 | /* prepare to setup the SSP, in pump_transfers, using the per |
1017 | * chip configuration */ | |
e0c9905e | 1018 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1019 | |
1020 | /* Mark as busy and launch transfers */ | |
1021 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1022 | return 0; |
1023 | } | |
1024 | ||
7d94a505 MW |
1025 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1026 | { | |
1027 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1028 | ||
1029 | /* Disable the SSP now */ | |
c039dd27 JN |
1030 | pxa2xx_spi_write(drv_data, SSCR0, |
1031 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1032 | |
7d94a505 MW |
1033 | return 0; |
1034 | } | |
1035 | ||
a7bb3909 EM |
1036 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1037 | struct pxa2xx_spi_chip *chip_info) | |
1038 | { | |
1039 | int err = 0; | |
1040 | ||
1041 | if (chip == NULL || chip_info == NULL) | |
1042 | return 0; | |
1043 | ||
1044 | /* NOTE: setup() can be called multiple times, possibly with | |
1045 | * different chip_info, release previously requested GPIO | |
1046 | */ | |
1047 | if (gpio_is_valid(chip->gpio_cs)) | |
1048 | gpio_free(chip->gpio_cs); | |
1049 | ||
1050 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1051 | if (chip_info->cs_control) { | |
1052 | chip->cs_control = chip_info->cs_control; | |
1053 | return 0; | |
1054 | } | |
1055 | ||
1056 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1057 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1058 | if (err) { | |
f6bd03a7 JN |
1059 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1060 | chip_info->gpio_cs); | |
a7bb3909 EM |
1061 | return err; |
1062 | } | |
1063 | ||
1064 | chip->gpio_cs = chip_info->gpio_cs; | |
1065 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1066 | ||
1067 | err = gpio_direction_output(chip->gpio_cs, | |
1068 | !chip->gpio_cs_inverted); | |
1069 | } | |
1070 | ||
1071 | return err; | |
1072 | } | |
1073 | ||
e0c9905e SS |
1074 | static int setup(struct spi_device *spi) |
1075 | { | |
1076 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1077 | struct chip_data *chip; | |
1078 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1079 | unsigned int clk_div; | |
a0d2642e MW |
1080 | uint tx_thres, tx_hi_thres, rx_thres; |
1081 | ||
e5262d05 WC |
1082 | switch (drv_data->ssp_type) { |
1083 | case QUARK_X1000_SSP: | |
1084 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1085 | tx_hi_thres = 0; | |
1086 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1087 | break; | |
1088 | case LPSS_SSP: | |
a0d2642e MW |
1089 | tx_thres = LPSS_TX_LOTHRESH_DFLT; |
1090 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
1091 | rx_thres = LPSS_RX_THRESH_DFLT; | |
e5262d05 WC |
1092 | break; |
1093 | default: | |
a0d2642e MW |
1094 | tx_thres = TX_THRESH_DFLT; |
1095 | tx_hi_thres = 0; | |
1096 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1097 | break; |
a0d2642e | 1098 | } |
e0c9905e | 1099 | |
8d94cc50 | 1100 | /* Only alloc on first setup */ |
e0c9905e | 1101 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1102 | if (!chip) { |
e0c9905e | 1103 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1104 | if (!chip) |
e0c9905e SS |
1105 | return -ENOMEM; |
1106 | ||
2a8626a9 SAS |
1107 | if (drv_data->ssp_type == CE4100_SSP) { |
1108 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1109 | dev_err(&spi->dev, |
1110 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1111 | kfree(chip); |
1112 | return -EINVAL; | |
1113 | } | |
1114 | ||
1115 | chip->frm = spi->chip_select; | |
1116 | } else | |
1117 | chip->gpio_cs = -1; | |
e0c9905e | 1118 | chip->enable_dma = 0; |
f1f640a9 | 1119 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1120 | } |
1121 | ||
8d94cc50 SS |
1122 | /* protocol drivers may change the chip settings, so... |
1123 | * if chip_info exists, use it */ | |
1124 | chip_info = spi->controller_data; | |
1125 | ||
e0c9905e | 1126 | /* chip_info isn't always needed */ |
8d94cc50 | 1127 | chip->cr1 = 0; |
e0c9905e | 1128 | if (chip_info) { |
f1f640a9 VS |
1129 | if (chip_info->timeout) |
1130 | chip->timeout = chip_info->timeout; | |
1131 | if (chip_info->tx_threshold) | |
1132 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1133 | if (chip_info->tx_hi_threshold) |
1134 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1135 | if (chip_info->rx_threshold) |
1136 | rx_thres = chip_info->rx_threshold; | |
1137 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1138 | chip->dma_threshold = 0; |
e0c9905e SS |
1139 | if (chip_info->enable_loopback) |
1140 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1141 | } else if (ACPI_HANDLE(&spi->dev)) { |
1142 | /* | |
1143 | * Slave devices enumerated from ACPI namespace don't | |
1144 | * usually have chip_info but we still might want to use | |
1145 | * DMA with them. | |
1146 | */ | |
1147 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1148 | } |
1149 | ||
a0d2642e MW |
1150 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1151 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1152 | | SSITF_TxHiThresh(tx_hi_thres); | |
1153 | ||
8d94cc50 SS |
1154 | /* set dma burst and threshold outside of chip_info path so that if |
1155 | * chip_info goes away after setting chip->enable_dma, the | |
1156 | * burst and threshold can still respond to changes in bits_per_word */ | |
1157 | if (chip->enable_dma) { | |
1158 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1159 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1160 | spi->bits_per_word, | |
8d94cc50 SS |
1161 | &chip->dma_burst_size, |
1162 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1163 | dev_warn(&spi->dev, |
1164 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1165 | } |
1166 | } | |
1167 | ||
e5262d05 | 1168 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); |
9708c121 | 1169 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e | 1170 | |
4fdb2424 WC |
1171 | chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, |
1172 | spi->bits_per_word); | |
e5262d05 WC |
1173 | switch (drv_data->ssp_type) { |
1174 | case QUARK_X1000_SSP: | |
1175 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1176 | & QUARK_X1000_SSCR1_RFT) | |
1177 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1178 | & QUARK_X1000_SSCR1_TFT); | |
1179 | break; | |
1180 | default: | |
1181 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1182 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1183 | break; | |
1184 | } | |
1185 | ||
7f6ee1ad JC |
1186 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1187 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1188 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1189 | |
b833172f MW |
1190 | if (spi->mode & SPI_LOOP) |
1191 | chip->cr1 |= SSCR1_LBM; | |
1192 | ||
e0c9905e | 1193 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 1194 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1195 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1196 | drv_data->max_clk_rate |
c9840daa EM |
1197 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1198 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1199 | else |
7d077197 | 1200 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1201 | drv_data->max_clk_rate / 2 |
c9840daa EM |
1202 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1203 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1204 | |
1205 | if (spi->bits_per_word <= 8) { | |
1206 | chip->n_bytes = 1; | |
e0c9905e SS |
1207 | chip->read = u8_reader; |
1208 | chip->write = u8_writer; | |
1209 | } else if (spi->bits_per_word <= 16) { | |
1210 | chip->n_bytes = 2; | |
e0c9905e SS |
1211 | chip->read = u16_reader; |
1212 | chip->write = u16_writer; | |
1213 | } else if (spi->bits_per_word <= 32) { | |
e5262d05 WC |
1214 | if (!is_quark_x1000_ssp(drv_data)) |
1215 | chip->cr0 |= SSCR0_EDSS; | |
e0c9905e | 1216 | chip->n_bytes = 4; |
e0c9905e SS |
1217 | chip->read = u32_reader; |
1218 | chip->write = u32_writer; | |
e0c9905e | 1219 | } |
9708c121 | 1220 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1221 | |
1222 | spi_set_ctldata(spi, chip); | |
1223 | ||
2a8626a9 SAS |
1224 | if (drv_data->ssp_type == CE4100_SSP) |
1225 | return 0; | |
1226 | ||
a7bb3909 | 1227 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1228 | } |
1229 | ||
0ffa0285 | 1230 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1231 | { |
0ffa0285 | 1232 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1233 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1234 | |
7348d82a DR |
1235 | if (!chip) |
1236 | return; | |
1237 | ||
2a8626a9 | 1238 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1239 | gpio_free(chip->gpio_cs); |
1240 | ||
e0c9905e SS |
1241 | kfree(chip); |
1242 | } | |
1243 | ||
a3496855 | 1244 | #ifdef CONFIG_ACPI |
a3496855 MW |
1245 | static struct pxa2xx_spi_master * |
1246 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1247 | { | |
1248 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1249 | struct acpi_device *adev; |
1250 | struct ssp_device *ssp; | |
1251 | struct resource *res; | |
1252 | int devid; | |
1253 | ||
1254 | if (!ACPI_HANDLE(&pdev->dev) || | |
1255 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1256 | return NULL; | |
1257 | ||
cc0ee987 | 1258 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1259 | if (!pdata) |
a3496855 | 1260 | return NULL; |
a3496855 MW |
1261 | |
1262 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1263 | if (!res) | |
1264 | return NULL; | |
1265 | ||
1266 | ssp = &pdata->ssp; | |
1267 | ||
1268 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1269 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1270 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1271 | return NULL; |
a3496855 MW |
1272 | |
1273 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1274 | ssp->irq = platform_get_irq(pdev, 0); | |
1275 | ssp->type = LPSS_SSP; | |
1276 | ssp->pdev = pdev; | |
1277 | ||
1278 | ssp->port_id = -1; | |
1279 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1280 | ssp->port_id = devid; | |
1281 | ||
1282 | pdata->num_chipselect = 1; | |
cddb339b | 1283 | pdata->enable_dma = true; |
a3496855 MW |
1284 | |
1285 | return pdata; | |
1286 | } | |
1287 | ||
1288 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1289 | { "INT33C0", 0 }, | |
1290 | { "INT33C1", 0 }, | |
54acbd96 MW |
1291 | { "INT3430", 0 }, |
1292 | { "INT3431", 0 }, | |
4b30f2a1 | 1293 | { "80860F0E", 0 }, |
aca26364 | 1294 | { "8086228E", 0 }, |
a3496855 MW |
1295 | { }, |
1296 | }; | |
1297 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1298 | #else | |
1299 | static inline struct pxa2xx_spi_master * | |
1300 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1301 | { | |
1302 | return NULL; | |
1303 | } | |
1304 | #endif | |
1305 | ||
fd4a319b | 1306 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1307 | { |
1308 | struct device *dev = &pdev->dev; | |
1309 | struct pxa2xx_spi_master *platform_info; | |
1310 | struct spi_master *master; | |
65a00a20 | 1311 | struct driver_data *drv_data; |
2f1a74e5 | 1312 | struct ssp_device *ssp; |
65a00a20 | 1313 | int status; |
c039dd27 | 1314 | u32 tmp; |
e0c9905e | 1315 | |
851bacf5 MW |
1316 | platform_info = dev_get_platdata(dev); |
1317 | if (!platform_info) { | |
a3496855 MW |
1318 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1319 | if (!platform_info) { | |
1320 | dev_err(&pdev->dev, "missing platform data\n"); | |
1321 | return -ENODEV; | |
1322 | } | |
851bacf5 | 1323 | } |
e0c9905e | 1324 | |
baffe169 | 1325 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1326 | if (!ssp) |
1327 | ssp = &platform_info->ssp; | |
1328 | ||
1329 | if (!ssp->mmio_base) { | |
1330 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1331 | return -ENODEV; |
1332 | } | |
1333 | ||
1334 | /* Allocate master with space for drv_data and null dma buffer */ | |
1335 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1336 | if (!master) { | |
65a00a20 | 1337 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1338 | pxa_ssp_free(ssp); |
e0c9905e SS |
1339 | return -ENOMEM; |
1340 | } | |
1341 | drv_data = spi_master_get_devdata(master); | |
1342 | drv_data->master = master; | |
1343 | drv_data->master_info = platform_info; | |
1344 | drv_data->pdev = pdev; | |
2f1a74e5 | 1345 | drv_data->ssp = ssp; |
e0c9905e | 1346 | |
21486af0 | 1347 | master->dev.parent = &pdev->dev; |
21486af0 | 1348 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1349 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1350 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1351 | |
851bacf5 | 1352 | master->bus_num = ssp->port_id; |
e0c9905e | 1353 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1354 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1355 | master->cleanup = cleanup; |
1356 | master->setup = setup; | |
7f86bde9 | 1357 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1358 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1359 | master->auto_runtime_pm = true; |
e0c9905e | 1360 | |
2f1a74e5 | 1361 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1362 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1363 | |
2f1a74e5 | 1364 | drv_data->ioaddr = ssp->mmio_base; |
1365 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1366 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1367 | switch (drv_data->ssp_type) { |
1368 | case QUARK_X1000_SSP: | |
1369 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1370 | break; | |
1371 | default: | |
1372 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1373 | break; | |
1374 | } | |
1375 | ||
e0c9905e SS |
1376 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1377 | drv_data->dma_cr1 = 0; | |
1378 | drv_data->clear_sr = SSSR_ROR; | |
1379 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1380 | } else { | |
24778be2 | 1381 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1382 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1383 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1384 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1385 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1386 | } | |
1387 | ||
49cbb1e0 SAS |
1388 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1389 | drv_data); | |
e0c9905e | 1390 | if (status < 0) { |
65a00a20 | 1391 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1392 | goto out_error_master_alloc; |
1393 | } | |
1394 | ||
1395 | /* Setup DMA if requested */ | |
1396 | drv_data->tx_channel = -1; | |
1397 | drv_data->rx_channel = -1; | |
1398 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1399 | status = pxa2xx_spi_dma_setup(drv_data); |
1400 | if (status) { | |
cddb339b | 1401 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1402 | platform_info->enable_dma = false; |
e0c9905e | 1403 | } |
e0c9905e SS |
1404 | } |
1405 | ||
1406 | /* Enable SOC clock */ | |
3343b7a6 MW |
1407 | clk_prepare_enable(ssp->clk); |
1408 | ||
1409 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1410 | |
1411 | /* Load default SSP configuration */ | |
c039dd27 | 1412 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1413 | switch (drv_data->ssp_type) { |
1414 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1415 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1416 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1417 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1418 | |
1419 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1420 | pxa2xx_spi_write(drv_data, SSCR0, |
1421 | QUARK_X1000_SSCR0_Motorola | |
1422 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1423 | break; |
1424 | default: | |
c039dd27 JN |
1425 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1426 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1427 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1428 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1429 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1430 | break; |
1431 | } | |
1432 | ||
2a8626a9 | 1433 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1434 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1435 | |
1436 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1437 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1438 | |
7566bcc7 JN |
1439 | if (is_lpss_ssp(drv_data)) |
1440 | lpss_ssp_setup(drv_data); | |
a0d2642e | 1441 | |
7f86bde9 MW |
1442 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1443 | (unsigned long)drv_data); | |
e0c9905e | 1444 | |
836d1a22 AO |
1445 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1446 | pm_runtime_use_autosuspend(&pdev->dev); | |
1447 | pm_runtime_set_active(&pdev->dev); | |
1448 | pm_runtime_enable(&pdev->dev); | |
1449 | ||
e0c9905e SS |
1450 | /* Register with the SPI framework */ |
1451 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1452 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1453 | if (status != 0) { |
1454 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1455 | goto out_error_clock_enabled; |
e0c9905e SS |
1456 | } |
1457 | ||
1458 | return status; | |
1459 | ||
e0c9905e | 1460 | out_error_clock_enabled: |
3343b7a6 | 1461 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1462 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1463 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1464 | |
1465 | out_error_master_alloc: | |
1466 | spi_master_put(master); | |
baffe169 | 1467 | pxa_ssp_free(ssp); |
e0c9905e SS |
1468 | return status; |
1469 | } | |
1470 | ||
1471 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1472 | { | |
1473 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1474 | struct ssp_device *ssp; |
e0c9905e SS |
1475 | |
1476 | if (!drv_data) | |
1477 | return 0; | |
51e911e2 | 1478 | ssp = drv_data->ssp; |
e0c9905e | 1479 | |
7d94a505 MW |
1480 | pm_runtime_get_sync(&pdev->dev); |
1481 | ||
e0c9905e | 1482 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1483 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1484 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1485 | |
1486 | /* Release DMA */ | |
cd7bed00 MW |
1487 | if (drv_data->master_info->enable_dma) |
1488 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1489 | |
7d94a505 MW |
1490 | pm_runtime_put_noidle(&pdev->dev); |
1491 | pm_runtime_disable(&pdev->dev); | |
1492 | ||
e0c9905e | 1493 | /* Release IRQ */ |
2f1a74e5 | 1494 | free_irq(ssp->irq, drv_data); |
1495 | ||
1496 | /* Release SSP */ | |
baffe169 | 1497 | pxa_ssp_free(ssp); |
e0c9905e | 1498 | |
e0c9905e SS |
1499 | return 0; |
1500 | } | |
1501 | ||
1502 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1503 | { | |
1504 | int status = 0; | |
1505 | ||
1506 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1507 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1508 | } | |
1509 | ||
382cebb0 | 1510 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1511 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1512 | { |
86d2593a | 1513 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1514 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1515 | int status = 0; |
1516 | ||
7f86bde9 | 1517 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1518 | if (status != 0) |
1519 | return status; | |
c039dd27 | 1520 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1521 | |
1522 | if (!pm_runtime_suspended(dev)) | |
1523 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
86d2593a | 1528 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1529 | { |
86d2593a | 1530 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1531 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1532 | int status = 0; |
1533 | ||
cd7bed00 | 1534 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1535 | |
e0c9905e | 1536 | /* Enable the SSP clock */ |
2b9375b9 DES |
1537 | if (!pm_runtime_suspended(dev)) |
1538 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1539 | |
c50325f7 | 1540 | /* Restore LPSS private register bits */ |
48421adf JN |
1541 | if (is_lpss_ssp(drv_data)) |
1542 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1543 | |
e0c9905e | 1544 | /* Start the queue running */ |
7f86bde9 | 1545 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1546 | if (status != 0) { |
86d2593a | 1547 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1548 | return status; |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
7d94a505 MW |
1553 | #endif |
1554 | ||
ec833050 | 1555 | #ifdef CONFIG_PM |
7d94a505 MW |
1556 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1557 | { | |
1558 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1559 | ||
1560 | clk_disable_unprepare(drv_data->ssp->clk); | |
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1565 | { | |
1566 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1567 | ||
1568 | clk_prepare_enable(drv_data->ssp->clk); | |
1569 | return 0; | |
1570 | } | |
1571 | #endif | |
86d2593a | 1572 | |
47145210 | 1573 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1574 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1575 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1576 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1577 | }; |
e0c9905e SS |
1578 | |
1579 | static struct platform_driver driver = { | |
1580 | .driver = { | |
86d2593a | 1581 | .name = "pxa2xx-spi", |
86d2593a | 1582 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1583 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1584 | }, |
fbd29a14 | 1585 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1586 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1587 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1588 | }; |
1589 | ||
1590 | static int __init pxa2xx_spi_init(void) | |
1591 | { | |
fbd29a14 | 1592 | return platform_driver_register(&driver); |
e0c9905e | 1593 | } |
5b61a749 | 1594 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1595 | |
1596 | static void __exit pxa2xx_spi_exit(void) | |
1597 | { | |
1598 | platform_driver_unregister(&driver); | |
1599 | } | |
1600 | module_exit(pxa2xx_spi_exit); |