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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
cbfd6a21 | 25 | #include <linux/err.h> |
e0c9905e SS |
26 | #include <linux/interrupt.h> |
27 | #include <linux/platform_device.h> | |
8348c259 | 28 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 29 | #include <linux/spi/spi.h> |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e SS |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
e0c9905e | 39 | #include <asm/delay.h> |
e0c9905e | 40 | |
cd7bed00 | 41 | #include "spi-pxa2xx.h" |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define TIMOUT_DFLT 1000 |
51 | ||
b97c74bd NF |
52 | /* |
53 | * for testing SSCR1 changes that require SSP restart, basically | |
54 | * everything except the service and interrupt enables, the pxa270 developer | |
55 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
56 | * list, but the PXA255 dev man says all bits without really meaning the | |
57 | * service and interrupt enables | |
58 | */ | |
59 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 60 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
61 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
62 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 65 | |
a0d2642e MW |
66 | #define LPSS_RX_THRESH_DFLT 64 |
67 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
68 | #define LPSS_TX_HITHRESH_DFLT 224 | |
69 | ||
70 | /* Offset from drv_data->lpss_base */ | |
1de70612 MW |
71 | #define GENERAL_REG 0x08 |
72 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 73 | #define SSP_REG 0x0c |
a0d2642e MW |
74 | #define SPI_CS_CONTROL 0x18 |
75 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
76 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
77 | ||
78 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
79 | { | |
80 | return drv_data->ssp_type == LPSS_SSP; | |
81 | } | |
82 | ||
83 | /* | |
84 | * Read and write LPSS SSP private registers. Caller must first check that | |
85 | * is_lpss_ssp() returns true before these can be called. | |
86 | */ | |
87 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
88 | { | |
89 | WARN_ON(!drv_data->lpss_base); | |
90 | return readl(drv_data->lpss_base + offset); | |
91 | } | |
92 | ||
93 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
94 | unsigned offset, u32 value) | |
95 | { | |
96 | WARN_ON(!drv_data->lpss_base); | |
97 | writel(value, drv_data->lpss_base + offset); | |
98 | } | |
99 | ||
100 | /* | |
101 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
102 | * @drv_data: pointer to the driver private data | |
103 | * | |
104 | * Perform LPSS SSP specific setup. This function must be called first if | |
105 | * one is going to use LPSS SSP private registers. | |
106 | */ | |
107 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
108 | { | |
109 | unsigned offset = 0x400; | |
110 | u32 value, orig; | |
111 | ||
112 | if (!is_lpss_ssp(drv_data)) | |
113 | return; | |
114 | ||
115 | /* | |
116 | * Perform auto-detection of the LPSS SSP private registers. They | |
117 | * can be either at 1k or 2k offset from the base address. | |
118 | */ | |
119 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
120 | ||
e61f487f | 121 | /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ |
a0d2642e MW |
122 | value = orig | SPI_CS_CONTROL_SW_MODE; |
123 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
124 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
125 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
126 | offset = 0x800; | |
127 | goto detection_done; | |
128 | } | |
129 | ||
e61f487f CCE |
130 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); |
131 | ||
132 | /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ | |
133 | value = orig & ~SPI_CS_CONTROL_SW_MODE; | |
a0d2642e MW |
134 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); |
135 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
e61f487f | 136 | if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { |
a0d2642e MW |
137 | offset = 0x800; |
138 | goto detection_done; | |
139 | } | |
140 | ||
141 | detection_done: | |
142 | /* Now set the LPSS base */ | |
143 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
144 | ||
145 | /* Enable software chip select control */ | |
146 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
147 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
148 | |
149 | /* Enable multiblock DMA transfers */ | |
1de70612 | 150 | if (drv_data->master_info->enable_dma) { |
0054e28d | 151 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
152 | |
153 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
154 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
155 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
156 | } | |
a0d2642e MW |
157 | } |
158 | ||
159 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
160 | { | |
161 | u32 value; | |
162 | ||
163 | if (!is_lpss_ssp(drv_data)) | |
164 | return; | |
165 | ||
166 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
167 | if (enable) | |
168 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
169 | else | |
170 | value |= SPI_CS_CONTROL_CS_HIGH; | |
171 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
172 | } | |
173 | ||
a7bb3909 EM |
174 | static void cs_assert(struct driver_data *drv_data) |
175 | { | |
176 | struct chip_data *chip = drv_data->cur_chip; | |
177 | ||
2a8626a9 SAS |
178 | if (drv_data->ssp_type == CE4100_SSP) { |
179 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
180 | return; | |
181 | } | |
182 | ||
a7bb3909 EM |
183 | if (chip->cs_control) { |
184 | chip->cs_control(PXA2XX_CS_ASSERT); | |
185 | return; | |
186 | } | |
187 | ||
a0d2642e | 188 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 189 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
190 | return; |
191 | } | |
192 | ||
193 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
194 | } |
195 | ||
196 | static void cs_deassert(struct driver_data *drv_data) | |
197 | { | |
198 | struct chip_data *chip = drv_data->cur_chip; | |
199 | ||
2a8626a9 SAS |
200 | if (drv_data->ssp_type == CE4100_SSP) |
201 | return; | |
202 | ||
a7bb3909 | 203 | if (chip->cs_control) { |
2b2562d3 | 204 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
205 | return; |
206 | } | |
207 | ||
a0d2642e | 208 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 209 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
210 | return; |
211 | } | |
212 | ||
213 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
214 | } |
215 | ||
cd7bed00 | 216 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
217 | { |
218 | unsigned long limit = loops_per_jiffy << 1; | |
219 | ||
cf43369d | 220 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
221 | |
222 | do { | |
223 | while (read_SSSR(reg) & SSSR_RNE) { | |
224 | read_SSDR(reg); | |
225 | } | |
306c68aa | 226 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 227 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
228 | |
229 | return limit; | |
230 | } | |
231 | ||
8d94cc50 | 232 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 233 | { |
cf43369d | 234 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 235 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 236 | |
4a25605f | 237 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
238 | || (drv_data->tx == drv_data->tx_end)) |
239 | return 0; | |
240 | ||
241 | write_SSDR(0, reg); | |
242 | drv_data->tx += n_bytes; | |
243 | ||
244 | return 1; | |
e0c9905e SS |
245 | } |
246 | ||
8d94cc50 | 247 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 248 | { |
cf43369d | 249 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 250 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
251 | |
252 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 253 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
254 | read_SSDR(reg); |
255 | drv_data->rx += n_bytes; | |
256 | } | |
8d94cc50 SS |
257 | |
258 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
259 | } |
260 | ||
8d94cc50 | 261 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 262 | { |
cf43369d | 263 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 264 | |
4a25605f | 265 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
266 | || (drv_data->tx == drv_data->tx_end)) |
267 | return 0; | |
268 | ||
269 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
270 | ++drv_data->tx; | |
271 | ||
272 | return 1; | |
e0c9905e SS |
273 | } |
274 | ||
8d94cc50 | 275 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 276 | { |
cf43369d | 277 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
278 | |
279 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 280 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
281 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
282 | ++drv_data->rx; | |
283 | } | |
8d94cc50 SS |
284 | |
285 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
286 | } |
287 | ||
8d94cc50 | 288 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 289 | { |
cf43369d | 290 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 291 | |
4a25605f | 292 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
293 | || (drv_data->tx == drv_data->tx_end)) |
294 | return 0; | |
295 | ||
296 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
297 | drv_data->tx += 2; | |
298 | ||
299 | return 1; | |
e0c9905e SS |
300 | } |
301 | ||
8d94cc50 | 302 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 303 | { |
cf43369d | 304 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
305 | |
306 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 307 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
308 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
309 | drv_data->rx += 2; | |
310 | } | |
8d94cc50 SS |
311 | |
312 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 313 | } |
8d94cc50 SS |
314 | |
315 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 316 | { |
cf43369d | 317 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 318 | |
4a25605f | 319 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
320 | || (drv_data->tx == drv_data->tx_end)) |
321 | return 0; | |
322 | ||
323 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
324 | drv_data->tx += 4; | |
325 | ||
326 | return 1; | |
e0c9905e SS |
327 | } |
328 | ||
8d94cc50 | 329 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 330 | { |
cf43369d | 331 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
332 | |
333 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 334 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
335 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
336 | drv_data->rx += 4; | |
337 | } | |
8d94cc50 SS |
338 | |
339 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
340 | } |
341 | ||
cd7bed00 | 342 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
343 | { |
344 | struct spi_message *msg = drv_data->cur_msg; | |
345 | struct spi_transfer *trans = drv_data->cur_transfer; | |
346 | ||
347 | /* Move to next transfer */ | |
348 | if (trans->transfer_list.next != &msg->transfers) { | |
349 | drv_data->cur_transfer = | |
350 | list_entry(trans->transfer_list.next, | |
351 | struct spi_transfer, | |
352 | transfer_list); | |
353 | return RUNNING_STATE; | |
354 | } else | |
355 | return DONE_STATE; | |
356 | } | |
357 | ||
e0c9905e | 358 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 359 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
360 | { |
361 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 362 | struct spi_message *msg; |
e0c9905e | 363 | |
5daa3ba0 SS |
364 | msg = drv_data->cur_msg; |
365 | drv_data->cur_msg = NULL; | |
366 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 367 | |
23e2c2aa | 368 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
369 | transfer_list); |
370 | ||
8423597d NF |
371 | /* Delay if requested before any change in chip select */ |
372 | if (last_transfer->delay_usecs) | |
373 | udelay(last_transfer->delay_usecs); | |
374 | ||
375 | /* Drop chip select UNLESS cs_change is true or we are returning | |
376 | * a message with an error, or next message is for another chip | |
377 | */ | |
e0c9905e | 378 | if (!last_transfer->cs_change) |
a7bb3909 | 379 | cs_deassert(drv_data); |
8423597d NF |
380 | else { |
381 | struct spi_message *next_msg; | |
382 | ||
383 | /* Holding of cs was hinted, but we need to make sure | |
384 | * the next message is for the same chip. Don't waste | |
385 | * time with the following tests unless this was hinted. | |
386 | * | |
387 | * We cannot postpone this until pump_messages, because | |
388 | * after calling msg->complete (below) the driver that | |
389 | * sent the current message could be unloaded, which | |
390 | * could invalidate the cs_control() callback... | |
391 | */ | |
392 | ||
393 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 394 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
395 | |
396 | /* see if the next and current messages point | |
397 | * to the same chip | |
398 | */ | |
399 | if (next_msg && next_msg->spi != msg->spi) | |
400 | next_msg = NULL; | |
401 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 402 | cs_deassert(drv_data); |
8423597d | 403 | } |
e0c9905e | 404 | |
7f86bde9 | 405 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 406 | drv_data->cur_chip = NULL; |
e0c9905e SS |
407 | } |
408 | ||
579d3bb2 SAS |
409 | static void reset_sccr1(struct driver_data *drv_data) |
410 | { | |
411 | void __iomem *reg = drv_data->ioaddr; | |
412 | struct chip_data *chip = drv_data->cur_chip; | |
413 | u32 sccr1_reg; | |
414 | ||
415 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
416 | sccr1_reg &= ~SSCR1_RFT; | |
417 | sccr1_reg |= chip->threshold; | |
418 | write_SSCR1(sccr1_reg, reg); | |
419 | } | |
420 | ||
8d94cc50 | 421 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 422 | { |
cf43369d | 423 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 424 | |
8d94cc50 | 425 | /* Stop and reset SSP */ |
2a8626a9 | 426 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 427 | reset_sccr1(drv_data); |
2a8626a9 | 428 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 429 | write_SSTO(0, reg); |
cd7bed00 | 430 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 431 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 432 | |
8d94cc50 | 433 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 434 | |
8d94cc50 SS |
435 | drv_data->cur_msg->state = ERROR_STATE; |
436 | tasklet_schedule(&drv_data->pump_transfers); | |
437 | } | |
5daa3ba0 | 438 | |
8d94cc50 SS |
439 | static void int_transfer_complete(struct driver_data *drv_data) |
440 | { | |
cf43369d | 441 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 442 | |
8d94cc50 | 443 | /* Stop SSP */ |
2a8626a9 | 444 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 445 | reset_sccr1(drv_data); |
2a8626a9 | 446 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 447 | write_SSTO(0, reg); |
e0c9905e | 448 | |
25985edc | 449 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
450 | drv_data->cur_msg->actual_length += drv_data->len - |
451 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 452 | |
8423597d NF |
453 | /* Transfer delays and chip select release are |
454 | * handled in pump_transfers or giveback | |
455 | */ | |
e0c9905e | 456 | |
8d94cc50 | 457 | /* Move to next transfer */ |
cd7bed00 | 458 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 459 | |
8d94cc50 SS |
460 | /* Schedule transfer tasklet */ |
461 | tasklet_schedule(&drv_data->pump_transfers); | |
462 | } | |
e0c9905e | 463 | |
8d94cc50 SS |
464 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
465 | { | |
cf43369d | 466 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 467 | |
8d94cc50 SS |
468 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
469 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 470 | |
8d94cc50 | 471 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 472 | |
8d94cc50 SS |
473 | if (irq_status & SSSR_ROR) { |
474 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
475 | return IRQ_HANDLED; | |
476 | } | |
e0c9905e | 477 | |
8d94cc50 SS |
478 | if (irq_status & SSSR_TINT) { |
479 | write_SSSR(SSSR_TINT, reg); | |
480 | if (drv_data->read(drv_data)) { | |
481 | int_transfer_complete(drv_data); | |
482 | return IRQ_HANDLED; | |
483 | } | |
484 | } | |
e0c9905e | 485 | |
8d94cc50 SS |
486 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
487 | do { | |
488 | if (drv_data->read(drv_data)) { | |
489 | int_transfer_complete(drv_data); | |
490 | return IRQ_HANDLED; | |
491 | } | |
492 | } while (drv_data->write(drv_data)); | |
e0c9905e | 493 | |
8d94cc50 SS |
494 | if (drv_data->read(drv_data)) { |
495 | int_transfer_complete(drv_data); | |
496 | return IRQ_HANDLED; | |
497 | } | |
e0c9905e | 498 | |
8d94cc50 | 499 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
500 | u32 bytes_left; |
501 | u32 sccr1_reg; | |
502 | ||
503 | sccr1_reg = read_SSCR1(reg); | |
504 | sccr1_reg &= ~SSCR1_TIE; | |
505 | ||
506 | /* | |
507 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 508 | * remaining RX bytes. |
579d3bb2 | 509 | */ |
2a8626a9 | 510 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
511 | |
512 | sccr1_reg &= ~SSCR1_RFT; | |
513 | ||
514 | bytes_left = drv_data->rx_end - drv_data->rx; | |
515 | switch (drv_data->n_bytes) { | |
516 | case 4: | |
517 | bytes_left >>= 1; | |
518 | case 2: | |
519 | bytes_left >>= 1; | |
8d94cc50 | 520 | } |
579d3bb2 SAS |
521 | |
522 | if (bytes_left > RX_THRESH_DFLT) | |
523 | bytes_left = RX_THRESH_DFLT; | |
524 | ||
525 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 526 | } |
579d3bb2 | 527 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
528 | } |
529 | ||
5daa3ba0 SS |
530 | /* We did something */ |
531 | return IRQ_HANDLED; | |
e0c9905e SS |
532 | } |
533 | ||
7d12e780 | 534 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 535 | { |
c7bec5ab | 536 | struct driver_data *drv_data = dev_id; |
cf43369d | 537 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 538 | u32 sccr1_reg; |
49cbb1e0 SAS |
539 | u32 mask = drv_data->mask_sr; |
540 | u32 status; | |
541 | ||
7d94a505 MW |
542 | /* |
543 | * The IRQ might be shared with other peripherals so we must first | |
544 | * check that are we RPM suspended or not. If we are we assume that | |
545 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
546 | * interrupt is enabled). | |
547 | */ | |
548 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
549 | return IRQ_NONE; | |
550 | ||
269e4a41 MW |
551 | /* |
552 | * If the device is not yet in RPM suspended state and we get an | |
553 | * interrupt that is meant for another device, check if status bits | |
554 | * are all set to one. That means that the device is already | |
555 | * powered off. | |
556 | */ | |
49cbb1e0 | 557 | status = read_SSSR(reg); |
269e4a41 MW |
558 | if (status == ~0) |
559 | return IRQ_NONE; | |
560 | ||
561 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
562 | |
563 | /* Ignore possible writes if we don't need to write */ | |
564 | if (!(sccr1_reg & SSCR1_TIE)) | |
565 | mask &= ~SSSR_TFS; | |
566 | ||
567 | if (!(status & mask)) | |
568 | return IRQ_NONE; | |
e0c9905e SS |
569 | |
570 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
571 | |
572 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
573 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 574 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 575 | write_SSTO(0, reg); |
2a8626a9 | 576 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 577 | |
f6bd03a7 JN |
578 | dev_err(&drv_data->pdev->dev, |
579 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 580 | |
e0c9905e SS |
581 | /* Never fail */ |
582 | return IRQ_HANDLED; | |
583 | } | |
584 | ||
585 | return drv_data->transfer_handler(drv_data); | |
586 | } | |
587 | ||
3343b7a6 | 588 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 589 | { |
3343b7a6 MW |
590 | unsigned long ssp_clk = drv_data->max_clk_rate; |
591 | const struct ssp_device *ssp = drv_data->ssp; | |
592 | ||
593 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 594 | |
2a8626a9 | 595 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 596 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
597 | else | |
598 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
599 | } | |
600 | ||
e0c9905e SS |
601 | static void pump_transfers(unsigned long data) |
602 | { | |
603 | struct driver_data *drv_data = (struct driver_data *)data; | |
604 | struct spi_message *message = NULL; | |
605 | struct spi_transfer *transfer = NULL; | |
606 | struct spi_transfer *previous = NULL; | |
607 | struct chip_data *chip = NULL; | |
cf43369d | 608 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
609 | u32 clk_div = 0; |
610 | u8 bits = 0; | |
611 | u32 speed = 0; | |
612 | u32 cr0; | |
8d94cc50 SS |
613 | u32 cr1; |
614 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
615 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
616 | |
617 | /* Get current state information */ | |
618 | message = drv_data->cur_msg; | |
619 | transfer = drv_data->cur_transfer; | |
620 | chip = drv_data->cur_chip; | |
621 | ||
622 | /* Handle for abort */ | |
623 | if (message->state == ERROR_STATE) { | |
624 | message->status = -EIO; | |
5daa3ba0 | 625 | giveback(drv_data); |
e0c9905e SS |
626 | return; |
627 | } | |
628 | ||
629 | /* Handle end of message */ | |
630 | if (message->state == DONE_STATE) { | |
631 | message->status = 0; | |
5daa3ba0 | 632 | giveback(drv_data); |
e0c9905e SS |
633 | return; |
634 | } | |
635 | ||
8423597d | 636 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
637 | if (message->state == RUNNING_STATE) { |
638 | previous = list_entry(transfer->transfer_list.prev, | |
639 | struct spi_transfer, | |
640 | transfer_list); | |
641 | if (previous->delay_usecs) | |
642 | udelay(previous->delay_usecs); | |
8423597d NF |
643 | |
644 | /* Drop chip select only if cs_change is requested */ | |
645 | if (previous->cs_change) | |
a7bb3909 | 646 | cs_deassert(drv_data); |
e0c9905e SS |
647 | } |
648 | ||
cd7bed00 MW |
649 | /* Check if we can DMA this transfer */ |
650 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
651 | |
652 | /* reject already-mapped transfers; PIO won't always work */ | |
653 | if (message->is_dma_mapped | |
654 | || transfer->rx_dma || transfer->tx_dma) { | |
655 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
656 | "pump_transfers: mapped transfer length of " |
657 | "%u is greater than %d\n", | |
7e964455 NF |
658 | transfer->len, MAX_DMA_LEN); |
659 | message->status = -EINVAL; | |
660 | giveback(drv_data); | |
661 | return; | |
662 | } | |
663 | ||
664 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
665 | dev_warn_ratelimited(&message->spi->dev, |
666 | "pump_transfers: DMA disabled for transfer length %ld " | |
667 | "greater than %d\n", | |
668 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
669 | } |
670 | ||
e0c9905e | 671 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 672 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
673 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
674 | message->status = -EIO; | |
5daa3ba0 | 675 | giveback(drv_data); |
e0c9905e SS |
676 | return; |
677 | } | |
9708c121 | 678 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
679 | drv_data->tx = (void *)transfer->tx_buf; |
680 | drv_data->tx_end = drv_data->tx + transfer->len; | |
681 | drv_data->rx = transfer->rx_buf; | |
682 | drv_data->rx_end = drv_data->rx + transfer->len; | |
683 | drv_data->rx_dma = transfer->rx_dma; | |
684 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 685 | drv_data->len = transfer->len; |
e0c9905e SS |
686 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
687 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
688 | |
689 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 690 | cr0 = chip->cr0; |
9708c121 SS |
691 | if (transfer->speed_hz || transfer->bits_per_word) { |
692 | ||
9708c121 SS |
693 | bits = chip->bits_per_word; |
694 | speed = chip->speed_hz; | |
695 | ||
696 | if (transfer->speed_hz) | |
697 | speed = transfer->speed_hz; | |
698 | ||
699 | if (transfer->bits_per_word) | |
700 | bits = transfer->bits_per_word; | |
701 | ||
3343b7a6 | 702 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
703 | |
704 | if (bits <= 8) { | |
705 | drv_data->n_bytes = 1; | |
9708c121 SS |
706 | drv_data->read = drv_data->read != null_reader ? |
707 | u8_reader : null_reader; | |
708 | drv_data->write = drv_data->write != null_writer ? | |
709 | u8_writer : null_writer; | |
710 | } else if (bits <= 16) { | |
711 | drv_data->n_bytes = 2; | |
9708c121 SS |
712 | drv_data->read = drv_data->read != null_reader ? |
713 | u16_reader : null_reader; | |
714 | drv_data->write = drv_data->write != null_writer ? | |
715 | u16_writer : null_writer; | |
716 | } else if (bits <= 32) { | |
717 | drv_data->n_bytes = 4; | |
9708c121 SS |
718 | drv_data->read = drv_data->read != null_reader ? |
719 | u32_reader : null_reader; | |
720 | drv_data->write = drv_data->write != null_writer ? | |
721 | u32_writer : null_writer; | |
722 | } | |
8d94cc50 SS |
723 | /* if bits/word is changed in dma mode, then must check the |
724 | * thresholds and burst also */ | |
725 | if (chip->enable_dma) { | |
cd7bed00 MW |
726 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
727 | message->spi, | |
8d94cc50 SS |
728 | bits, &dma_burst, |
729 | &dma_thresh)) | |
f6bd03a7 JN |
730 | dev_warn_ratelimited(&message->spi->dev, |
731 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 732 | } |
9708c121 SS |
733 | |
734 | cr0 = clk_div | |
735 | | SSCR0_Motorola | |
5daa3ba0 | 736 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
737 | | SSCR0_SSE |
738 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
739 | } |
740 | ||
e0c9905e SS |
741 | message->state = RUNNING_STATE; |
742 | ||
7e964455 | 743 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
744 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
745 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 746 | if (drv_data->dma_mapped) { |
e0c9905e SS |
747 | |
748 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
749 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
750 | ||
751 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 752 | |
8d94cc50 SS |
753 | /* Clear status and start DMA engine */ |
754 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 755 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
756 | |
757 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
758 | } else { |
759 | /* Ensure we have the correct interrupt handler */ | |
760 | drv_data->transfer_handler = interrupt_transfer; | |
761 | ||
8d94cc50 SS |
762 | /* Clear status */ |
763 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 764 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
765 | } |
766 | ||
a0d2642e MW |
767 | if (is_lpss_ssp(drv_data)) { |
768 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
769 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
770 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
771 | write_SSITF(chip->lpss_tx_threshold, reg); | |
772 | } | |
773 | ||
8d94cc50 SS |
774 | /* see if we need to reload the config registers */ |
775 | if ((read_SSCR0(reg) != cr0) | |
776 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
777 | (cr1 & SSCR1_CHANGE_MASK)) { | |
778 | ||
b97c74bd | 779 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 780 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 781 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 782 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
783 | /* first set CR1 without interrupt and service enables */ |
784 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
785 | /* restart the SSP */ | |
8d94cc50 | 786 | write_SSCR0(cr0, reg); |
b97c74bd | 787 | |
8d94cc50 | 788 | } else { |
2a8626a9 | 789 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 790 | write_SSTO(chip->timeout, reg); |
e0c9905e | 791 | } |
b97c74bd | 792 | |
a7bb3909 | 793 | cs_assert(drv_data); |
b97c74bd NF |
794 | |
795 | /* after chip select, release the data by enabling service | |
796 | * requests and interrupts, without changing any mode bits */ | |
797 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
798 | } |
799 | ||
7f86bde9 MW |
800 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
801 | struct spi_message *msg) | |
e0c9905e | 802 | { |
7f86bde9 | 803 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 804 | |
7f86bde9 | 805 | drv_data->cur_msg = msg; |
e0c9905e SS |
806 | /* Initial message state*/ |
807 | drv_data->cur_msg->state = START_STATE; | |
808 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
809 | struct spi_transfer, | |
810 | transfer_list); | |
811 | ||
8d94cc50 SS |
812 | /* prepare to setup the SSP, in pump_transfers, using the per |
813 | * chip configuration */ | |
e0c9905e | 814 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
815 | |
816 | /* Mark as busy and launch transfers */ | |
817 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
818 | return 0; |
819 | } | |
820 | ||
7d94a505 MW |
821 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
822 | { | |
823 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
824 | ||
825 | /* Disable the SSP now */ | |
826 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
827 | drv_data->ioaddr); | |
828 | ||
7d94a505 MW |
829 | return 0; |
830 | } | |
831 | ||
a7bb3909 EM |
832 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
833 | struct pxa2xx_spi_chip *chip_info) | |
834 | { | |
835 | int err = 0; | |
836 | ||
837 | if (chip == NULL || chip_info == NULL) | |
838 | return 0; | |
839 | ||
840 | /* NOTE: setup() can be called multiple times, possibly with | |
841 | * different chip_info, release previously requested GPIO | |
842 | */ | |
843 | if (gpio_is_valid(chip->gpio_cs)) | |
844 | gpio_free(chip->gpio_cs); | |
845 | ||
846 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
847 | if (chip_info->cs_control) { | |
848 | chip->cs_control = chip_info->cs_control; | |
849 | return 0; | |
850 | } | |
851 | ||
852 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
853 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
854 | if (err) { | |
f6bd03a7 JN |
855 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
856 | chip_info->gpio_cs); | |
a7bb3909 EM |
857 | return err; |
858 | } | |
859 | ||
860 | chip->gpio_cs = chip_info->gpio_cs; | |
861 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
862 | ||
863 | err = gpio_direction_output(chip->gpio_cs, | |
864 | !chip->gpio_cs_inverted); | |
865 | } | |
866 | ||
867 | return err; | |
868 | } | |
869 | ||
e0c9905e SS |
870 | static int setup(struct spi_device *spi) |
871 | { | |
872 | struct pxa2xx_spi_chip *chip_info = NULL; | |
873 | struct chip_data *chip; | |
874 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
875 | unsigned int clk_div; | |
a0d2642e MW |
876 | uint tx_thres, tx_hi_thres, rx_thres; |
877 | ||
878 | if (is_lpss_ssp(drv_data)) { | |
879 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
880 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
881 | rx_thres = LPSS_RX_THRESH_DFLT; | |
882 | } else { | |
883 | tx_thres = TX_THRESH_DFLT; | |
884 | tx_hi_thres = 0; | |
885 | rx_thres = RX_THRESH_DFLT; | |
886 | } | |
e0c9905e | 887 | |
8d94cc50 | 888 | /* Only alloc on first setup */ |
e0c9905e | 889 | chip = spi_get_ctldata(spi); |
8d94cc50 | 890 | if (!chip) { |
e0c9905e | 891 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 892 | if (!chip) |
e0c9905e SS |
893 | return -ENOMEM; |
894 | ||
2a8626a9 SAS |
895 | if (drv_data->ssp_type == CE4100_SSP) { |
896 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
897 | dev_err(&spi->dev, |
898 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
899 | kfree(chip); |
900 | return -EINVAL; | |
901 | } | |
902 | ||
903 | chip->frm = spi->chip_select; | |
904 | } else | |
905 | chip->gpio_cs = -1; | |
e0c9905e | 906 | chip->enable_dma = 0; |
f1f640a9 | 907 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
908 | } |
909 | ||
8d94cc50 SS |
910 | /* protocol drivers may change the chip settings, so... |
911 | * if chip_info exists, use it */ | |
912 | chip_info = spi->controller_data; | |
913 | ||
e0c9905e | 914 | /* chip_info isn't always needed */ |
8d94cc50 | 915 | chip->cr1 = 0; |
e0c9905e | 916 | if (chip_info) { |
f1f640a9 VS |
917 | if (chip_info->timeout) |
918 | chip->timeout = chip_info->timeout; | |
919 | if (chip_info->tx_threshold) | |
920 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
921 | if (chip_info->tx_hi_threshold) |
922 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
923 | if (chip_info->rx_threshold) |
924 | rx_thres = chip_info->rx_threshold; | |
925 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 926 | chip->dma_threshold = 0; |
e0c9905e SS |
927 | if (chip_info->enable_loopback) |
928 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
929 | } else if (ACPI_HANDLE(&spi->dev)) { |
930 | /* | |
931 | * Slave devices enumerated from ACPI namespace don't | |
932 | * usually have chip_info but we still might want to use | |
933 | * DMA with them. | |
934 | */ | |
935 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
936 | } |
937 | ||
f1f640a9 VS |
938 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
939 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
940 | ||
a0d2642e MW |
941 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
942 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
943 | | SSITF_TxHiThresh(tx_hi_thres); | |
944 | ||
8d94cc50 SS |
945 | /* set dma burst and threshold outside of chip_info path so that if |
946 | * chip_info goes away after setting chip->enable_dma, the | |
947 | * burst and threshold can still respond to changes in bits_per_word */ | |
948 | if (chip->enable_dma) { | |
949 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
950 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
951 | spi->bits_per_word, | |
8d94cc50 SS |
952 | &chip->dma_burst_size, |
953 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
954 | dev_warn(&spi->dev, |
955 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
956 | } |
957 | } | |
958 | ||
3343b7a6 | 959 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 960 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
961 | |
962 | chip->cr0 = clk_div | |
963 | | SSCR0_Motorola | |
5daa3ba0 SS |
964 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
965 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
966 | | SSCR0_SSE |
967 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
968 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
969 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
970 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 971 | |
b833172f MW |
972 | if (spi->mode & SPI_LOOP) |
973 | chip->cr1 |= SSCR1_LBM; | |
974 | ||
e0c9905e | 975 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 976 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 977 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 978 | drv_data->max_clk_rate |
c9840daa EM |
979 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
980 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 981 | else |
7d077197 | 982 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 983 | drv_data->max_clk_rate / 2 |
c9840daa EM |
984 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
985 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
986 | |
987 | if (spi->bits_per_word <= 8) { | |
988 | chip->n_bytes = 1; | |
e0c9905e SS |
989 | chip->read = u8_reader; |
990 | chip->write = u8_writer; | |
991 | } else if (spi->bits_per_word <= 16) { | |
992 | chip->n_bytes = 2; | |
e0c9905e SS |
993 | chip->read = u16_reader; |
994 | chip->write = u16_writer; | |
995 | } else if (spi->bits_per_word <= 32) { | |
996 | chip->cr0 |= SSCR0_EDSS; | |
997 | chip->n_bytes = 4; | |
e0c9905e SS |
998 | chip->read = u32_reader; |
999 | chip->write = u32_writer; | |
e0c9905e | 1000 | } |
9708c121 | 1001 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1002 | |
1003 | spi_set_ctldata(spi, chip); | |
1004 | ||
2a8626a9 SAS |
1005 | if (drv_data->ssp_type == CE4100_SSP) |
1006 | return 0; | |
1007 | ||
a7bb3909 | 1008 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1009 | } |
1010 | ||
0ffa0285 | 1011 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1012 | { |
0ffa0285 | 1013 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1014 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1015 | |
7348d82a DR |
1016 | if (!chip) |
1017 | return; | |
1018 | ||
2a8626a9 | 1019 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1020 | gpio_free(chip->gpio_cs); |
1021 | ||
e0c9905e SS |
1022 | kfree(chip); |
1023 | } | |
1024 | ||
a3496855 | 1025 | #ifdef CONFIG_ACPI |
a3496855 MW |
1026 | static struct pxa2xx_spi_master * |
1027 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1028 | { | |
1029 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1030 | struct acpi_device *adev; |
1031 | struct ssp_device *ssp; | |
1032 | struct resource *res; | |
1033 | int devid; | |
1034 | ||
1035 | if (!ACPI_HANDLE(&pdev->dev) || | |
1036 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1037 | return NULL; | |
1038 | ||
cc0ee987 | 1039 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1040 | if (!pdata) |
a3496855 | 1041 | return NULL; |
a3496855 MW |
1042 | |
1043 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1044 | if (!res) | |
1045 | return NULL; | |
1046 | ||
1047 | ssp = &pdata->ssp; | |
1048 | ||
1049 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1050 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1051 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1052 | return NULL; |
a3496855 MW |
1053 | |
1054 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1055 | ssp->irq = platform_get_irq(pdev, 0); | |
1056 | ssp->type = LPSS_SSP; | |
1057 | ssp->pdev = pdev; | |
1058 | ||
1059 | ssp->port_id = -1; | |
1060 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1061 | ssp->port_id = devid; | |
1062 | ||
1063 | pdata->num_chipselect = 1; | |
cddb339b | 1064 | pdata->enable_dma = true; |
483c3191 MW |
1065 | pdata->tx_chan_id = -1; |
1066 | pdata->rx_chan_id = -1; | |
a3496855 MW |
1067 | |
1068 | return pdata; | |
1069 | } | |
1070 | ||
1071 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1072 | { "INT33C0", 0 }, | |
1073 | { "INT33C1", 0 }, | |
54acbd96 MW |
1074 | { "INT3430", 0 }, |
1075 | { "INT3431", 0 }, | |
4b30f2a1 | 1076 | { "80860F0E", 0 }, |
a3496855 MW |
1077 | { }, |
1078 | }; | |
1079 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1080 | #else | |
1081 | static inline struct pxa2xx_spi_master * | |
1082 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1083 | { | |
1084 | return NULL; | |
1085 | } | |
1086 | #endif | |
1087 | ||
fd4a319b | 1088 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1089 | { |
1090 | struct device *dev = &pdev->dev; | |
1091 | struct pxa2xx_spi_master *platform_info; | |
1092 | struct spi_master *master; | |
65a00a20 | 1093 | struct driver_data *drv_data; |
2f1a74e5 | 1094 | struct ssp_device *ssp; |
65a00a20 | 1095 | int status; |
e0c9905e | 1096 | |
851bacf5 MW |
1097 | platform_info = dev_get_platdata(dev); |
1098 | if (!platform_info) { | |
a3496855 MW |
1099 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1100 | if (!platform_info) { | |
1101 | dev_err(&pdev->dev, "missing platform data\n"); | |
1102 | return -ENODEV; | |
1103 | } | |
851bacf5 | 1104 | } |
e0c9905e | 1105 | |
baffe169 | 1106 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1107 | if (!ssp) |
1108 | ssp = &platform_info->ssp; | |
1109 | ||
1110 | if (!ssp->mmio_base) { | |
1111 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1112 | return -ENODEV; |
1113 | } | |
1114 | ||
1115 | /* Allocate master with space for drv_data and null dma buffer */ | |
1116 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1117 | if (!master) { | |
65a00a20 | 1118 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1119 | pxa_ssp_free(ssp); |
e0c9905e SS |
1120 | return -ENOMEM; |
1121 | } | |
1122 | drv_data = spi_master_get_devdata(master); | |
1123 | drv_data->master = master; | |
1124 | drv_data->master_info = platform_info; | |
1125 | drv_data->pdev = pdev; | |
2f1a74e5 | 1126 | drv_data->ssp = ssp; |
e0c9905e | 1127 | |
21486af0 | 1128 | master->dev.parent = &pdev->dev; |
21486af0 | 1129 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1130 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1131 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1132 | |
851bacf5 | 1133 | master->bus_num = ssp->port_id; |
e0c9905e | 1134 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1135 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1136 | master->cleanup = cleanup; |
1137 | master->setup = setup; | |
7f86bde9 | 1138 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1139 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1140 | master->auto_runtime_pm = true; |
e0c9905e | 1141 | |
2f1a74e5 | 1142 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1143 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1144 | |
2f1a74e5 | 1145 | drv_data->ioaddr = ssp->mmio_base; |
1146 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1147 | if (pxa25x_ssp_comp(drv_data)) { |
24778be2 | 1148 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e0c9905e SS |
1149 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1150 | drv_data->dma_cr1 = 0; | |
1151 | drv_data->clear_sr = SSSR_ROR; | |
1152 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1153 | } else { | |
24778be2 | 1154 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1155 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1156 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1157 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1158 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1159 | } | |
1160 | ||
49cbb1e0 SAS |
1161 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1162 | drv_data); | |
e0c9905e | 1163 | if (status < 0) { |
65a00a20 | 1164 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1165 | goto out_error_master_alloc; |
1166 | } | |
1167 | ||
1168 | /* Setup DMA if requested */ | |
1169 | drv_data->tx_channel = -1; | |
1170 | drv_data->rx_channel = -1; | |
1171 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1172 | status = pxa2xx_spi_dma_setup(drv_data); |
1173 | if (status) { | |
cddb339b | 1174 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1175 | platform_info->enable_dma = false; |
e0c9905e | 1176 | } |
e0c9905e SS |
1177 | } |
1178 | ||
1179 | /* Enable SOC clock */ | |
3343b7a6 MW |
1180 | clk_prepare_enable(ssp->clk); |
1181 | ||
1182 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1183 | |
1184 | /* Load default SSP configuration */ | |
1185 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1186 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1187 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1188 | drv_data->ioaddr); | |
c9840daa | 1189 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1190 | | SSCR0_Motorola |
1191 | | SSCR0_DataSize(8), | |
1192 | drv_data->ioaddr); | |
2a8626a9 | 1193 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1194 | write_SSTO(0, drv_data->ioaddr); |
1195 | write_SSPSP(0, drv_data->ioaddr); | |
1196 | ||
a0d2642e MW |
1197 | lpss_ssp_setup(drv_data); |
1198 | ||
7f86bde9 MW |
1199 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1200 | (unsigned long)drv_data); | |
e0c9905e | 1201 | |
836d1a22 AO |
1202 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1203 | pm_runtime_use_autosuspend(&pdev->dev); | |
1204 | pm_runtime_set_active(&pdev->dev); | |
1205 | pm_runtime_enable(&pdev->dev); | |
1206 | ||
e0c9905e SS |
1207 | /* Register with the SPI framework */ |
1208 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1209 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1210 | if (status != 0) { |
1211 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1212 | goto out_error_clock_enabled; |
e0c9905e SS |
1213 | } |
1214 | ||
1215 | return status; | |
1216 | ||
e0c9905e | 1217 | out_error_clock_enabled: |
3343b7a6 | 1218 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1219 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1220 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1221 | |
1222 | out_error_master_alloc: | |
1223 | spi_master_put(master); | |
baffe169 | 1224 | pxa_ssp_free(ssp); |
e0c9905e SS |
1225 | return status; |
1226 | } | |
1227 | ||
1228 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1229 | { | |
1230 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1231 | struct ssp_device *ssp; |
e0c9905e SS |
1232 | |
1233 | if (!drv_data) | |
1234 | return 0; | |
51e911e2 | 1235 | ssp = drv_data->ssp; |
e0c9905e | 1236 | |
7d94a505 MW |
1237 | pm_runtime_get_sync(&pdev->dev); |
1238 | ||
e0c9905e SS |
1239 | /* Disable the SSP at the peripheral and SOC level */ |
1240 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1241 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1242 | |
1243 | /* Release DMA */ | |
cd7bed00 MW |
1244 | if (drv_data->master_info->enable_dma) |
1245 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1246 | |
7d94a505 MW |
1247 | pm_runtime_put_noidle(&pdev->dev); |
1248 | pm_runtime_disable(&pdev->dev); | |
1249 | ||
e0c9905e | 1250 | /* Release IRQ */ |
2f1a74e5 | 1251 | free_irq(ssp->irq, drv_data); |
1252 | ||
1253 | /* Release SSP */ | |
baffe169 | 1254 | pxa_ssp_free(ssp); |
e0c9905e | 1255 | |
e0c9905e SS |
1256 | return 0; |
1257 | } | |
1258 | ||
1259 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1260 | { | |
1261 | int status = 0; | |
1262 | ||
1263 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1264 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1265 | } | |
1266 | ||
382cebb0 | 1267 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1268 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1269 | { |
86d2593a | 1270 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1271 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1272 | int status = 0; |
1273 | ||
7f86bde9 | 1274 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1275 | if (status != 0) |
1276 | return status; | |
1277 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1278 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1279 | |
1280 | return 0; | |
1281 | } | |
1282 | ||
86d2593a | 1283 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1284 | { |
86d2593a | 1285 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1286 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1287 | int status = 0; |
1288 | ||
cd7bed00 | 1289 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1290 | |
e0c9905e | 1291 | /* Enable the SSP clock */ |
3343b7a6 | 1292 | clk_prepare_enable(ssp->clk); |
e0c9905e | 1293 | |
c50325f7 CCE |
1294 | /* Restore LPSS private register bits */ |
1295 | lpss_ssp_setup(drv_data); | |
1296 | ||
e0c9905e | 1297 | /* Start the queue running */ |
7f86bde9 | 1298 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1299 | if (status != 0) { |
86d2593a | 1300 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1301 | return status; |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | } | |
7d94a505 MW |
1306 | #endif |
1307 | ||
1308 | #ifdef CONFIG_PM_RUNTIME | |
1309 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1310 | { | |
1311 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1312 | ||
1313 | clk_disable_unprepare(drv_data->ssp->clk); | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1318 | { | |
1319 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1320 | ||
1321 | clk_prepare_enable(drv_data->ssp->clk); | |
1322 | return 0; | |
1323 | } | |
1324 | #endif | |
86d2593a | 1325 | |
47145210 | 1326 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1327 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1328 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1329 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1330 | }; |
e0c9905e SS |
1331 | |
1332 | static struct platform_driver driver = { | |
1333 | .driver = { | |
86d2593a MR |
1334 | .name = "pxa2xx-spi", |
1335 | .owner = THIS_MODULE, | |
86d2593a | 1336 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1337 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1338 | }, |
fbd29a14 | 1339 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1340 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1341 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1342 | }; |
1343 | ||
1344 | static int __init pxa2xx_spi_init(void) | |
1345 | { | |
fbd29a14 | 1346 | return platform_driver_register(&driver); |
e0c9905e | 1347 | } |
5b61a749 | 1348 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1349 | |
1350 | static void __exit pxa2xx_spi_exit(void) | |
1351 | { | |
1352 | platform_driver_unregister(&driver); | |
1353 | } | |
1354 | module_exit(pxa2xx_spi_exit); |