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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
cbfd6a21 | 25 | #include <linux/err.h> |
e0c9905e SS |
26 | #include <linux/interrupt.h> |
27 | #include <linux/platform_device.h> | |
8348c259 | 28 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 29 | #include <linux/spi/spi.h> |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e SS |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
e0c9905e | 39 | #include <asm/delay.h> |
e0c9905e | 40 | |
cd7bed00 | 41 | #include "spi-pxa2xx.h" |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define TIMOUT_DFLT 1000 |
51 | ||
b97c74bd NF |
52 | /* |
53 | * for testing SSCR1 changes that require SSP restart, basically | |
54 | * everything except the service and interrupt enables, the pxa270 developer | |
55 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
56 | * list, but the PXA255 dev man says all bits without really meaning the | |
57 | * service and interrupt enables | |
58 | */ | |
59 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 60 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
61 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
62 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 65 | |
a0d2642e MW |
66 | #define LPSS_RX_THRESH_DFLT 64 |
67 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
68 | #define LPSS_TX_HITHRESH_DFLT 224 | |
69 | ||
70 | /* Offset from drv_data->lpss_base */ | |
1de70612 MW |
71 | #define GENERAL_REG 0x08 |
72 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 73 | #define SSP_REG 0x0c |
a0d2642e MW |
74 | #define SPI_CS_CONTROL 0x18 |
75 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
76 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
77 | ||
78 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
79 | { | |
80 | return drv_data->ssp_type == LPSS_SSP; | |
81 | } | |
82 | ||
4fdb2424 WC |
83 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
84 | { | |
85 | switch (drv_data->ssp_type) { | |
86 | default: | |
87 | return SSCR1_CHANGE_MASK; | |
88 | } | |
89 | } | |
90 | ||
91 | static u32 | |
92 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
93 | { | |
94 | switch (drv_data->ssp_type) { | |
95 | default: | |
96 | return RX_THRESH_DFLT; | |
97 | } | |
98 | } | |
99 | ||
100 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
101 | { | |
102 | void __iomem *reg = drv_data->ioaddr; | |
103 | u32 mask; | |
104 | ||
105 | switch (drv_data->ssp_type) { | |
106 | default: | |
107 | mask = SSSR_TFL_MASK; | |
108 | break; | |
109 | } | |
110 | ||
111 | return (read_SSSR(reg) & mask) == mask; | |
112 | } | |
113 | ||
114 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
115 | u32 *sccr1_reg) | |
116 | { | |
117 | u32 mask; | |
118 | ||
119 | switch (drv_data->ssp_type) { | |
120 | default: | |
121 | mask = SSCR1_RFT; | |
122 | break; | |
123 | } | |
124 | *sccr1_reg &= ~mask; | |
125 | } | |
126 | ||
127 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
128 | u32 *sccr1_reg, u32 threshold) | |
129 | { | |
130 | switch (drv_data->ssp_type) { | |
131 | default: | |
132 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
133 | break; | |
134 | } | |
135 | } | |
136 | ||
137 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
138 | u32 clk_div, u8 bits) | |
139 | { | |
140 | switch (drv_data->ssp_type) { | |
141 | default: | |
142 | return clk_div | |
143 | | SSCR0_Motorola | |
144 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
145 | | SSCR0_SSE | |
146 | | (bits > 16 ? SSCR0_EDSS : 0); | |
147 | } | |
148 | } | |
149 | ||
a0d2642e MW |
150 | /* |
151 | * Read and write LPSS SSP private registers. Caller must first check that | |
152 | * is_lpss_ssp() returns true before these can be called. | |
153 | */ | |
154 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
155 | { | |
156 | WARN_ON(!drv_data->lpss_base); | |
157 | return readl(drv_data->lpss_base + offset); | |
158 | } | |
159 | ||
160 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
161 | unsigned offset, u32 value) | |
162 | { | |
163 | WARN_ON(!drv_data->lpss_base); | |
164 | writel(value, drv_data->lpss_base + offset); | |
165 | } | |
166 | ||
167 | /* | |
168 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
169 | * @drv_data: pointer to the driver private data | |
170 | * | |
171 | * Perform LPSS SSP specific setup. This function must be called first if | |
172 | * one is going to use LPSS SSP private registers. | |
173 | */ | |
174 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
175 | { | |
176 | unsigned offset = 0x400; | |
177 | u32 value, orig; | |
178 | ||
179 | if (!is_lpss_ssp(drv_data)) | |
180 | return; | |
181 | ||
182 | /* | |
183 | * Perform auto-detection of the LPSS SSP private registers. They | |
184 | * can be either at 1k or 2k offset from the base address. | |
185 | */ | |
186 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
187 | ||
e61f487f | 188 | /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ |
a0d2642e MW |
189 | value = orig | SPI_CS_CONTROL_SW_MODE; |
190 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
191 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
192 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
193 | offset = 0x800; | |
194 | goto detection_done; | |
195 | } | |
196 | ||
e61f487f CCE |
197 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); |
198 | ||
199 | /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ | |
200 | value = orig & ~SPI_CS_CONTROL_SW_MODE; | |
a0d2642e MW |
201 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); |
202 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
e61f487f | 203 | if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { |
a0d2642e MW |
204 | offset = 0x800; |
205 | goto detection_done; | |
206 | } | |
207 | ||
208 | detection_done: | |
209 | /* Now set the LPSS base */ | |
210 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
211 | ||
212 | /* Enable software chip select control */ | |
213 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
214 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
215 | |
216 | /* Enable multiblock DMA transfers */ | |
1de70612 | 217 | if (drv_data->master_info->enable_dma) { |
0054e28d | 218 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
219 | |
220 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
221 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
222 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
223 | } | |
a0d2642e MW |
224 | } |
225 | ||
226 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
227 | { | |
228 | u32 value; | |
229 | ||
230 | if (!is_lpss_ssp(drv_data)) | |
231 | return; | |
232 | ||
233 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
234 | if (enable) | |
235 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
236 | else | |
237 | value |= SPI_CS_CONTROL_CS_HIGH; | |
238 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
239 | } | |
240 | ||
a7bb3909 EM |
241 | static void cs_assert(struct driver_data *drv_data) |
242 | { | |
243 | struct chip_data *chip = drv_data->cur_chip; | |
244 | ||
2a8626a9 SAS |
245 | if (drv_data->ssp_type == CE4100_SSP) { |
246 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
247 | return; | |
248 | } | |
249 | ||
a7bb3909 EM |
250 | if (chip->cs_control) { |
251 | chip->cs_control(PXA2XX_CS_ASSERT); | |
252 | return; | |
253 | } | |
254 | ||
a0d2642e | 255 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 256 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
257 | return; |
258 | } | |
259 | ||
260 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
261 | } |
262 | ||
263 | static void cs_deassert(struct driver_data *drv_data) | |
264 | { | |
265 | struct chip_data *chip = drv_data->cur_chip; | |
266 | ||
2a8626a9 SAS |
267 | if (drv_data->ssp_type == CE4100_SSP) |
268 | return; | |
269 | ||
a7bb3909 | 270 | if (chip->cs_control) { |
2b2562d3 | 271 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
272 | return; |
273 | } | |
274 | ||
a0d2642e | 275 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 276 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
277 | return; |
278 | } | |
279 | ||
280 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
281 | } |
282 | ||
cd7bed00 | 283 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
284 | { |
285 | unsigned long limit = loops_per_jiffy << 1; | |
286 | ||
cf43369d | 287 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
288 | |
289 | do { | |
290 | while (read_SSSR(reg) & SSSR_RNE) { | |
291 | read_SSDR(reg); | |
292 | } | |
306c68aa | 293 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 294 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
295 | |
296 | return limit; | |
297 | } | |
298 | ||
8d94cc50 | 299 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 300 | { |
cf43369d | 301 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 302 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 303 | |
4fdb2424 | 304 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
305 | || (drv_data->tx == drv_data->tx_end)) |
306 | return 0; | |
307 | ||
308 | write_SSDR(0, reg); | |
309 | drv_data->tx += n_bytes; | |
310 | ||
311 | return 1; | |
e0c9905e SS |
312 | } |
313 | ||
8d94cc50 | 314 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 315 | { |
cf43369d | 316 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 317 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
318 | |
319 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 320 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
321 | read_SSDR(reg); |
322 | drv_data->rx += n_bytes; | |
323 | } | |
8d94cc50 SS |
324 | |
325 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
326 | } |
327 | ||
8d94cc50 | 328 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 329 | { |
cf43369d | 330 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 331 | |
4fdb2424 | 332 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
333 | || (drv_data->tx == drv_data->tx_end)) |
334 | return 0; | |
335 | ||
336 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
337 | ++drv_data->tx; | |
338 | ||
339 | return 1; | |
e0c9905e SS |
340 | } |
341 | ||
8d94cc50 | 342 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 343 | { |
cf43369d | 344 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
345 | |
346 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 347 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
348 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
349 | ++drv_data->rx; | |
350 | } | |
8d94cc50 SS |
351 | |
352 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
353 | } |
354 | ||
8d94cc50 | 355 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 356 | { |
cf43369d | 357 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 358 | |
4fdb2424 | 359 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
360 | || (drv_data->tx == drv_data->tx_end)) |
361 | return 0; | |
362 | ||
363 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
364 | drv_data->tx += 2; | |
365 | ||
366 | return 1; | |
e0c9905e SS |
367 | } |
368 | ||
8d94cc50 | 369 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 370 | { |
cf43369d | 371 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
372 | |
373 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 374 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
375 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
376 | drv_data->rx += 2; | |
377 | } | |
8d94cc50 SS |
378 | |
379 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 380 | } |
8d94cc50 SS |
381 | |
382 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 383 | { |
cf43369d | 384 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 385 | |
4fdb2424 | 386 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
387 | || (drv_data->tx == drv_data->tx_end)) |
388 | return 0; | |
389 | ||
390 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
391 | drv_data->tx += 4; | |
392 | ||
393 | return 1; | |
e0c9905e SS |
394 | } |
395 | ||
8d94cc50 | 396 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 397 | { |
cf43369d | 398 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
399 | |
400 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 401 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
402 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
403 | drv_data->rx += 4; | |
404 | } | |
8d94cc50 SS |
405 | |
406 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
407 | } |
408 | ||
cd7bed00 | 409 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
410 | { |
411 | struct spi_message *msg = drv_data->cur_msg; | |
412 | struct spi_transfer *trans = drv_data->cur_transfer; | |
413 | ||
414 | /* Move to next transfer */ | |
415 | if (trans->transfer_list.next != &msg->transfers) { | |
416 | drv_data->cur_transfer = | |
417 | list_entry(trans->transfer_list.next, | |
418 | struct spi_transfer, | |
419 | transfer_list); | |
420 | return RUNNING_STATE; | |
421 | } else | |
422 | return DONE_STATE; | |
423 | } | |
424 | ||
e0c9905e | 425 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 426 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
427 | { |
428 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 429 | struct spi_message *msg; |
e0c9905e | 430 | |
5daa3ba0 SS |
431 | msg = drv_data->cur_msg; |
432 | drv_data->cur_msg = NULL; | |
433 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 434 | |
23e2c2aa | 435 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
436 | transfer_list); |
437 | ||
8423597d NF |
438 | /* Delay if requested before any change in chip select */ |
439 | if (last_transfer->delay_usecs) | |
440 | udelay(last_transfer->delay_usecs); | |
441 | ||
442 | /* Drop chip select UNLESS cs_change is true or we are returning | |
443 | * a message with an error, or next message is for another chip | |
444 | */ | |
e0c9905e | 445 | if (!last_transfer->cs_change) |
a7bb3909 | 446 | cs_deassert(drv_data); |
8423597d NF |
447 | else { |
448 | struct spi_message *next_msg; | |
449 | ||
450 | /* Holding of cs was hinted, but we need to make sure | |
451 | * the next message is for the same chip. Don't waste | |
452 | * time with the following tests unless this was hinted. | |
453 | * | |
454 | * We cannot postpone this until pump_messages, because | |
455 | * after calling msg->complete (below) the driver that | |
456 | * sent the current message could be unloaded, which | |
457 | * could invalidate the cs_control() callback... | |
458 | */ | |
459 | ||
460 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 461 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
462 | |
463 | /* see if the next and current messages point | |
464 | * to the same chip | |
465 | */ | |
466 | if (next_msg && next_msg->spi != msg->spi) | |
467 | next_msg = NULL; | |
468 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 469 | cs_deassert(drv_data); |
8423597d | 470 | } |
e0c9905e | 471 | |
7f86bde9 | 472 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 473 | drv_data->cur_chip = NULL; |
e0c9905e SS |
474 | } |
475 | ||
579d3bb2 SAS |
476 | static void reset_sccr1(struct driver_data *drv_data) |
477 | { | |
478 | void __iomem *reg = drv_data->ioaddr; | |
479 | struct chip_data *chip = drv_data->cur_chip; | |
480 | u32 sccr1_reg; | |
481 | ||
482 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
483 | sccr1_reg &= ~SSCR1_RFT; | |
484 | sccr1_reg |= chip->threshold; | |
485 | write_SSCR1(sccr1_reg, reg); | |
486 | } | |
487 | ||
8d94cc50 | 488 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 489 | { |
cf43369d | 490 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 491 | |
8d94cc50 | 492 | /* Stop and reset SSP */ |
2a8626a9 | 493 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 494 | reset_sccr1(drv_data); |
2a8626a9 | 495 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 496 | write_SSTO(0, reg); |
cd7bed00 | 497 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 498 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 499 | |
8d94cc50 | 500 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 501 | |
8d94cc50 SS |
502 | drv_data->cur_msg->state = ERROR_STATE; |
503 | tasklet_schedule(&drv_data->pump_transfers); | |
504 | } | |
5daa3ba0 | 505 | |
8d94cc50 SS |
506 | static void int_transfer_complete(struct driver_data *drv_data) |
507 | { | |
cf43369d | 508 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 509 | |
8d94cc50 | 510 | /* Stop SSP */ |
2a8626a9 | 511 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 512 | reset_sccr1(drv_data); |
2a8626a9 | 513 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 514 | write_SSTO(0, reg); |
e0c9905e | 515 | |
25985edc | 516 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
517 | drv_data->cur_msg->actual_length += drv_data->len - |
518 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 519 | |
8423597d NF |
520 | /* Transfer delays and chip select release are |
521 | * handled in pump_transfers or giveback | |
522 | */ | |
e0c9905e | 523 | |
8d94cc50 | 524 | /* Move to next transfer */ |
cd7bed00 | 525 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 526 | |
8d94cc50 SS |
527 | /* Schedule transfer tasklet */ |
528 | tasklet_schedule(&drv_data->pump_transfers); | |
529 | } | |
e0c9905e | 530 | |
8d94cc50 SS |
531 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
532 | { | |
cf43369d | 533 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 534 | |
8d94cc50 SS |
535 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
536 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 537 | |
8d94cc50 | 538 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 539 | |
8d94cc50 SS |
540 | if (irq_status & SSSR_ROR) { |
541 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
542 | return IRQ_HANDLED; | |
543 | } | |
e0c9905e | 544 | |
8d94cc50 SS |
545 | if (irq_status & SSSR_TINT) { |
546 | write_SSSR(SSSR_TINT, reg); | |
547 | if (drv_data->read(drv_data)) { | |
548 | int_transfer_complete(drv_data); | |
549 | return IRQ_HANDLED; | |
550 | } | |
551 | } | |
e0c9905e | 552 | |
8d94cc50 SS |
553 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
554 | do { | |
555 | if (drv_data->read(drv_data)) { | |
556 | int_transfer_complete(drv_data); | |
557 | return IRQ_HANDLED; | |
558 | } | |
559 | } while (drv_data->write(drv_data)); | |
e0c9905e | 560 | |
8d94cc50 SS |
561 | if (drv_data->read(drv_data)) { |
562 | int_transfer_complete(drv_data); | |
563 | return IRQ_HANDLED; | |
564 | } | |
e0c9905e | 565 | |
8d94cc50 | 566 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
567 | u32 bytes_left; |
568 | u32 sccr1_reg; | |
569 | ||
570 | sccr1_reg = read_SSCR1(reg); | |
571 | sccr1_reg &= ~SSCR1_TIE; | |
572 | ||
573 | /* | |
574 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 575 | * remaining RX bytes. |
579d3bb2 | 576 | */ |
2a8626a9 | 577 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 578 | u32 rx_thre; |
579d3bb2 | 579 | |
4fdb2424 | 580 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
581 | |
582 | bytes_left = drv_data->rx_end - drv_data->rx; | |
583 | switch (drv_data->n_bytes) { | |
584 | case 4: | |
585 | bytes_left >>= 1; | |
586 | case 2: | |
587 | bytes_left >>= 1; | |
8d94cc50 | 588 | } |
579d3bb2 | 589 | |
4fdb2424 WC |
590 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
591 | if (rx_thre > bytes_left) | |
592 | rx_thre = bytes_left; | |
579d3bb2 | 593 | |
4fdb2424 | 594 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 595 | } |
579d3bb2 | 596 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
597 | } |
598 | ||
5daa3ba0 SS |
599 | /* We did something */ |
600 | return IRQ_HANDLED; | |
e0c9905e SS |
601 | } |
602 | ||
7d12e780 | 603 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 604 | { |
c7bec5ab | 605 | struct driver_data *drv_data = dev_id; |
cf43369d | 606 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 607 | u32 sccr1_reg; |
49cbb1e0 SAS |
608 | u32 mask = drv_data->mask_sr; |
609 | u32 status; | |
610 | ||
7d94a505 MW |
611 | /* |
612 | * The IRQ might be shared with other peripherals so we must first | |
613 | * check that are we RPM suspended or not. If we are we assume that | |
614 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
615 | * interrupt is enabled). | |
616 | */ | |
617 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
618 | return IRQ_NONE; | |
619 | ||
269e4a41 MW |
620 | /* |
621 | * If the device is not yet in RPM suspended state and we get an | |
622 | * interrupt that is meant for another device, check if status bits | |
623 | * are all set to one. That means that the device is already | |
624 | * powered off. | |
625 | */ | |
49cbb1e0 | 626 | status = read_SSSR(reg); |
269e4a41 MW |
627 | if (status == ~0) |
628 | return IRQ_NONE; | |
629 | ||
630 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
631 | |
632 | /* Ignore possible writes if we don't need to write */ | |
633 | if (!(sccr1_reg & SSCR1_TIE)) | |
634 | mask &= ~SSSR_TFS; | |
635 | ||
636 | if (!(status & mask)) | |
637 | return IRQ_NONE; | |
e0c9905e SS |
638 | |
639 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
640 | |
641 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
642 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 643 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 644 | write_SSTO(0, reg); |
2a8626a9 | 645 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 646 | |
f6bd03a7 JN |
647 | dev_err(&drv_data->pdev->dev, |
648 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 649 | |
e0c9905e SS |
650 | /* Never fail */ |
651 | return IRQ_HANDLED; | |
652 | } | |
653 | ||
654 | return drv_data->transfer_handler(drv_data); | |
655 | } | |
656 | ||
3343b7a6 | 657 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 658 | { |
3343b7a6 MW |
659 | unsigned long ssp_clk = drv_data->max_clk_rate; |
660 | const struct ssp_device *ssp = drv_data->ssp; | |
661 | ||
662 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 663 | |
2a8626a9 | 664 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 665 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
666 | else | |
667 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
668 | } | |
669 | ||
e0c9905e SS |
670 | static void pump_transfers(unsigned long data) |
671 | { | |
672 | struct driver_data *drv_data = (struct driver_data *)data; | |
673 | struct spi_message *message = NULL; | |
674 | struct spi_transfer *transfer = NULL; | |
675 | struct spi_transfer *previous = NULL; | |
676 | struct chip_data *chip = NULL; | |
cf43369d | 677 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
678 | u32 clk_div = 0; |
679 | u8 bits = 0; | |
680 | u32 speed = 0; | |
681 | u32 cr0; | |
8d94cc50 SS |
682 | u32 cr1; |
683 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
684 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 685 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
686 | |
687 | /* Get current state information */ | |
688 | message = drv_data->cur_msg; | |
689 | transfer = drv_data->cur_transfer; | |
690 | chip = drv_data->cur_chip; | |
691 | ||
692 | /* Handle for abort */ | |
693 | if (message->state == ERROR_STATE) { | |
694 | message->status = -EIO; | |
5daa3ba0 | 695 | giveback(drv_data); |
e0c9905e SS |
696 | return; |
697 | } | |
698 | ||
699 | /* Handle end of message */ | |
700 | if (message->state == DONE_STATE) { | |
701 | message->status = 0; | |
5daa3ba0 | 702 | giveback(drv_data); |
e0c9905e SS |
703 | return; |
704 | } | |
705 | ||
8423597d | 706 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
707 | if (message->state == RUNNING_STATE) { |
708 | previous = list_entry(transfer->transfer_list.prev, | |
709 | struct spi_transfer, | |
710 | transfer_list); | |
711 | if (previous->delay_usecs) | |
712 | udelay(previous->delay_usecs); | |
8423597d NF |
713 | |
714 | /* Drop chip select only if cs_change is requested */ | |
715 | if (previous->cs_change) | |
a7bb3909 | 716 | cs_deassert(drv_data); |
e0c9905e SS |
717 | } |
718 | ||
cd7bed00 MW |
719 | /* Check if we can DMA this transfer */ |
720 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
721 | |
722 | /* reject already-mapped transfers; PIO won't always work */ | |
723 | if (message->is_dma_mapped | |
724 | || transfer->rx_dma || transfer->tx_dma) { | |
725 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
726 | "pump_transfers: mapped transfer length of " |
727 | "%u is greater than %d\n", | |
7e964455 NF |
728 | transfer->len, MAX_DMA_LEN); |
729 | message->status = -EINVAL; | |
730 | giveback(drv_data); | |
731 | return; | |
732 | } | |
733 | ||
734 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
735 | dev_warn_ratelimited(&message->spi->dev, |
736 | "pump_transfers: DMA disabled for transfer length %ld " | |
737 | "greater than %d\n", | |
738 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
739 | } |
740 | ||
e0c9905e | 741 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 742 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
743 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
744 | message->status = -EIO; | |
5daa3ba0 | 745 | giveback(drv_data); |
e0c9905e SS |
746 | return; |
747 | } | |
9708c121 | 748 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
749 | drv_data->tx = (void *)transfer->tx_buf; |
750 | drv_data->tx_end = drv_data->tx + transfer->len; | |
751 | drv_data->rx = transfer->rx_buf; | |
752 | drv_data->rx_end = drv_data->rx + transfer->len; | |
753 | drv_data->rx_dma = transfer->rx_dma; | |
754 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 755 | drv_data->len = transfer->len; |
e0c9905e SS |
756 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
757 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
758 | |
759 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 760 | cr0 = chip->cr0; |
9708c121 SS |
761 | if (transfer->speed_hz || transfer->bits_per_word) { |
762 | ||
9708c121 SS |
763 | bits = chip->bits_per_word; |
764 | speed = chip->speed_hz; | |
765 | ||
766 | if (transfer->speed_hz) | |
767 | speed = transfer->speed_hz; | |
768 | ||
769 | if (transfer->bits_per_word) | |
770 | bits = transfer->bits_per_word; | |
771 | ||
3343b7a6 | 772 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
773 | |
774 | if (bits <= 8) { | |
775 | drv_data->n_bytes = 1; | |
9708c121 SS |
776 | drv_data->read = drv_data->read != null_reader ? |
777 | u8_reader : null_reader; | |
778 | drv_data->write = drv_data->write != null_writer ? | |
779 | u8_writer : null_writer; | |
780 | } else if (bits <= 16) { | |
781 | drv_data->n_bytes = 2; | |
9708c121 SS |
782 | drv_data->read = drv_data->read != null_reader ? |
783 | u16_reader : null_reader; | |
784 | drv_data->write = drv_data->write != null_writer ? | |
785 | u16_writer : null_writer; | |
786 | } else if (bits <= 32) { | |
787 | drv_data->n_bytes = 4; | |
9708c121 SS |
788 | drv_data->read = drv_data->read != null_reader ? |
789 | u32_reader : null_reader; | |
790 | drv_data->write = drv_data->write != null_writer ? | |
791 | u32_writer : null_writer; | |
792 | } | |
8d94cc50 SS |
793 | /* if bits/word is changed in dma mode, then must check the |
794 | * thresholds and burst also */ | |
795 | if (chip->enable_dma) { | |
cd7bed00 MW |
796 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
797 | message->spi, | |
8d94cc50 SS |
798 | bits, &dma_burst, |
799 | &dma_thresh)) | |
f6bd03a7 JN |
800 | dev_warn_ratelimited(&message->spi->dev, |
801 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 802 | } |
9708c121 | 803 | |
4fdb2424 | 804 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
9708c121 SS |
805 | } |
806 | ||
e0c9905e SS |
807 | message->state = RUNNING_STATE; |
808 | ||
7e964455 | 809 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
810 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
811 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 812 | if (drv_data->dma_mapped) { |
e0c9905e SS |
813 | |
814 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
815 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
816 | ||
817 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 818 | |
8d94cc50 SS |
819 | /* Clear status and start DMA engine */ |
820 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 821 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
822 | |
823 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
824 | } else { |
825 | /* Ensure we have the correct interrupt handler */ | |
826 | drv_data->transfer_handler = interrupt_transfer; | |
827 | ||
8d94cc50 SS |
828 | /* Clear status */ |
829 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 830 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
831 | } |
832 | ||
a0d2642e MW |
833 | if (is_lpss_ssp(drv_data)) { |
834 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
835 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
836 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
837 | write_SSITF(chip->lpss_tx_threshold, reg); | |
838 | } | |
839 | ||
8d94cc50 | 840 | /* see if we need to reload the config registers */ |
4fdb2424 WC |
841 | if ((read_SSCR0(reg) != cr0) || |
842 | (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) { | |
8d94cc50 | 843 | |
b97c74bd | 844 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 845 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 846 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 847 | write_SSTO(chip->timeout, reg); |
b97c74bd | 848 | /* first set CR1 without interrupt and service enables */ |
4fdb2424 | 849 | write_SSCR1(cr1 & change_mask, reg); |
b97c74bd | 850 | /* restart the SSP */ |
8d94cc50 | 851 | write_SSCR0(cr0, reg); |
b97c74bd | 852 | |
8d94cc50 | 853 | } else { |
2a8626a9 | 854 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 855 | write_SSTO(chip->timeout, reg); |
e0c9905e | 856 | } |
b97c74bd | 857 | |
a7bb3909 | 858 | cs_assert(drv_data); |
b97c74bd NF |
859 | |
860 | /* after chip select, release the data by enabling service | |
861 | * requests and interrupts, without changing any mode bits */ | |
862 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
863 | } |
864 | ||
7f86bde9 MW |
865 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
866 | struct spi_message *msg) | |
e0c9905e | 867 | { |
7f86bde9 | 868 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 869 | |
7f86bde9 | 870 | drv_data->cur_msg = msg; |
e0c9905e SS |
871 | /* Initial message state*/ |
872 | drv_data->cur_msg->state = START_STATE; | |
873 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
874 | struct spi_transfer, | |
875 | transfer_list); | |
876 | ||
8d94cc50 SS |
877 | /* prepare to setup the SSP, in pump_transfers, using the per |
878 | * chip configuration */ | |
e0c9905e | 879 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
880 | |
881 | /* Mark as busy and launch transfers */ | |
882 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
883 | return 0; |
884 | } | |
885 | ||
7d94a505 MW |
886 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
887 | { | |
888 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
889 | ||
890 | /* Disable the SSP now */ | |
891 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
892 | drv_data->ioaddr); | |
893 | ||
7d94a505 MW |
894 | return 0; |
895 | } | |
896 | ||
a7bb3909 EM |
897 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
898 | struct pxa2xx_spi_chip *chip_info) | |
899 | { | |
900 | int err = 0; | |
901 | ||
902 | if (chip == NULL || chip_info == NULL) | |
903 | return 0; | |
904 | ||
905 | /* NOTE: setup() can be called multiple times, possibly with | |
906 | * different chip_info, release previously requested GPIO | |
907 | */ | |
908 | if (gpio_is_valid(chip->gpio_cs)) | |
909 | gpio_free(chip->gpio_cs); | |
910 | ||
911 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
912 | if (chip_info->cs_control) { | |
913 | chip->cs_control = chip_info->cs_control; | |
914 | return 0; | |
915 | } | |
916 | ||
917 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
918 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
919 | if (err) { | |
f6bd03a7 JN |
920 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
921 | chip_info->gpio_cs); | |
a7bb3909 EM |
922 | return err; |
923 | } | |
924 | ||
925 | chip->gpio_cs = chip_info->gpio_cs; | |
926 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
927 | ||
928 | err = gpio_direction_output(chip->gpio_cs, | |
929 | !chip->gpio_cs_inverted); | |
930 | } | |
931 | ||
932 | return err; | |
933 | } | |
934 | ||
e0c9905e SS |
935 | static int setup(struct spi_device *spi) |
936 | { | |
937 | struct pxa2xx_spi_chip *chip_info = NULL; | |
938 | struct chip_data *chip; | |
939 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
940 | unsigned int clk_div; | |
a0d2642e MW |
941 | uint tx_thres, tx_hi_thres, rx_thres; |
942 | ||
943 | if (is_lpss_ssp(drv_data)) { | |
944 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
945 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
946 | rx_thres = LPSS_RX_THRESH_DFLT; | |
947 | } else { | |
948 | tx_thres = TX_THRESH_DFLT; | |
949 | tx_hi_thres = 0; | |
950 | rx_thres = RX_THRESH_DFLT; | |
951 | } | |
e0c9905e | 952 | |
8d94cc50 | 953 | /* Only alloc on first setup */ |
e0c9905e | 954 | chip = spi_get_ctldata(spi); |
8d94cc50 | 955 | if (!chip) { |
e0c9905e | 956 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 957 | if (!chip) |
e0c9905e SS |
958 | return -ENOMEM; |
959 | ||
2a8626a9 SAS |
960 | if (drv_data->ssp_type == CE4100_SSP) { |
961 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
962 | dev_err(&spi->dev, |
963 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
964 | kfree(chip); |
965 | return -EINVAL; | |
966 | } | |
967 | ||
968 | chip->frm = spi->chip_select; | |
969 | } else | |
970 | chip->gpio_cs = -1; | |
e0c9905e | 971 | chip->enable_dma = 0; |
f1f640a9 | 972 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
973 | } |
974 | ||
8d94cc50 SS |
975 | /* protocol drivers may change the chip settings, so... |
976 | * if chip_info exists, use it */ | |
977 | chip_info = spi->controller_data; | |
978 | ||
e0c9905e | 979 | /* chip_info isn't always needed */ |
8d94cc50 | 980 | chip->cr1 = 0; |
e0c9905e | 981 | if (chip_info) { |
f1f640a9 VS |
982 | if (chip_info->timeout) |
983 | chip->timeout = chip_info->timeout; | |
984 | if (chip_info->tx_threshold) | |
985 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
986 | if (chip_info->tx_hi_threshold) |
987 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
988 | if (chip_info->rx_threshold) |
989 | rx_thres = chip_info->rx_threshold; | |
990 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 991 | chip->dma_threshold = 0; |
e0c9905e SS |
992 | if (chip_info->enable_loopback) |
993 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
994 | } else if (ACPI_HANDLE(&spi->dev)) { |
995 | /* | |
996 | * Slave devices enumerated from ACPI namespace don't | |
997 | * usually have chip_info but we still might want to use | |
998 | * DMA with them. | |
999 | */ | |
1000 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1001 | } |
1002 | ||
f1f640a9 VS |
1003 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1004 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1005 | ||
a0d2642e MW |
1006 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1007 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1008 | | SSITF_TxHiThresh(tx_hi_thres); | |
1009 | ||
8d94cc50 SS |
1010 | /* set dma burst and threshold outside of chip_info path so that if |
1011 | * chip_info goes away after setting chip->enable_dma, the | |
1012 | * burst and threshold can still respond to changes in bits_per_word */ | |
1013 | if (chip->enable_dma) { | |
1014 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1015 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1016 | spi->bits_per_word, | |
8d94cc50 SS |
1017 | &chip->dma_burst_size, |
1018 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1019 | dev_warn(&spi->dev, |
1020 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1021 | } |
1022 | } | |
1023 | ||
3343b7a6 | 1024 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 1025 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e | 1026 | |
4fdb2424 WC |
1027 | chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, |
1028 | spi->bits_per_word); | |
7f6ee1ad JC |
1029 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1030 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1031 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1032 | |
b833172f MW |
1033 | if (spi->mode & SPI_LOOP) |
1034 | chip->cr1 |= SSCR1_LBM; | |
1035 | ||
e0c9905e | 1036 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 1037 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1038 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1039 | drv_data->max_clk_rate |
c9840daa EM |
1040 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1041 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1042 | else |
7d077197 | 1043 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1044 | drv_data->max_clk_rate / 2 |
c9840daa EM |
1045 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1046 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1047 | |
1048 | if (spi->bits_per_word <= 8) { | |
1049 | chip->n_bytes = 1; | |
e0c9905e SS |
1050 | chip->read = u8_reader; |
1051 | chip->write = u8_writer; | |
1052 | } else if (spi->bits_per_word <= 16) { | |
1053 | chip->n_bytes = 2; | |
e0c9905e SS |
1054 | chip->read = u16_reader; |
1055 | chip->write = u16_writer; | |
1056 | } else if (spi->bits_per_word <= 32) { | |
1057 | chip->cr0 |= SSCR0_EDSS; | |
1058 | chip->n_bytes = 4; | |
e0c9905e SS |
1059 | chip->read = u32_reader; |
1060 | chip->write = u32_writer; | |
e0c9905e | 1061 | } |
9708c121 | 1062 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1063 | |
1064 | spi_set_ctldata(spi, chip); | |
1065 | ||
2a8626a9 SAS |
1066 | if (drv_data->ssp_type == CE4100_SSP) |
1067 | return 0; | |
1068 | ||
a7bb3909 | 1069 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1070 | } |
1071 | ||
0ffa0285 | 1072 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1073 | { |
0ffa0285 | 1074 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1075 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1076 | |
7348d82a DR |
1077 | if (!chip) |
1078 | return; | |
1079 | ||
2a8626a9 | 1080 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1081 | gpio_free(chip->gpio_cs); |
1082 | ||
e0c9905e SS |
1083 | kfree(chip); |
1084 | } | |
1085 | ||
a3496855 | 1086 | #ifdef CONFIG_ACPI |
a3496855 MW |
1087 | static struct pxa2xx_spi_master * |
1088 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1089 | { | |
1090 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1091 | struct acpi_device *adev; |
1092 | struct ssp_device *ssp; | |
1093 | struct resource *res; | |
1094 | int devid; | |
1095 | ||
1096 | if (!ACPI_HANDLE(&pdev->dev) || | |
1097 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1098 | return NULL; | |
1099 | ||
cc0ee987 | 1100 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1101 | if (!pdata) |
a3496855 | 1102 | return NULL; |
a3496855 MW |
1103 | |
1104 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1105 | if (!res) | |
1106 | return NULL; | |
1107 | ||
1108 | ssp = &pdata->ssp; | |
1109 | ||
1110 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1111 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1112 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1113 | return NULL; |
a3496855 MW |
1114 | |
1115 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1116 | ssp->irq = platform_get_irq(pdev, 0); | |
1117 | ssp->type = LPSS_SSP; | |
1118 | ssp->pdev = pdev; | |
1119 | ||
1120 | ssp->port_id = -1; | |
1121 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1122 | ssp->port_id = devid; | |
1123 | ||
1124 | pdata->num_chipselect = 1; | |
cddb339b | 1125 | pdata->enable_dma = true; |
a3496855 MW |
1126 | |
1127 | return pdata; | |
1128 | } | |
1129 | ||
1130 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1131 | { "INT33C0", 0 }, | |
1132 | { "INT33C1", 0 }, | |
54acbd96 MW |
1133 | { "INT3430", 0 }, |
1134 | { "INT3431", 0 }, | |
4b30f2a1 | 1135 | { "80860F0E", 0 }, |
aca26364 | 1136 | { "8086228E", 0 }, |
a3496855 MW |
1137 | { }, |
1138 | }; | |
1139 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1140 | #else | |
1141 | static inline struct pxa2xx_spi_master * | |
1142 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1143 | { | |
1144 | return NULL; | |
1145 | } | |
1146 | #endif | |
1147 | ||
fd4a319b | 1148 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1149 | { |
1150 | struct device *dev = &pdev->dev; | |
1151 | struct pxa2xx_spi_master *platform_info; | |
1152 | struct spi_master *master; | |
65a00a20 | 1153 | struct driver_data *drv_data; |
2f1a74e5 | 1154 | struct ssp_device *ssp; |
65a00a20 | 1155 | int status; |
e0c9905e | 1156 | |
851bacf5 MW |
1157 | platform_info = dev_get_platdata(dev); |
1158 | if (!platform_info) { | |
a3496855 MW |
1159 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1160 | if (!platform_info) { | |
1161 | dev_err(&pdev->dev, "missing platform data\n"); | |
1162 | return -ENODEV; | |
1163 | } | |
851bacf5 | 1164 | } |
e0c9905e | 1165 | |
baffe169 | 1166 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1167 | if (!ssp) |
1168 | ssp = &platform_info->ssp; | |
1169 | ||
1170 | if (!ssp->mmio_base) { | |
1171 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1172 | return -ENODEV; |
1173 | } | |
1174 | ||
1175 | /* Allocate master with space for drv_data and null dma buffer */ | |
1176 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1177 | if (!master) { | |
65a00a20 | 1178 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1179 | pxa_ssp_free(ssp); |
e0c9905e SS |
1180 | return -ENOMEM; |
1181 | } | |
1182 | drv_data = spi_master_get_devdata(master); | |
1183 | drv_data->master = master; | |
1184 | drv_data->master_info = platform_info; | |
1185 | drv_data->pdev = pdev; | |
2f1a74e5 | 1186 | drv_data->ssp = ssp; |
e0c9905e | 1187 | |
21486af0 | 1188 | master->dev.parent = &pdev->dev; |
21486af0 | 1189 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1190 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1191 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1192 | |
851bacf5 | 1193 | master->bus_num = ssp->port_id; |
e0c9905e | 1194 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1195 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1196 | master->cleanup = cleanup; |
1197 | master->setup = setup; | |
7f86bde9 | 1198 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1199 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1200 | master->auto_runtime_pm = true; |
e0c9905e | 1201 | |
2f1a74e5 | 1202 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1203 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1204 | |
2f1a74e5 | 1205 | drv_data->ioaddr = ssp->mmio_base; |
1206 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1207 | if (pxa25x_ssp_comp(drv_data)) { |
24778be2 | 1208 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e0c9905e SS |
1209 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1210 | drv_data->dma_cr1 = 0; | |
1211 | drv_data->clear_sr = SSSR_ROR; | |
1212 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1213 | } else { | |
24778be2 | 1214 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1215 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1216 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1217 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1218 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1219 | } | |
1220 | ||
49cbb1e0 SAS |
1221 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1222 | drv_data); | |
e0c9905e | 1223 | if (status < 0) { |
65a00a20 | 1224 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1225 | goto out_error_master_alloc; |
1226 | } | |
1227 | ||
1228 | /* Setup DMA if requested */ | |
1229 | drv_data->tx_channel = -1; | |
1230 | drv_data->rx_channel = -1; | |
1231 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1232 | status = pxa2xx_spi_dma_setup(drv_data); |
1233 | if (status) { | |
cddb339b | 1234 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1235 | platform_info->enable_dma = false; |
e0c9905e | 1236 | } |
e0c9905e SS |
1237 | } |
1238 | ||
1239 | /* Enable SOC clock */ | |
3343b7a6 MW |
1240 | clk_prepare_enable(ssp->clk); |
1241 | ||
1242 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1243 | |
1244 | /* Load default SSP configuration */ | |
1245 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1246 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1247 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1248 | drv_data->ioaddr); | |
c9840daa | 1249 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1250 | | SSCR0_Motorola |
1251 | | SSCR0_DataSize(8), | |
1252 | drv_data->ioaddr); | |
2a8626a9 | 1253 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1254 | write_SSTO(0, drv_data->ioaddr); |
1255 | write_SSPSP(0, drv_data->ioaddr); | |
1256 | ||
a0d2642e MW |
1257 | lpss_ssp_setup(drv_data); |
1258 | ||
7f86bde9 MW |
1259 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1260 | (unsigned long)drv_data); | |
e0c9905e | 1261 | |
836d1a22 AO |
1262 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1263 | pm_runtime_use_autosuspend(&pdev->dev); | |
1264 | pm_runtime_set_active(&pdev->dev); | |
1265 | pm_runtime_enable(&pdev->dev); | |
1266 | ||
e0c9905e SS |
1267 | /* Register with the SPI framework */ |
1268 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1269 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1270 | if (status != 0) { |
1271 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1272 | goto out_error_clock_enabled; |
e0c9905e SS |
1273 | } |
1274 | ||
1275 | return status; | |
1276 | ||
e0c9905e | 1277 | out_error_clock_enabled: |
3343b7a6 | 1278 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1279 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1280 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1281 | |
1282 | out_error_master_alloc: | |
1283 | spi_master_put(master); | |
baffe169 | 1284 | pxa_ssp_free(ssp); |
e0c9905e SS |
1285 | return status; |
1286 | } | |
1287 | ||
1288 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1289 | { | |
1290 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1291 | struct ssp_device *ssp; |
e0c9905e SS |
1292 | |
1293 | if (!drv_data) | |
1294 | return 0; | |
51e911e2 | 1295 | ssp = drv_data->ssp; |
e0c9905e | 1296 | |
7d94a505 MW |
1297 | pm_runtime_get_sync(&pdev->dev); |
1298 | ||
e0c9905e SS |
1299 | /* Disable the SSP at the peripheral and SOC level */ |
1300 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1301 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1302 | |
1303 | /* Release DMA */ | |
cd7bed00 MW |
1304 | if (drv_data->master_info->enable_dma) |
1305 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1306 | |
7d94a505 MW |
1307 | pm_runtime_put_noidle(&pdev->dev); |
1308 | pm_runtime_disable(&pdev->dev); | |
1309 | ||
e0c9905e | 1310 | /* Release IRQ */ |
2f1a74e5 | 1311 | free_irq(ssp->irq, drv_data); |
1312 | ||
1313 | /* Release SSP */ | |
baffe169 | 1314 | pxa_ssp_free(ssp); |
e0c9905e | 1315 | |
e0c9905e SS |
1316 | return 0; |
1317 | } | |
1318 | ||
1319 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1320 | { | |
1321 | int status = 0; | |
1322 | ||
1323 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1324 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1325 | } | |
1326 | ||
382cebb0 | 1327 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1328 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1329 | { |
86d2593a | 1330 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1331 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1332 | int status = 0; |
1333 | ||
7f86bde9 | 1334 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1335 | if (status != 0) |
1336 | return status; | |
1337 | write_SSCR0(0, drv_data->ioaddr); | |
2b9375b9 DES |
1338 | |
1339 | if (!pm_runtime_suspended(dev)) | |
1340 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1341 | |
1342 | return 0; | |
1343 | } | |
1344 | ||
86d2593a | 1345 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1346 | { |
86d2593a | 1347 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1348 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1349 | int status = 0; |
1350 | ||
cd7bed00 | 1351 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1352 | |
e0c9905e | 1353 | /* Enable the SSP clock */ |
2b9375b9 DES |
1354 | if (!pm_runtime_suspended(dev)) |
1355 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1356 | |
c50325f7 CCE |
1357 | /* Restore LPSS private register bits */ |
1358 | lpss_ssp_setup(drv_data); | |
1359 | ||
e0c9905e | 1360 | /* Start the queue running */ |
7f86bde9 | 1361 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1362 | if (status != 0) { |
86d2593a | 1363 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1364 | return status; |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
7d94a505 MW |
1369 | #endif |
1370 | ||
1371 | #ifdef CONFIG_PM_RUNTIME | |
1372 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1373 | { | |
1374 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1375 | ||
1376 | clk_disable_unprepare(drv_data->ssp->clk); | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1381 | { | |
1382 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1383 | ||
1384 | clk_prepare_enable(drv_data->ssp->clk); | |
1385 | return 0; | |
1386 | } | |
1387 | #endif | |
86d2593a | 1388 | |
47145210 | 1389 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1390 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1391 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1392 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1393 | }; |
e0c9905e SS |
1394 | |
1395 | static struct platform_driver driver = { | |
1396 | .driver = { | |
86d2593a MR |
1397 | .name = "pxa2xx-spi", |
1398 | .owner = THIS_MODULE, | |
86d2593a | 1399 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1400 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1401 | }, |
fbd29a14 | 1402 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1403 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1404 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1405 | }; |
1406 | ||
1407 | static int __init pxa2xx_spi_init(void) | |
1408 | { | |
fbd29a14 | 1409 | return platform_driver_register(&driver); |
e0c9905e | 1410 | } |
5b61a749 | 1411 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1412 | |
1413 | static void __exit pxa2xx_spi_exit(void) | |
1414 | { | |
1415 | platform_driver_unregister(&driver); | |
1416 | } | |
1417 | module_exit(pxa2xx_spi_exit); |