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cd7bed00 MW |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * Copyright (C) 2013, Intel Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef SPI_PXA2XX_H | |
11 | #define SPI_PXA2XX_H | |
12 | ||
5928808e MW |
13 | #include <linux/atomic.h> |
14 | #include <linux/dmaengine.h> | |
cd7bed00 MW |
15 | #include <linux/errno.h> |
16 | #include <linux/io.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/pxa2xx_ssp.h> | |
5928808e MW |
20 | #include <linux/scatterlist.h> |
21 | #include <linux/sizes.h> | |
cd7bed00 MW |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/spi/pxa2xx_spi.h> | |
24 | ||
25 | struct driver_data { | |
26 | /* Driver model hookup */ | |
27 | struct platform_device *pdev; | |
28 | ||
29 | /* SSP Info */ | |
30 | struct ssp_device *ssp; | |
31 | ||
32 | /* SPI framework hookup */ | |
33 | enum pxa_ssp_type ssp_type; | |
34 | struct spi_master *master; | |
35 | ||
36 | /* PXA hookup */ | |
37 | struct pxa2xx_spi_master *master_info; | |
38 | ||
cd7bed00 MW |
39 | /* SSP register addresses */ |
40 | void __iomem *ioaddr; | |
41 | u32 ssdr_physical; | |
42 | ||
43 | /* SSP masks*/ | |
44 | u32 dma_cr1; | |
45 | u32 int_cr1; | |
46 | u32 clear_sr; | |
47 | u32 mask_sr; | |
48 | ||
cd7bed00 MW |
49 | /* Message Transfer pump */ |
50 | struct tasklet_struct pump_transfers; | |
51 | ||
5928808e MW |
52 | /* DMA engine support */ |
53 | struct dma_chan *rx_chan; | |
54 | struct dma_chan *tx_chan; | |
55 | struct sg_table rx_sgt; | |
56 | struct sg_table tx_sgt; | |
57 | int rx_nents; | |
58 | int tx_nents; | |
59 | void *dummy; | |
60 | atomic_t dma_running; | |
61 | ||
cd7bed00 MW |
62 | /* Current message transfer state info */ |
63 | struct spi_message *cur_msg; | |
64 | struct spi_transfer *cur_transfer; | |
65 | struct chip_data *cur_chip; | |
66 | size_t len; | |
67 | void *tx; | |
68 | void *tx_end; | |
69 | void *rx; | |
70 | void *rx_end; | |
71 | int dma_mapped; | |
72 | dma_addr_t rx_dma; | |
73 | dma_addr_t tx_dma; | |
74 | size_t rx_map_len; | |
75 | size_t tx_map_len; | |
76 | u8 n_bytes; | |
77 | int (*write)(struct driver_data *drv_data); | |
78 | int (*read)(struct driver_data *drv_data); | |
79 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); | |
80 | void (*cs_control)(u32 command); | |
a0d2642e MW |
81 | |
82 | void __iomem *lpss_base; | |
cd7bed00 MW |
83 | }; |
84 | ||
85 | struct chip_data { | |
cd7bed00 | 86 | u32 cr1; |
e5262d05 | 87 | u32 dds_rate; |
cd7bed00 MW |
88 | u32 timeout; |
89 | u8 n_bytes; | |
90 | u32 dma_burst_size; | |
91 | u32 threshold; | |
92 | u32 dma_threshold; | |
a0d2642e MW |
93 | u16 lpss_rx_threshold; |
94 | u16 lpss_tx_threshold; | |
cd7bed00 | 95 | u8 enable_dma; |
cd7bed00 MW |
96 | union { |
97 | int gpio_cs; | |
98 | unsigned int frm; | |
99 | }; | |
100 | int gpio_cs_inverted; | |
101 | int (*write)(struct driver_data *drv_data); | |
102 | int (*read)(struct driver_data *drv_data); | |
103 | void (*cs_control)(u32 command); | |
104 | }; | |
105 | ||
c039dd27 JN |
106 | static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, |
107 | unsigned reg) | |
108 | { | |
109 | return __raw_readl(drv_data->ioaddr + reg); | |
110 | } | |
111 | ||
112 | static inline void pxa2xx_spi_write(const struct driver_data *drv_data, | |
113 | unsigned reg, u32 val) | |
114 | { | |
115 | __raw_writel(val, drv_data->ioaddr + reg); | |
116 | } | |
cd7bed00 MW |
117 | |
118 | #define START_STATE ((void *)0) | |
119 | #define RUNNING_STATE ((void *)1) | |
120 | #define DONE_STATE ((void *)2) | |
121 | #define ERROR_STATE ((void *)-1) | |
122 | ||
cd7bed00 MW |
123 | #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) |
124 | #define DMA_ALIGNMENT 8 | |
125 | ||
126 | static inline int pxa25x_ssp_comp(struct driver_data *drv_data) | |
127 | { | |
e5262d05 WC |
128 | switch (drv_data->ssp_type) { |
129 | case PXA25x_SSP: | |
130 | case CE4100_SSP: | |
131 | case QUARK_X1000_SSP: | |
cd7bed00 | 132 | return 1; |
e5262d05 WC |
133 | default: |
134 | return 0; | |
135 | } | |
cd7bed00 MW |
136 | } |
137 | ||
138 | static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) | |
139 | { | |
e5262d05 WC |
140 | if (drv_data->ssp_type == CE4100_SSP || |
141 | drv_data->ssp_type == QUARK_X1000_SSP) | |
c039dd27 | 142 | val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK; |
cd7bed00 | 143 | |
c039dd27 | 144 | pxa2xx_spi_write(drv_data, SSSR, val); |
cd7bed00 MW |
145 | } |
146 | ||
147 | extern int pxa2xx_spi_flush(struct driver_data *drv_data); | |
148 | extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data); | |
149 | ||
5928808e MW |
150 | /* |
151 | * Select the right DMA implementation. | |
152 | */ | |
6356437e | 153 | #if defined(CONFIG_SPI_PXA2XX_DMA) |
5928808e MW |
154 | #define SPI_PXA2XX_USE_DMA 1 |
155 | #define MAX_DMA_LEN SZ_64K | |
156 | #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL) | |
157 | #else | |
158 | #undef SPI_PXA2XX_USE_DMA | |
159 | #define MAX_DMA_LEN 0 | |
160 | #define DEFAULT_DMA_CR1 0 | |
161 | #endif | |
162 | ||
163 | #ifdef SPI_PXA2XX_USE_DMA | |
cd7bed00 MW |
164 | extern bool pxa2xx_spi_dma_is_possible(size_t len); |
165 | extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data); | |
166 | extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data); | |
167 | extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst); | |
168 | extern void pxa2xx_spi_dma_start(struct driver_data *drv_data); | |
169 | extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data); | |
170 | extern void pxa2xx_spi_dma_release(struct driver_data *drv_data); | |
cd7bed00 MW |
171 | extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, |
172 | struct spi_device *spi, | |
173 | u8 bits_per_word, | |
174 | u32 *burst_code, | |
175 | u32 *threshold); | |
176 | #else | |
177 | static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; } | |
178 | static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data) | |
179 | { | |
180 | return 0; | |
181 | } | |
182 | #define pxa2xx_spi_dma_transfer NULL | |
183 | static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data, | |
184 | u32 dma_burst) {} | |
185 | static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {} | |
186 | static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data) | |
187 | { | |
188 | return 0; | |
189 | } | |
190 | static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {} | |
cd7bed00 MW |
191 | static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, |
192 | struct spi_device *spi, | |
193 | u8 bits_per_word, | |
194 | u32 *burst_code, | |
195 | u32 *threshold) | |
196 | { | |
197 | return -ENODEV; | |
198 | } | |
199 | #endif | |
200 | ||
201 | #endif /* SPI_PXA2XX_H */ |