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64ff247a II |
1 | /* |
2 | * Copyright (c) 2008-2014, The Linux foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License rev 2 and | |
6 | * only rev 2 as published by the free Software foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/spi/spi.h> | |
25 | ||
26 | #define QUP_CONFIG 0x0000 | |
27 | #define QUP_STATE 0x0004 | |
28 | #define QUP_IO_M_MODES 0x0008 | |
29 | #define QUP_SW_RESET 0x000c | |
30 | #define QUP_OPERATIONAL 0x0018 | |
31 | #define QUP_ERROR_FLAGS 0x001c | |
32 | #define QUP_ERROR_FLAGS_EN 0x0020 | |
33 | #define QUP_OPERATIONAL_MASK 0x0028 | |
34 | #define QUP_HW_VERSION 0x0030 | |
35 | #define QUP_MX_OUTPUT_CNT 0x0100 | |
36 | #define QUP_OUTPUT_FIFO 0x0110 | |
37 | #define QUP_MX_WRITE_CNT 0x0150 | |
38 | #define QUP_MX_INPUT_CNT 0x0200 | |
39 | #define QUP_MX_READ_CNT 0x0208 | |
40 | #define QUP_INPUT_FIFO 0x0218 | |
41 | ||
42 | #define SPI_CONFIG 0x0300 | |
43 | #define SPI_IO_CONTROL 0x0304 | |
44 | #define SPI_ERROR_FLAGS 0x0308 | |
45 | #define SPI_ERROR_FLAGS_EN 0x030c | |
46 | ||
47 | /* QUP_CONFIG fields */ | |
48 | #define QUP_CONFIG_SPI_MODE (1 << 8) | |
49 | #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13) | |
50 | #define QUP_CONFIG_NO_INPUT BIT(7) | |
51 | #define QUP_CONFIG_NO_OUTPUT BIT(6) | |
52 | #define QUP_CONFIG_N 0x001f | |
53 | ||
54 | /* QUP_STATE fields */ | |
55 | #define QUP_STATE_VALID BIT(2) | |
56 | #define QUP_STATE_RESET 0 | |
57 | #define QUP_STATE_RUN 1 | |
58 | #define QUP_STATE_PAUSE 3 | |
59 | #define QUP_STATE_MASK 3 | |
60 | #define QUP_STATE_CLEAR 2 | |
61 | ||
62 | #define QUP_HW_VERSION_2_1_1 0x20010001 | |
63 | ||
64 | /* QUP_IO_M_MODES fields */ | |
65 | #define QUP_IO_M_PACK_EN BIT(15) | |
66 | #define QUP_IO_M_UNPACK_EN BIT(14) | |
67 | #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12 | |
68 | #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10 | |
69 | #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT) | |
70 | #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT) | |
71 | ||
72 | #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0) | |
73 | #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2) | |
74 | #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5) | |
75 | #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7) | |
76 | ||
77 | #define QUP_IO_M_MODE_FIFO 0 | |
78 | #define QUP_IO_M_MODE_BLOCK 1 | |
79 | #define QUP_IO_M_MODE_DMOV 2 | |
80 | #define QUP_IO_M_MODE_BAM 3 | |
81 | ||
82 | /* QUP_OPERATIONAL fields */ | |
83 | #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) | |
84 | #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) | |
85 | #define QUP_OP_IN_SERVICE_FLAG BIT(9) | |
86 | #define QUP_OP_OUT_SERVICE_FLAG BIT(8) | |
87 | #define QUP_OP_IN_FIFO_FULL BIT(7) | |
88 | #define QUP_OP_OUT_FIFO_FULL BIT(6) | |
89 | #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5) | |
90 | #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4) | |
91 | ||
92 | /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */ | |
93 | #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5) | |
94 | #define QUP_ERROR_INPUT_UNDER_RUN BIT(4) | |
95 | #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3) | |
96 | #define QUP_ERROR_INPUT_OVER_RUN BIT(2) | |
97 | ||
98 | /* SPI_CONFIG fields */ | |
99 | #define SPI_CONFIG_HS_MODE BIT(10) | |
100 | #define SPI_CONFIG_INPUT_FIRST BIT(9) | |
101 | #define SPI_CONFIG_LOOPBACK BIT(8) | |
102 | ||
103 | /* SPI_IO_CONTROL fields */ | |
104 | #define SPI_IO_C_FORCE_CS BIT(11) | |
105 | #define SPI_IO_C_CLK_IDLE_HIGH BIT(10) | |
106 | #define SPI_IO_C_MX_CS_MODE BIT(8) | |
107 | #define SPI_IO_C_CS_N_POLARITY_0 BIT(4) | |
108 | #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2) | |
109 | #define SPI_IO_C_CS_SELECT_MASK 0x000c | |
110 | #define SPI_IO_C_TRISTATE_CS BIT(1) | |
111 | #define SPI_IO_C_NO_TRI_STATE BIT(0) | |
112 | ||
113 | /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */ | |
114 | #define SPI_ERROR_CLK_OVER_RUN BIT(1) | |
115 | #define SPI_ERROR_CLK_UNDER_RUN BIT(0) | |
116 | ||
117 | #define SPI_NUM_CHIPSELECTS 4 | |
118 | ||
119 | /* high speed mode is when bus rate is greater then 26MHz */ | |
120 | #define SPI_HS_MIN_RATE 26000000 | |
121 | #define SPI_MAX_RATE 50000000 | |
122 | ||
123 | #define SPI_DELAY_THRESHOLD 1 | |
124 | #define SPI_DELAY_RETRY 10 | |
125 | ||
64ff247a II |
126 | struct spi_qup { |
127 | void __iomem *base; | |
128 | struct device *dev; | |
129 | struct clk *cclk; /* core clock */ | |
130 | struct clk *iclk; /* interface clock */ | |
131 | int irq; | |
64ff247a II |
132 | spinlock_t lock; |
133 | ||
134 | int in_fifo_sz; | |
135 | int out_fifo_sz; | |
136 | int in_blk_sz; | |
137 | int out_blk_sz; | |
138 | ||
139 | struct spi_transfer *xfer; | |
140 | struct completion done; | |
141 | int error; | |
142 | int w_size; /* bytes per SPI word */ | |
143 | int tx_bytes; | |
144 | int rx_bytes; | |
70cea0a9 | 145 | int qup_v1; |
64ff247a II |
146 | }; |
147 | ||
148 | ||
149 | static inline bool spi_qup_is_valid_state(struct spi_qup *controller) | |
150 | { | |
151 | u32 opstate = readl_relaxed(controller->base + QUP_STATE); | |
152 | ||
153 | return opstate & QUP_STATE_VALID; | |
154 | } | |
155 | ||
156 | static int spi_qup_set_state(struct spi_qup *controller, u32 state) | |
157 | { | |
158 | unsigned long loop; | |
159 | u32 cur_state; | |
160 | ||
161 | loop = 0; | |
162 | while (!spi_qup_is_valid_state(controller)) { | |
163 | ||
164 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
165 | ||
166 | if (++loop > SPI_DELAY_RETRY) | |
167 | return -EIO; | |
168 | } | |
169 | ||
170 | if (loop) | |
171 | dev_dbg(controller->dev, "invalid state for %ld,us %d\n", | |
172 | loop, state); | |
173 | ||
174 | cur_state = readl_relaxed(controller->base + QUP_STATE); | |
175 | /* | |
176 | * Per spec: for PAUSE_STATE to RESET_STATE, two writes | |
177 | * of (b10) are required | |
178 | */ | |
179 | if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) && | |
180 | (state == QUP_STATE_RESET)) { | |
181 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
182 | writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); | |
183 | } else { | |
184 | cur_state &= ~QUP_STATE_MASK; | |
185 | cur_state |= state; | |
186 | writel_relaxed(cur_state, controller->base + QUP_STATE); | |
187 | } | |
188 | ||
189 | loop = 0; | |
190 | while (!spi_qup_is_valid_state(controller)) { | |
191 | ||
192 | usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2); | |
193 | ||
194 | if (++loop > SPI_DELAY_RETRY) | |
195 | return -EIO; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | ||
202 | static void spi_qup_fifo_read(struct spi_qup *controller, | |
203 | struct spi_transfer *xfer) | |
204 | { | |
205 | u8 *rx_buf = xfer->rx_buf; | |
206 | u32 word, state; | |
207 | int idx, shift, w_size; | |
208 | ||
209 | w_size = controller->w_size; | |
210 | ||
211 | while (controller->rx_bytes < xfer->len) { | |
212 | ||
213 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
214 | if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) | |
215 | break; | |
216 | ||
217 | word = readl_relaxed(controller->base + QUP_INPUT_FIFO); | |
218 | ||
219 | if (!rx_buf) { | |
220 | controller->rx_bytes += w_size; | |
221 | continue; | |
222 | } | |
223 | ||
224 | for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) { | |
225 | /* | |
226 | * The data format depends on bytes per SPI word: | |
227 | * 4 bytes: 0x12345678 | |
228 | * 2 bytes: 0x00001234 | |
229 | * 1 byte : 0x00000012 | |
230 | */ | |
231 | shift = BITS_PER_BYTE; | |
232 | shift *= (w_size - idx - 1); | |
233 | rx_buf[controller->rx_bytes] = word >> shift; | |
234 | } | |
235 | } | |
236 | } | |
237 | ||
238 | static void spi_qup_fifo_write(struct spi_qup *controller, | |
239 | struct spi_transfer *xfer) | |
240 | { | |
241 | const u8 *tx_buf = xfer->tx_buf; | |
242 | u32 word, state, data; | |
243 | int idx, w_size; | |
244 | ||
245 | w_size = controller->w_size; | |
246 | ||
247 | while (controller->tx_bytes < xfer->len) { | |
248 | ||
249 | state = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
250 | if (state & QUP_OP_OUT_FIFO_FULL) | |
251 | break; | |
252 | ||
253 | word = 0; | |
254 | for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) { | |
255 | ||
256 | if (!tx_buf) { | |
257 | controller->tx_bytes += w_size; | |
258 | break; | |
259 | } | |
260 | ||
261 | data = tx_buf[controller->tx_bytes]; | |
262 | word |= data << (BITS_PER_BYTE * (3 - idx)); | |
263 | } | |
264 | ||
265 | writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); | |
266 | } | |
267 | } | |
268 | ||
269 | static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) | |
270 | { | |
271 | struct spi_qup *controller = dev_id; | |
272 | struct spi_transfer *xfer; | |
273 | u32 opflags, qup_err, spi_err; | |
274 | unsigned long flags; | |
275 | int error = 0; | |
276 | ||
277 | spin_lock_irqsave(&controller->lock, flags); | |
278 | xfer = controller->xfer; | |
279 | controller->xfer = NULL; | |
280 | spin_unlock_irqrestore(&controller->lock, flags); | |
281 | ||
282 | qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); | |
283 | spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); | |
284 | opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); | |
285 | ||
286 | writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); | |
287 | writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); | |
288 | writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); | |
289 | ||
290 | if (!xfer) { | |
8f391222 | 291 | dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n", |
64ff247a II |
292 | qup_err, spi_err, opflags); |
293 | return IRQ_HANDLED; | |
294 | } | |
295 | ||
296 | if (qup_err) { | |
297 | if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) | |
298 | dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); | |
299 | if (qup_err & QUP_ERROR_INPUT_UNDER_RUN) | |
300 | dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); | |
301 | if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN) | |
302 | dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); | |
303 | if (qup_err & QUP_ERROR_INPUT_OVER_RUN) | |
304 | dev_warn(controller->dev, "INPUT_OVER_RUN\n"); | |
305 | ||
306 | error = -EIO; | |
307 | } | |
308 | ||
309 | if (spi_err) { | |
310 | if (spi_err & SPI_ERROR_CLK_OVER_RUN) | |
311 | dev_warn(controller->dev, "CLK_OVER_RUN\n"); | |
312 | if (spi_err & SPI_ERROR_CLK_UNDER_RUN) | |
313 | dev_warn(controller->dev, "CLK_UNDER_RUN\n"); | |
314 | ||
315 | error = -EIO; | |
316 | } | |
317 | ||
318 | if (opflags & QUP_OP_IN_SERVICE_FLAG) | |
319 | spi_qup_fifo_read(controller, xfer); | |
320 | ||
321 | if (opflags & QUP_OP_OUT_SERVICE_FLAG) | |
322 | spi_qup_fifo_write(controller, xfer); | |
323 | ||
324 | spin_lock_irqsave(&controller->lock, flags); | |
325 | controller->error = error; | |
326 | controller->xfer = xfer; | |
327 | spin_unlock_irqrestore(&controller->lock, flags); | |
328 | ||
329 | if (controller->rx_bytes == xfer->len || error) | |
330 | complete(&controller->done); | |
331 | ||
332 | return IRQ_HANDLED; | |
333 | } | |
334 | ||
335 | ||
336 | /* set clock freq ... bits per word */ | |
00cce74d | 337 | static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) |
64ff247a | 338 | { |
00cce74d | 339 | struct spi_qup *controller = spi_master_get_devdata(spi->master); |
0667dd5f | 340 | u32 config, iomode, mode, control; |
64ff247a II |
341 | int ret, n_words, w_size; |
342 | ||
00cce74d | 343 | if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { |
64ff247a II |
344 | dev_err(controller->dev, "too big size for loopback %d > %d\n", |
345 | xfer->len, controller->in_fifo_sz); | |
346 | return -EIO; | |
347 | } | |
348 | ||
349 | ret = clk_set_rate(controller->cclk, xfer->speed_hz); | |
350 | if (ret) { | |
351 | dev_err(controller->dev, "fail to set frequency %d", | |
352 | xfer->speed_hz); | |
353 | return -EIO; | |
354 | } | |
355 | ||
356 | if (spi_qup_set_state(controller, QUP_STATE_RESET)) { | |
357 | dev_err(controller->dev, "cannot set RESET state\n"); | |
358 | return -EIO; | |
359 | } | |
360 | ||
361 | w_size = 4; | |
362 | if (xfer->bits_per_word <= 8) | |
363 | w_size = 1; | |
364 | else if (xfer->bits_per_word <= 16) | |
365 | w_size = 2; | |
366 | ||
367 | n_words = xfer->len / w_size; | |
368 | controller->w_size = w_size; | |
369 | ||
8f391222 | 370 | if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { |
64ff247a II |
371 | mode = QUP_IO_M_MODE_FIFO; |
372 | writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); | |
373 | writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); | |
374 | /* must be zero for FIFO */ | |
375 | writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); | |
376 | writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); | |
377 | } else { | |
378 | mode = QUP_IO_M_MODE_BLOCK; | |
379 | writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); | |
380 | writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); | |
381 | /* must be zero for BLOCK and BAM */ | |
382 | writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | |
383 | writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | |
384 | } | |
385 | ||
386 | iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); | |
387 | /* Set input and output transfer mode */ | |
388 | iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); | |
389 | iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); | |
390 | iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); | |
391 | iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); | |
392 | ||
393 | writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); | |
394 | ||
0667dd5f II |
395 | control = readl_relaxed(controller->base + SPI_IO_CONTROL); |
396 | ||
397 | if (spi->mode & SPI_CPOL) | |
398 | control |= SPI_IO_C_CLK_IDLE_HIGH; | |
399 | else | |
400 | control &= ~SPI_IO_C_CLK_IDLE_HIGH; | |
401 | ||
402 | writel_relaxed(control, controller->base + SPI_IO_CONTROL); | |
403 | ||
64ff247a II |
404 | config = readl_relaxed(controller->base + SPI_CONFIG); |
405 | ||
00cce74d | 406 | if (spi->mode & SPI_LOOP) |
64ff247a II |
407 | config |= SPI_CONFIG_LOOPBACK; |
408 | else | |
409 | config &= ~SPI_CONFIG_LOOPBACK; | |
410 | ||
00cce74d | 411 | if (spi->mode & SPI_CPHA) |
64ff247a II |
412 | config &= ~SPI_CONFIG_INPUT_FIRST; |
413 | else | |
414 | config |= SPI_CONFIG_INPUT_FIRST; | |
415 | ||
416 | /* | |
417 | * HS_MODE improves signal stability for spi-clk high rates, | |
418 | * but is invalid in loop back mode. | |
419 | */ | |
00cce74d | 420 | if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) |
64ff247a II |
421 | config |= SPI_CONFIG_HS_MODE; |
422 | else | |
423 | config &= ~SPI_CONFIG_HS_MODE; | |
424 | ||
425 | writel_relaxed(config, controller->base + SPI_CONFIG); | |
426 | ||
427 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
428 | config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); | |
429 | config |= xfer->bits_per_word - 1; | |
430 | config |= QUP_CONFIG_SPI_MODE; | |
431 | writel_relaxed(config, controller->base + QUP_CONFIG); | |
432 | ||
70cea0a9 AG |
433 | /* only write to OPERATIONAL_MASK when register is present */ |
434 | if (!controller->qup_v1) | |
435 | writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK); | |
64ff247a II |
436 | return 0; |
437 | } | |
438 | ||
64ff247a II |
439 | static int spi_qup_transfer_one(struct spi_master *master, |
440 | struct spi_device *spi, | |
441 | struct spi_transfer *xfer) | |
442 | { | |
443 | struct spi_qup *controller = spi_master_get_devdata(master); | |
64ff247a II |
444 | unsigned long timeout, flags; |
445 | int ret = -EIO; | |
446 | ||
00cce74d | 447 | ret = spi_qup_io_config(spi, xfer); |
64ff247a II |
448 | if (ret) |
449 | return ret; | |
450 | ||
451 | timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); | |
452 | timeout = DIV_ROUND_UP(xfer->len * 8, timeout); | |
453 | timeout = 100 * msecs_to_jiffies(timeout); | |
454 | ||
455 | reinit_completion(&controller->done); | |
456 | ||
457 | spin_lock_irqsave(&controller->lock, flags); | |
458 | controller->xfer = xfer; | |
459 | controller->error = 0; | |
460 | controller->rx_bytes = 0; | |
461 | controller->tx_bytes = 0; | |
462 | spin_unlock_irqrestore(&controller->lock, flags); | |
463 | ||
464 | if (spi_qup_set_state(controller, QUP_STATE_RUN)) { | |
465 | dev_warn(controller->dev, "cannot set RUN state\n"); | |
466 | goto exit; | |
467 | } | |
468 | ||
469 | if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) { | |
470 | dev_warn(controller->dev, "cannot set PAUSE state\n"); | |
471 | goto exit; | |
472 | } | |
473 | ||
474 | spi_qup_fifo_write(controller, xfer); | |
475 | ||
476 | if (spi_qup_set_state(controller, QUP_STATE_RUN)) { | |
477 | dev_warn(controller->dev, "cannot set EXECUTE state\n"); | |
478 | goto exit; | |
479 | } | |
480 | ||
481 | if (!wait_for_completion_timeout(&controller->done, timeout)) | |
482 | ret = -ETIMEDOUT; | |
483 | exit: | |
484 | spi_qup_set_state(controller, QUP_STATE_RESET); | |
485 | spin_lock_irqsave(&controller->lock, flags); | |
486 | controller->xfer = NULL; | |
487 | if (!ret) | |
488 | ret = controller->error; | |
489 | spin_unlock_irqrestore(&controller->lock, flags); | |
490 | return ret; | |
491 | } | |
492 | ||
64ff247a II |
493 | static int spi_qup_probe(struct platform_device *pdev) |
494 | { | |
495 | struct spi_master *master; | |
496 | struct clk *iclk, *cclk; | |
497 | struct spi_qup *controller; | |
498 | struct resource *res; | |
499 | struct device *dev; | |
500 | void __iomem *base; | |
70cea0a9 | 501 | u32 max_freq, iomode; |
64ff247a II |
502 | int ret, irq, size; |
503 | ||
504 | dev = &pdev->dev; | |
505 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
506 | base = devm_ioremap_resource(dev, res); | |
507 | if (IS_ERR(base)) | |
508 | return PTR_ERR(base); | |
509 | ||
510 | irq = platform_get_irq(pdev, 0); | |
64ff247a II |
511 | if (irq < 0) |
512 | return irq; | |
513 | ||
514 | cclk = devm_clk_get(dev, "core"); | |
515 | if (IS_ERR(cclk)) | |
516 | return PTR_ERR(cclk); | |
517 | ||
518 | iclk = devm_clk_get(dev, "iface"); | |
519 | if (IS_ERR(iclk)) | |
520 | return PTR_ERR(iclk); | |
521 | ||
522 | /* This is optional parameter */ | |
523 | if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) | |
524 | max_freq = SPI_MAX_RATE; | |
525 | ||
526 | if (!max_freq || max_freq > SPI_MAX_RATE) { | |
527 | dev_err(dev, "invalid clock frequency %d\n", max_freq); | |
528 | return -ENXIO; | |
529 | } | |
530 | ||
531 | ret = clk_prepare_enable(cclk); | |
532 | if (ret) { | |
533 | dev_err(dev, "cannot enable core clock\n"); | |
534 | return ret; | |
535 | } | |
536 | ||
537 | ret = clk_prepare_enable(iclk); | |
538 | if (ret) { | |
539 | clk_disable_unprepare(cclk); | |
540 | dev_err(dev, "cannot enable iface clock\n"); | |
541 | return ret; | |
542 | } | |
543 | ||
64ff247a II |
544 | master = spi_alloc_master(dev, sizeof(struct spi_qup)); |
545 | if (!master) { | |
546 | clk_disable_unprepare(cclk); | |
547 | clk_disable_unprepare(iclk); | |
548 | dev_err(dev, "cannot allocate master\n"); | |
549 | return -ENOMEM; | |
550 | } | |
551 | ||
4a8573ab AG |
552 | /* use num-cs unless not present or out of range */ |
553 | if (of_property_read_u16(dev->of_node, "num-cs", | |
554 | &master->num_chipselect) || | |
555 | (master->num_chipselect > SPI_NUM_CHIPSELECTS)) | |
556 | master->num_chipselect = SPI_NUM_CHIPSELECTS; | |
557 | ||
64ff247a II |
558 | master->bus_num = pdev->id; |
559 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
64ff247a | 560 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
cb64ca54 | 561 | master->max_speed_hz = max_freq; |
64ff247a II |
562 | master->transfer_one = spi_qup_transfer_one; |
563 | master->dev.of_node = pdev->dev.of_node; | |
564 | master->auto_runtime_pm = true; | |
565 | ||
566 | platform_set_drvdata(pdev, master); | |
567 | ||
568 | controller = spi_master_get_devdata(master); | |
569 | ||
570 | controller->dev = dev; | |
571 | controller->base = base; | |
572 | controller->iclk = iclk; | |
573 | controller->cclk = cclk; | |
574 | controller->irq = irq; | |
64ff247a | 575 | |
70cea0a9 AG |
576 | /* set v1 flag if device is version 1 */ |
577 | if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) | |
578 | controller->qup_v1 = 1; | |
579 | ||
64ff247a II |
580 | spin_lock_init(&controller->lock); |
581 | init_completion(&controller->done); | |
582 | ||
583 | iomode = readl_relaxed(base + QUP_IO_M_MODES); | |
584 | ||
585 | size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); | |
586 | if (size) | |
587 | controller->out_blk_sz = size * 16; | |
588 | else | |
589 | controller->out_blk_sz = 4; | |
590 | ||
591 | size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); | |
592 | if (size) | |
593 | controller->in_blk_sz = size * 16; | |
594 | else | |
595 | controller->in_blk_sz = 4; | |
596 | ||
597 | size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); | |
598 | controller->out_fifo_sz = controller->out_blk_sz * (2 << size); | |
599 | ||
600 | size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); | |
601 | controller->in_fifo_sz = controller->in_blk_sz * (2 << size); | |
602 | ||
70cea0a9 AG |
603 | dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", |
604 | controller->in_blk_sz, controller->in_fifo_sz, | |
64ff247a II |
605 | controller->out_blk_sz, controller->out_fifo_sz); |
606 | ||
607 | writel_relaxed(1, base + QUP_SW_RESET); | |
608 | ||
609 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
610 | if (ret) { | |
611 | dev_err(dev, "cannot set RESET state\n"); | |
612 | goto error; | |
613 | } | |
614 | ||
615 | writel_relaxed(0, base + QUP_OPERATIONAL); | |
616 | writel_relaxed(0, base + QUP_IO_M_MODES); | |
70cea0a9 AG |
617 | |
618 | if (!controller->qup_v1) | |
619 | writel_relaxed(0, base + QUP_OPERATIONAL_MASK); | |
620 | ||
64ff247a II |
621 | writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, |
622 | base + SPI_ERROR_FLAGS_EN); | |
623 | ||
70cea0a9 AG |
624 | /* if earlier version of the QUP, disable INPUT_OVERRUN */ |
625 | if (controller->qup_v1) | |
626 | writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN | | |
627 | QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, | |
628 | base + QUP_ERROR_FLAGS_EN); | |
629 | ||
64ff247a II |
630 | writel_relaxed(0, base + SPI_CONFIG); |
631 | writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); | |
632 | ||
633 | ret = devm_request_irq(dev, irq, spi_qup_qup_irq, | |
634 | IRQF_TRIGGER_HIGH, pdev->name, controller); | |
635 | if (ret) | |
636 | goto error; | |
637 | ||
64ff247a II |
638 | pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); |
639 | pm_runtime_use_autosuspend(dev); | |
640 | pm_runtime_set_active(dev); | |
641 | pm_runtime_enable(dev); | |
045c243a AG |
642 | |
643 | ret = devm_spi_register_master(dev, master); | |
644 | if (ret) | |
645 | goto disable_pm; | |
646 | ||
64ff247a II |
647 | return 0; |
648 | ||
045c243a AG |
649 | disable_pm: |
650 | pm_runtime_disable(&pdev->dev); | |
64ff247a II |
651 | error: |
652 | clk_disable_unprepare(cclk); | |
653 | clk_disable_unprepare(iclk); | |
654 | spi_master_put(master); | |
655 | return ret; | |
656 | } | |
657 | ||
ec833050 | 658 | #ifdef CONFIG_PM |
64ff247a II |
659 | static int spi_qup_pm_suspend_runtime(struct device *device) |
660 | { | |
661 | struct spi_master *master = dev_get_drvdata(device); | |
662 | struct spi_qup *controller = spi_master_get_devdata(master); | |
663 | u32 config; | |
664 | ||
665 | /* Enable clocks auto gaiting */ | |
666 | config = readl(controller->base + QUP_CONFIG); | |
f0ceb114 | 667 | config |= QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a II |
668 | writel_relaxed(config, controller->base + QUP_CONFIG); |
669 | return 0; | |
670 | } | |
671 | ||
672 | static int spi_qup_pm_resume_runtime(struct device *device) | |
673 | { | |
674 | struct spi_master *master = dev_get_drvdata(device); | |
675 | struct spi_qup *controller = spi_master_get_devdata(master); | |
676 | u32 config; | |
677 | ||
678 | /* Disable clocks auto gaiting */ | |
679 | config = readl_relaxed(controller->base + QUP_CONFIG); | |
f0ceb114 | 680 | config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; |
64ff247a II |
681 | writel_relaxed(config, controller->base + QUP_CONFIG); |
682 | return 0; | |
683 | } | |
ec833050 | 684 | #endif /* CONFIG_PM */ |
64ff247a II |
685 | |
686 | #ifdef CONFIG_PM_SLEEP | |
687 | static int spi_qup_suspend(struct device *device) | |
688 | { | |
689 | struct spi_master *master = dev_get_drvdata(device); | |
690 | struct spi_qup *controller = spi_master_get_devdata(master); | |
691 | int ret; | |
692 | ||
693 | ret = spi_master_suspend(master); | |
694 | if (ret) | |
695 | return ret; | |
696 | ||
697 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
698 | if (ret) | |
699 | return ret; | |
700 | ||
701 | clk_disable_unprepare(controller->cclk); | |
702 | clk_disable_unprepare(controller->iclk); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static int spi_qup_resume(struct device *device) | |
707 | { | |
708 | struct spi_master *master = dev_get_drvdata(device); | |
709 | struct spi_qup *controller = spi_master_get_devdata(master); | |
710 | int ret; | |
711 | ||
712 | ret = clk_prepare_enable(controller->iclk); | |
713 | if (ret) | |
714 | return ret; | |
715 | ||
716 | ret = clk_prepare_enable(controller->cclk); | |
717 | if (ret) | |
718 | return ret; | |
719 | ||
720 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
721 | if (ret) | |
722 | return ret; | |
723 | ||
724 | return spi_master_resume(master); | |
725 | } | |
726 | #endif /* CONFIG_PM_SLEEP */ | |
727 | ||
728 | static int spi_qup_remove(struct platform_device *pdev) | |
729 | { | |
730 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | |
731 | struct spi_qup *controller = spi_master_get_devdata(master); | |
732 | int ret; | |
733 | ||
734 | ret = pm_runtime_get_sync(&pdev->dev); | |
3d89e141 | 735 | if (ret < 0) |
64ff247a II |
736 | return ret; |
737 | ||
738 | ret = spi_qup_set_state(controller, QUP_STATE_RESET); | |
739 | if (ret) | |
740 | return ret; | |
741 | ||
742 | clk_disable_unprepare(controller->cclk); | |
743 | clk_disable_unprepare(controller->iclk); | |
744 | ||
745 | pm_runtime_put_noidle(&pdev->dev); | |
746 | pm_runtime_disable(&pdev->dev); | |
64ff247a II |
747 | return 0; |
748 | } | |
749 | ||
113b1a07 | 750 | static const struct of_device_id spi_qup_dt_match[] = { |
70cea0a9 | 751 | { .compatible = "qcom,spi-qup-v1.1.1", }, |
64ff247a II |
752 | { .compatible = "qcom,spi-qup-v2.1.1", }, |
753 | { .compatible = "qcom,spi-qup-v2.2.1", }, | |
754 | { } | |
755 | }; | |
756 | MODULE_DEVICE_TABLE(of, spi_qup_dt_match); | |
757 | ||
758 | static const struct dev_pm_ops spi_qup_dev_pm_ops = { | |
759 | SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume) | |
760 | SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime, | |
761 | spi_qup_pm_resume_runtime, | |
762 | NULL) | |
763 | }; | |
764 | ||
765 | static struct platform_driver spi_qup_driver = { | |
766 | .driver = { | |
767 | .name = "spi_qup", | |
64ff247a II |
768 | .pm = &spi_qup_dev_pm_ops, |
769 | .of_match_table = spi_qup_dt_match, | |
770 | }, | |
771 | .probe = spi_qup_probe, | |
772 | .remove = spi_qup_remove, | |
773 | }; | |
774 | module_platform_driver(spi_qup_driver); | |
775 | ||
776 | MODULE_LICENSE("GPL v2"); | |
64ff247a | 777 | MODULE_ALIAS("platform:spi_qup"); |