projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spi: rspi: Add more RSPI register documentation
[deliverable/linux.git] / drivers / spi / spi-rspi.c
CommitLineData
0b2182dd
SY		 1/*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
31#include <linux/platform_device.h>
32#include <linux/io.h>
33#include <linux/clk.h>
a3633fe7
SY		 34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/sh_dma.h>
0b2182dd 37#include <linux/spi/spi.h>
a3633fe7 38#include <linux/spi/rspi.h>
0b2182dd 39
6ab4865b
GU		 40#define RSPI_SPCR 0x00 /* Control Register */
41#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
42#define RSPI_SPPCR 0x02 /* Pin Control Register */
43#define RSPI_SPSR 0x03 /* Status Register */
44#define RSPI_SPDR 0x04 /* Data Register */
45#define RSPI_SPSCR 0x08 /* Sequence Control Register */
46#define RSPI_SPSSR 0x09 /* Sequence Status Register */
47#define RSPI_SPBR 0x0a /* Bit Rate Register */
48#define RSPI_SPDCR 0x0b /* Data Control Register */
49#define RSPI_SPCKD 0x0c /* Clock Delay Register */
50#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
51#define RSPI_SPND 0x0e /* Next-Access Delay Register */
52#define RSPI_SPCR2 0x0f /* Control Register 2 */
53#define RSPI_SPCMD0 0x10 /* Command Register 0 */
54#define RSPI_SPCMD1 0x12 /* Command Register 1 */
55#define RSPI_SPCMD2 0x14 /* Command Register 2 */
56#define RSPI_SPCMD3 0x16 /* Command Register 3 */
57#define RSPI_SPCMD4 0x18 /* Command Register 4 */
58#define RSPI_SPCMD5 0x1a /* Command Register 5 */
59#define RSPI_SPCMD6 0x1c /* Command Register 6 */
60#define RSPI_SPCMD7 0x1e /* Command Register 7 */
61#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
62#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
0b2182dd 63
5ce0ba88
HCM		 64/*qspi only */
65#define QSPI_SPBFCR 0x18
66#define QSPI_SPBDCR 0x1a
67#define QSPI_SPBMUL0 0x1c
68#define QSPI_SPBMUL1 0x20
69#define QSPI_SPBMUL2 0x24
70#define QSPI_SPBMUL3 0x28
71
6ab4865b
GU		 72/* SPCR - Control Register */
73#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
74#define SPCR_SPE 0x40 /* Function Enable */
75#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
76#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
77#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
78#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
79/* RSPI on SH only */
80#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
81#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
82
83/* SSLP - Slave Select Polarity Register */
84#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
85#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
86
87/* SPPCR - Pin Control Register */
88#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
89#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
0b2182dd 90#define SPPCR_SPOM 0x04
6ab4865b
GU		 91#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
92#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
93
94/* SPSR - Status Register */
95#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
96#define SPSR_TEND 0x40 /* Transmit End */
97#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
98#define SPSR_PERF 0x08 /* Parity Error Flag */
99#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
100#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
101#define SPSR_OVRF 0x01 /* Overrun Error Flag */
102
103/* SPSCR - Sequence Control Register */
104#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
105
106/* SPSSR - Sequence Status Register */
107#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
108#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
109
110/* SPDCR - Data Control Register */
111#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
112#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
113#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
114#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
115#define SPDCR_SPLWORD SPDCR_SPLW1
116#define SPDCR_SPLBYTE SPDCR_SPLW0
117#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
118#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */
0b2182dd
SY		 119#define SPDCR_SLSEL1 0x08
120#define SPDCR_SLSEL0 0x04
6ab4865b 121#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */
0b2182dd
SY		 122#define SPDCR_SPFC1 0x02
123#define SPDCR_SPFC0 0x01
6ab4865b 124#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */
0b2182dd 125
6ab4865b
GU		 126/* SPCKD - Clock Delay Register */
127#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
0b2182dd 128
6ab4865b
GU		 129/* SSLND - Slave Select Negation Delay Register */
130#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
0b2182dd 131
6ab4865b
GU		 132/* SPND - Next-Access Delay Register */
133#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
0b2182dd 134
6ab4865b
GU		 135/* SPCR2 - Control Register 2 */
136#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
137#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
138#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
139#define SPCR2_SPPE 0x01 /* Parity Enable */
0b2182dd 140
6ab4865b
GU		 141/* SPCMDn - Command Registers */
142#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
143#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
144#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
145#define SPCMD_LSBF 0x1000 /* LSB First */
146#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
0b2182dd 147#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
5ce0ba88
HCM		 148#define SPCMD_SPB_8BIT 0x0000 /* qspi only */
149#define SPCMD_SPB_16BIT 0x0100
0b2182dd
SY		 150#define SPCMD_SPB_20BIT 0x0000
151#define SPCMD_SPB_24BIT 0x0100
152#define SPCMD_SPB_32BIT 0x0200
6ab4865b
GU		 153#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
154#define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
155#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
156#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
157#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
158
159/* SPBFCR - Buffer Control Register */
160#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */
161#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */
162#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
163#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
5ce0ba88 164
2aae80b2
GU		 165#define DUMMY_DATA 0x00
166
0b2182dd
SY		 167struct rspi_data {
168 void __iomem *addr;
169 u32 max_speed_hz;
170 struct spi_master *master;
171 struct list_head queue;
172 struct work_struct ws;
173 wait_queue_head_t wait;
174 spinlock_t lock;
175 struct clk *clk;
97b95c11 176 u8 spsr;
5ce0ba88 177 const struct spi_ops *ops;
a3633fe7
SY		 178
179 /* for dmaengine */
a3633fe7
SY		 180 struct dma_chan *chan_tx;
181 struct dma_chan *chan_rx;
182 int irq;
183
184 unsigned dma_width_16bit:1;
185 unsigned dma_callbacked:1;
0b2182dd
SY		 186};
187
baf588f4 188static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
0b2182dd
SY		 189{
190 iowrite8(data, rspi->addr + offset);
191}
192
baf588f4 193static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
0b2182dd
SY		 194{
195 iowrite16(data, rspi->addr + offset);
196}
197
baf588f4 198static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
5ce0ba88
HCM		 199{
200 iowrite32(data, rspi->addr + offset);
201}
202
baf588f4 203static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
0b2182dd
SY		 204{
205 return ioread8(rspi->addr + offset);
206}
207
baf588f4 208static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
0b2182dd
SY		 209{
210 return ioread16(rspi->addr + offset);
211}
212
5ce0ba88
HCM		 213/* optional functions */
214struct spi_ops {
baf588f4
GU		 215 int (*set_config_register)(const struct rspi_data *rspi,
216 int access_size);
cb52c673
HCM		 217 int (*send_pio)(struct rspi_data *rspi, struct spi_message *mesg,
218 struct spi_transfer *t);
219 int (*receive_pio)(struct rspi_data *rspi, struct spi_message *mesg,
220 struct spi_transfer *t);
221
5ce0ba88
HCM		 222};
223
224/*
225 * functions for RSPI
226 */
baf588f4
GU		 227static int rspi_set_config_register(const struct rspi_data *rspi,
228 int access_size)
0b2182dd 229{
5ce0ba88
HCM		 230 int spbr;
231
232 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
233 rspi_write8(rspi, 0x00, RSPI_SPPCR);
0b2182dd 234
5ce0ba88
HCM		 235 /* Sets transfer bit rate */
236 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
237 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
238
239 /* Sets number of frames to be used: 1 frame */
240 rspi_write8(rspi, 0x00, RSPI_SPDCR);
0b2182dd 241
5ce0ba88
HCM		 242 /* Sets RSPCK, SSL, next-access delay value */
243 rspi_write8(rspi, 0x00, RSPI_SPCKD);
244 rspi_write8(rspi, 0x00, RSPI_SSLND);
245 rspi_write8(rspi, 0x00, RSPI_SPND);
246
247 /* Sets parity, interrupt mask */
248 rspi_write8(rspi, 0x00, RSPI_SPCR2);
249
250 /* Sets SPCMD */
251 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
252 RSPI_SPCMD0);
253
254 /* Sets RSPI mode */
255 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
256
257 return 0;
0b2182dd
SY		 258}
259
5ce0ba88
HCM		 260/*
261 * functions for QSPI
262 */
baf588f4
GU		 263static int qspi_set_config_register(const struct rspi_data *rspi,
264 int access_size)
5ce0ba88
HCM		 265{
266 u16 spcmd;
267 int spbr;
268
269 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
270 rspi_write8(rspi, 0x00, RSPI_SPPCR);
271
272 /* Sets transfer bit rate */
273 spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz);
274 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
275
276 /* Sets number of frames to be used: 1 frame */
277 rspi_write8(rspi, 0x00, RSPI_SPDCR);
278
279 /* Sets RSPCK, SSL, next-access delay value */
280 rspi_write8(rspi, 0x00, RSPI_SPCKD);
281 rspi_write8(rspi, 0x00, RSPI_SSLND);
282 rspi_write8(rspi, 0x00, RSPI_SPND);
283
284 /* Data Length Setting */
285 if (access_size == 8)
286 spcmd = SPCMD_SPB_8BIT;
287 else if (access_size == 16)
288 spcmd = SPCMD_SPB_16BIT;
289 else if (access_size == 32)
290 spcmd = SPCMD_SPB_32BIT;
291
292 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN;
293
294 /* Resets transfer data length */
295 rspi_write32(rspi, 0, QSPI_SPBMUL0);
296
297 /* Resets transmit and receive buffer */
298 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
299 /* Sets buffer to allow normal operation */
300 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
301
302 /* Sets SPCMD */
303 rspi_write16(rspi, spcmd, RSPI_SPCMD0);
304
305 /* Enables SPI function in a master mode */
306 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
307
308 return 0;
309}
310
311#define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
312
baf588f4 313static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
0b2182dd
SY		 314{
315 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
316}
317
baf588f4 318static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
0b2182dd
SY		 319{
320 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
321}
322
323static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
324 u8 enable_bit)
325{
326 int ret;
327
328 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
329 rspi_enable_irq(rspi, enable_bit);
330 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
331 if (ret == 0 && !(rspi->spsr & wait_mask))
332 return -ETIMEDOUT;
333
334 return 0;
335}
336
baf588f4 337static void rspi_assert_ssl(const struct rspi_data *rspi)
0b2182dd
SY		 338{
339 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
340}
341
baf588f4 342static void rspi_negate_ssl(const struct rspi_data *rspi)
0b2182dd
SY		 343{
344 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
345}
346
0b2182dd
SY		 347static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
348 struct spi_transfer *t)
349{
350 int remain = t->len;
c132f094 351 const u8 *data = t->tx_buf;
0b2182dd
SY		 352 while (remain > 0) {
353 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
354 RSPI_SPCR);
355
356 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
357 dev_err(&rspi->master->dev,
358 "%s: tx empty timeout\n", __func__);
359 return -ETIMEDOUT;
360 }
361
362 rspi_write16(rspi, *data, RSPI_SPDR);
363 data++;
364 remain--;
365 }
366
367 /* Waiting for the last transmition */
368 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
369
370 return 0;
371}
372
cb52c673
HCM		 373static int qspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
374 struct spi_transfer *t)
375{
376 int remain = t->len;
c132f094 377 const u8 *data = t->tx_buf;
cb52c673
HCM		 378
379 rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR);
380 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
381
cb52c673
HCM		 382 while (remain > 0) {
383
384 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
385 dev_err(&rspi->master->dev,
386 "%s: tx empty timeout\n", __func__);
387 return -ETIMEDOUT;
388 }
389 rspi_write8(rspi, *data++, RSPI_SPDR);
390
391 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
392 dev_err(&rspi->master->dev,
393 "%s: receive timeout\n", __func__);
394 return -ETIMEDOUT;
395 }
396 rspi_read8(rspi, RSPI_SPDR);
397
398 remain--;
399 }
400
401 /* Waiting for the last transmition */
402 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
403
404 return 0;
405}
406
407#define send_pio(spi, mesg, t) spi->ops->send_pio(spi, mesg, t)
408
a3633fe7
SY		 409static void rspi_dma_complete(void *arg)
410{
411 struct rspi_data *rspi = arg;
412
413 rspi->dma_callbacked = 1;
414 wake_up_interruptible(&rspi->wait);
415}
416
c132f094
GU		 417static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
418 unsigned len, struct dma_chan *chan,
a3633fe7
SY		 419 enum dma_transfer_direction dir)
420{
421 sg_init_table(sg, 1);
422 sg_set_buf(sg, buf, len);
423 sg_dma_len(sg) = len;
424 return dma_map_sg(chan->device->dev, sg, 1, dir);
425}
426
427static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
428 enum dma_transfer_direction dir)
429{
430 dma_unmap_sg(chan->device->dev, sg, 1, dir);
431}
432
433static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len)
434{
435 u16 *dst = buf;
436 const u8 *src = data;
437
438 while (len) {
439 *dst++ = (u16)(*src++);
440 len--;
441 }
442}
443
444static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
445{
446 u8 *dst = buf;
447 const u16 *src = data;
448
449 while (len) {
450 *dst++ = (u8)*src++;
451 len--;
452 }
453}
454
455static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
456{
457 struct scatterlist sg;
c132f094 458 const void *buf = NULL;
a3633fe7
SY		 459 struct dma_async_tx_descriptor *desc;
460 unsigned len;
461 int ret = 0;
462
463 if (rspi->dma_width_16bit) {
c132f094 464 void *tmp;
a3633fe7
SY		 465 /*
466 * If DMAC bus width is 16-bit, the driver allocates a dummy
467 * buffer. And, the driver converts original data into the
468 * DMAC data as the following format:
469 * original data: 1st byte, 2nd byte ...
470 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
471 */
472 len = t->len * 2;
c132f094
GU		 473 tmp = kmalloc(len, GFP_KERNEL);
474 if (!tmp)
a3633fe7 475 return -ENOMEM;
c132f094
GU		 476 rspi_memory_to_8bit(tmp, t->tx_buf, t->len);
477 buf = tmp;
a3633fe7
SY		 478 } else {
479 len = t->len;
c132f094 480 buf = t->tx_buf;
a3633fe7
SY		 481 }
482
483 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
484 ret = -EFAULT;
485 goto end_nomap;
486 }
487 desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 if (!desc) {
490 ret = -EIO;
491 goto end;
492 }
493
494 /*
495 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
496 * called. So, this driver disables the IRQ while DMA transfer.
497 */
498 disable_irq(rspi->irq);
499
500 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
501 rspi_enable_irq(rspi, SPCR_SPTIE);
502 rspi->dma_callbacked = 0;
503
504 desc->callback = rspi_dma_complete;
505 desc->callback_param = rspi;
506 dmaengine_submit(desc);
507 dma_async_issue_pending(rspi->chan_tx);
508
509 ret = wait_event_interruptible_timeout(rspi->wait,
510 rspi->dma_callbacked, HZ);
511 if (ret > 0 && rspi->dma_callbacked)
512 ret = 0;
513 else if (!ret)
514 ret = -ETIMEDOUT;
515 rspi_disable_irq(rspi, SPCR_SPTIE);
516
517 enable_irq(rspi->irq);
518
519end:
520 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
521end_nomap:
522 if (rspi->dma_width_16bit)
523 kfree(buf);
524
525 return ret;
526}
527
baf588f4 528static void rspi_receive_init(const struct rspi_data *rspi)
0b2182dd 529{
97b95c11 530 u8 spsr;
0b2182dd
SY		 531
532 spsr = rspi_read8(rspi, RSPI_SPSR);
533 if (spsr & SPSR_SPRF)
534 rspi_read16(rspi, RSPI_SPDR); /* dummy read */
535 if (spsr & SPSR_OVRF)
536 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
537 RSPI_SPCR);
a3633fe7
SY		 538}
539
540static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
541 struct spi_transfer *t)
542{
543 int remain = t->len;
544 u8 *data;
545
546 rspi_receive_init(rspi);
0b2182dd 547
c132f094 548 data = t->rx_buf;
0b2182dd
SY		 549 while (remain > 0) {
550 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
551 RSPI_SPCR);
552
553 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
554 dev_err(&rspi->master->dev,
555 "%s: tx empty timeout\n", __func__);
556 return -ETIMEDOUT;
557 }
558 /* dummy write for generate clock */
2aae80b2 559 rspi_write16(rspi, DUMMY_DATA, RSPI_SPDR);
0b2182dd
SY		 560
561 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
562 dev_err(&rspi->master->dev,
563 "%s: receive timeout\n", __func__);
564 return -ETIMEDOUT;
565 }
566 /* SPDR allows 16 or 32-bit access only */
567 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
568
569 data++;
570 remain--;
571 }
572
573 return 0;
574}
575
baf588f4 576static void qspi_receive_init(const struct rspi_data *rspi)
cb52c673 577{
97b95c11 578 u8 spsr;
cb52c673
HCM		 579
580 spsr = rspi_read8(rspi, RSPI_SPSR);
581 if (spsr & SPSR_SPRF)
582 rspi_read8(rspi, RSPI_SPDR); /* dummy read */
583 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
584 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
585}
586
587static int qspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
588 struct spi_transfer *t)
589{
590 int remain = t->len;
591 u8 *data;
592
593 qspi_receive_init(rspi);
594
c132f094 595 data = t->rx_buf;
cb52c673
HCM		 596 while (remain > 0) {
597
598 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
599 dev_err(&rspi->master->dev,
600 "%s: tx empty timeout\n", __func__);
601 return -ETIMEDOUT;
602 }
603 /* dummy write for generate clock */
2aae80b2 604 rspi_write8(rspi, DUMMY_DATA, RSPI_SPDR);
cb52c673
HCM		 605
606 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
607 dev_err(&rspi->master->dev,
608 "%s: receive timeout\n", __func__);
609 return -ETIMEDOUT;
610 }
611 /* SPDR allows 8, 16 or 32-bit access */
612 *data++ = rspi_read8(rspi, RSPI_SPDR);
613 remain--;
614 }
615
616 return 0;
617}
618
619#define receive_pio(spi, mesg, t) spi->ops->receive_pio(spi, mesg, t)
620
a3633fe7
SY		 621static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
622{
623 struct scatterlist sg, sg_dummy;
624 void *dummy = NULL, *rx_buf = NULL;
625 struct dma_async_tx_descriptor *desc, *desc_dummy;
626 unsigned len;
627 int ret = 0;
628
629 if (rspi->dma_width_16bit) {
630 /*
631 * If DMAC bus width is 16-bit, the driver allocates a dummy
632 * buffer. And, finally the driver converts the DMAC data into
633 * actual data as the following format:
634 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
635 * actual data: 1st byte, 2nd byte ...
636 */
637 len = t->len * 2;
638 rx_buf = kmalloc(len, GFP_KERNEL);
639 if (!rx_buf)
640 return -ENOMEM;
641 } else {
642 len = t->len;
643 rx_buf = t->rx_buf;
644 }
645
646 /* prepare dummy transfer to generate SPI clocks */
647 dummy = kzalloc(len, GFP_KERNEL);
648 if (!dummy) {
649 ret = -ENOMEM;
650 goto end_nomap;
651 }
652 if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx,
653 DMA_TO_DEVICE)) {
654 ret = -EFAULT;
655 goto end_nomap;
656 }
657 desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1,
658 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
659 if (!desc_dummy) {
660 ret = -EIO;
661 goto end_dummy_mapped;
662 }
663
664 /* prepare receive transfer */
665 if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx,
666 DMA_FROM_DEVICE)) {
667 ret = -EFAULT;
668 goto end_dummy_mapped;
669
670 }
671 desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE,
672 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
673 if (!desc) {
674 ret = -EIO;
675 goto end;
676 }
677
678 rspi_receive_init(rspi);
679
680 /*
681 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
682 * called. So, this driver disables the IRQ while DMA transfer.
683 */
684 disable_irq(rspi->irq);
685
686 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
687 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
688 rspi->dma_callbacked = 0;
689
690 desc->callback = rspi_dma_complete;
691 desc->callback_param = rspi;
692 dmaengine_submit(desc);
693 dma_async_issue_pending(rspi->chan_rx);
694
695 desc_dummy->callback = NULL; /* No callback */
696 dmaengine_submit(desc_dummy);
697 dma_async_issue_pending(rspi->chan_tx);
698
699 ret = wait_event_interruptible_timeout(rspi->wait,
700 rspi->dma_callbacked, HZ);
701 if (ret > 0 && rspi->dma_callbacked)
702 ret = 0;
703 else if (!ret)
704 ret = -ETIMEDOUT;
705 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
706
707 enable_irq(rspi->irq);
708
709end:
710 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
711end_dummy_mapped:
712 rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE);
713end_nomap:
714 if (rspi->dma_width_16bit) {
715 if (!ret)
716 rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len);
717 kfree(rx_buf);
718 }
719 kfree(dummy);
720
721 return ret;
722}
723
baf588f4 724static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
a3633fe7
SY		 725{
726 if (t->tx_buf && rspi->chan_tx)
727 return 1;
728 /* If the module receives data by DMAC, it also needs TX DMAC */
729 if (t->rx_buf && rspi->chan_tx && rspi->chan_rx)
730 return 1;
731
732 return 0;
733}
734
0b2182dd
SY		 735static void rspi_work(struct work_struct *work)
736{
737 struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
738 struct spi_message *mesg;
739 struct spi_transfer *t;
740 unsigned long flags;
741 int ret;
742
8d4d08ce
SY		 743 while (1) {
744 spin_lock_irqsave(&rspi->lock, flags);
745 if (list_empty(&rspi->queue)) {
746 spin_unlock_irqrestore(&rspi->lock, flags);
747 break;
748 }
0b2182dd
SY		 749 mesg = list_entry(rspi->queue.next, struct spi_message, queue);
750 list_del_init(&mesg->queue);
751 spin_unlock_irqrestore(&rspi->lock, flags);
752
753 rspi_assert_ssl(rspi);
754
755 list_for_each_entry(t, &mesg->transfers, transfer_list) {
756 if (t->tx_buf) {
a3633fe7
SY		 757 if (rspi_is_dma(rspi, t))
758 ret = rspi_send_dma(rspi, t);
759 else
cb52c673 760 ret = send_pio(rspi, mesg, t);
0b2182dd
SY		 761 if (ret < 0)
762 goto error;
763 }
764 if (t->rx_buf) {
a3633fe7
SY		 765 if (rspi_is_dma(rspi, t))
766 ret = rspi_receive_dma(rspi, t);
767 else
cb52c673 768 ret = receive_pio(rspi, mesg, t);
0b2182dd
SY		 769 if (ret < 0)
770 goto error;
771 }
772 mesg->actual_length += t->len;
773 }
774 rspi_negate_ssl(rspi);
775
776 mesg->status = 0;
777 mesg->complete(mesg->context);
0b2182dd
SY		 778 }
779
780 return;
781
782error:
783 mesg->status = ret;
784 mesg->complete(mesg->context);
785}
786
787static int rspi_setup(struct spi_device *spi)
788{
789 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
790
791 if (!spi->bits_per_word)
792 spi->bits_per_word = 8;
793 rspi->max_speed_hz = spi->max_speed_hz;
794
5ce0ba88 795 set_config_register(rspi, 8);
0b2182dd
SY		 796
797 return 0;
798}
799
800static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
801{
802 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
803 unsigned long flags;
804
805 mesg->actual_length = 0;
806 mesg->status = -EINPROGRESS;
807
808 spin_lock_irqsave(&rspi->lock, flags);
809 list_add_tail(&mesg->queue, &rspi->queue);
810 schedule_work(&rspi->ws);
811 spin_unlock_irqrestore(&rspi->lock, flags);
812
813 return 0;
814}
815
816static void rspi_cleanup(struct spi_device *spi)
817{
818}
819
820static irqreturn_t rspi_irq(int irq, void *_sr)
821{
c132f094 822 struct rspi_data *rspi = _sr;
97b95c11 823 u8 spsr;
0b2182dd 824 irqreturn_t ret = IRQ_NONE;
97b95c11 825 u8 disable_irq = 0;
0b2182dd
SY		 826
827 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
828 if (spsr & SPSR_SPRF)
829 disable_irq |= SPCR_SPRIE;
830 if (spsr & SPSR_SPTEF)
831 disable_irq |= SPCR_SPTIE;
832
833 if (disable_irq) {
834 ret = IRQ_HANDLED;
835 rspi_disable_irq(rspi, disable_irq);
836 wake_up(&rspi->wait);
837 }
838
839 return ret;
840}
841
fd4a319b 842static int rspi_request_dma(struct rspi_data *rspi,
0243c536 843 struct platform_device *pdev)
a3633fe7 844{
baf588f4 845 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
e2b05099 846 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a3633fe7 847 dma_cap_mask_t mask;
0243c536
SY		 848 struct dma_slave_config cfg;
849 int ret;
a3633fe7 850
e2b05099 851 if (!res || !rspi_pd)
0243c536 852 return 0; /* The driver assumes no error. */
a3633fe7
SY		 853
854 rspi->dma_width_16bit = rspi_pd->dma_width_16bit;
855
856 /* If the module receives data by DMAC, it also needs TX DMAC */
857 if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
858 dma_cap_zero(mask);
859 dma_cap_set(DMA_SLAVE, mask);
0243c536
SY		 860 rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter,
861 (void *)rspi_pd->dma_rx_id);
862 if (rspi->chan_rx) {
863 cfg.slave_id = rspi_pd->dma_rx_id;
864 cfg.direction = DMA_DEV_TO_MEM;
e2b05099
GL		 865 cfg.dst_addr = 0;
866 cfg.src_addr = res->start + RSPI_SPDR;
0243c536
SY		 867 ret = dmaengine_slave_config(rspi->chan_rx, &cfg);
868 if (!ret)
869 dev_info(&pdev->dev, "Use DMA when rx.\n");
870 else
871 return ret;
872 }
a3633fe7
SY		 873 }
874 if (rspi_pd->dma_tx_id) {
875 dma_cap_zero(mask);
876 dma_cap_set(DMA_SLAVE, mask);
0243c536
SY		 877 rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter,
878 (void *)rspi_pd->dma_tx_id);
879 if (rspi->chan_tx) {
880 cfg.slave_id = rspi_pd->dma_tx_id;
881 cfg.direction = DMA_MEM_TO_DEV;
e2b05099
GL		 882 cfg.dst_addr = res->start + RSPI_SPDR;
883 cfg.src_addr = 0;
0243c536
SY		 884 ret = dmaengine_slave_config(rspi->chan_tx, &cfg);
885 if (!ret)
886 dev_info(&pdev->dev, "Use DMA when tx\n");
887 else
888 return ret;
889 }
a3633fe7 890 }
0243c536
SY		 891
892 return 0;
a3633fe7
SY		 893}
894
fd4a319b 895static void rspi_release_dma(struct rspi_data *rspi)
a3633fe7
SY		 896{
897 if (rspi->chan_tx)
898 dma_release_channel(rspi->chan_tx);
899 if (rspi->chan_rx)
900 dma_release_channel(rspi->chan_rx);
901}
902
fd4a319b 903static int rspi_remove(struct platform_device *pdev)
0b2182dd 904{
9d3405db 905 struct rspi_data *rspi = spi_master_get(platform_get_drvdata(pdev));
0b2182dd
SY		 906
907 spi_unregister_master(rspi->master);
a3633fe7 908 rspi_release_dma(rspi);
0b2182dd
SY		 909 free_irq(platform_get_irq(pdev, 0), rspi);
910 clk_put(rspi->clk);
911 iounmap(rspi->addr);
912 spi_master_put(rspi->master);
913
914 return 0;
915}
916
fd4a319b 917static int rspi_probe(struct platform_device *pdev)
0b2182dd
SY		 918{
919 struct resource *res;
920 struct spi_master *master;
921 struct rspi_data *rspi;
922 int ret, irq;
923 char clk_name[16];
baf588f4 924 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
5ce0ba88
HCM		 925 const struct spi_ops *ops;
926 const struct platform_device_id *id_entry = pdev->id_entry;
927
928 ops = (struct spi_ops *)id_entry->driver_data;
929 /* ops parameter check */
930 if (!ops->set_config_register) {
931 dev_err(&pdev->dev, "there is no set_config_register\n");
932 return -ENODEV;
933 }
0b2182dd
SY		 934 /* get base addr */
935 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
936 if (unlikely(res == NULL)) {
937 dev_err(&pdev->dev, "invalid resource\n");
938 return -EINVAL;
939 }
940
941 irq = platform_get_irq(pdev, 0);
942 if (irq < 0) {
943 dev_err(&pdev->dev, "platform_get_irq error\n");
944 return -ENODEV;
945 }
946
947 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
948 if (master == NULL) {
949 dev_err(&pdev->dev, "spi_alloc_master error.\n");
950 return -ENOMEM;
951 }
952
953 rspi = spi_master_get_devdata(master);
24b5a82c 954 platform_set_drvdata(pdev, rspi);
5ce0ba88 955 rspi->ops = ops;
0b2182dd
SY		 956 rspi->master = master;
957 rspi->addr = ioremap(res->start, resource_size(res));
958 if (rspi->addr == NULL) {
959 dev_err(&pdev->dev, "ioremap error.\n");
960 ret = -ENOMEM;
961 goto error1;
962 }
963
5ce0ba88 964 snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id);
0b2182dd
SY		 965 rspi->clk = clk_get(&pdev->dev, clk_name);
966 if (IS_ERR(rspi->clk)) {
967 dev_err(&pdev->dev, "cannot get clock\n");
968 ret = PTR_ERR(rspi->clk);
969 goto error2;
970 }
971 clk_enable(rspi->clk);
972
973 INIT_LIST_HEAD(&rspi->queue);
974 spin_lock_init(&rspi->lock);
975 INIT_WORK(&rspi->ws, rspi_work);
976 init_waitqueue_head(&rspi->wait);
977
5ce0ba88
HCM		 978 master->num_chipselect = rspi_pd->num_chipselect;
979 if (!master->num_chipselect)
980 master->num_chipselect = 2; /* default */
981
0b2182dd
SY		 982 master->bus_num = pdev->id;
983 master->setup = rspi_setup;
984 master->transfer = rspi_transfer;
985 master->cleanup = rspi_cleanup;
986
987 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
988 if (ret < 0) {
989 dev_err(&pdev->dev, "request_irq error\n");
990 goto error3;
991 }
992
a3633fe7 993 rspi->irq = irq;
0243c536
SY		 994 ret = rspi_request_dma(rspi, pdev);
995 if (ret < 0) {
996 dev_err(&pdev->dev, "rspi_request_dma failed.\n");
997 goto error4;
998 }
a3633fe7 999
0b2182dd
SY		 1000 ret = spi_register_master(master);
1001 if (ret < 0) {
1002 dev_err(&pdev->dev, "spi_register_master error.\n");
1003 goto error4;
1004 }
1005
1006 dev_info(&pdev->dev, "probed\n");
1007
1008 return 0;
1009
1010error4:
a3633fe7 1011 rspi_release_dma(rspi);
0b2182dd
SY		 1012 free_irq(irq, rspi);
1013error3:
1014 clk_put(rspi->clk);
1015error2:
1016 iounmap(rspi->addr);
1017error1:
1018 spi_master_put(master);
1019
1020 return ret;
1021}
1022
5ce0ba88
HCM		 1023static struct spi_ops rspi_ops = {
1024 .set_config_register = rspi_set_config_register,
cb52c673
HCM		 1025 .send_pio = rspi_send_pio,
1026 .receive_pio = rspi_receive_pio,
5ce0ba88
HCM		 1027};
1028
1029static struct spi_ops qspi_ops = {
1030 .set_config_register = qspi_set_config_register,
cb52c673
HCM		 1031 .send_pio = qspi_send_pio,
1032 .receive_pio = qspi_receive_pio,
5ce0ba88
HCM		 1033};
1034
1035static struct platform_device_id spi_driver_ids[] = {
1036 { "rspi", (kernel_ulong_t)&rspi_ops },
1037 { "qspi", (kernel_ulong_t)&qspi_ops },
1038 {},
1039};
1040
1041MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1042
0b2182dd
SY		 1043static struct platform_driver rspi_driver = {
1044 .probe = rspi_probe,
fd4a319b 1045 .remove = rspi_remove,
5ce0ba88 1046 .id_table = spi_driver_ids,
0b2182dd 1047 .driver = {
5ce0ba88 1048 .name = "renesas_spi",
0b2182dd
SY		 1049 .owner = THIS_MODULE,
1050 },
1051};
1052module_platform_driver(rspi_driver);
1053
1054MODULE_DESCRIPTION("Renesas RSPI bus driver");
1055MODULE_LICENSE("GPL v2");
1056MODULE_AUTHOR("Yoshihiro Shimoda");
1057MODULE_ALIAS("platform:rspi");
Linux kernel - Deliverables
This page took 0.151149 seconds and 5 git commands to generate.