Commit | Line | Data |
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0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * Based on spi-sh.c: | |
7 | * Copyright (C) 2011 Renesas Solutions Corp. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/errno.h> | |
0b2182dd SY |
28 | #include <linux/interrupt.h> |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/clk.h> | |
a3633fe7 SY |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/sh_dma.h> | |
0b2182dd | 35 | #include <linux/spi/spi.h> |
a3633fe7 | 36 | #include <linux/spi/rspi.h> |
0b2182dd | 37 | |
6ab4865b GU |
38 | #define RSPI_SPCR 0x00 /* Control Register */ |
39 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
40 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
41 | #define RSPI_SPSR 0x03 /* Status Register */ | |
42 | #define RSPI_SPDR 0x04 /* Data Register */ | |
43 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
44 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
45 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
46 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
47 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
48 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
49 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
50 | #define RSPI_SPCR2 0x0f /* Control Register 2 */ | |
51 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ | |
52 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
53 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
54 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
55 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
56 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
57 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
58 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
59 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ | |
60 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 61 | |
5ce0ba88 | 62 | /*qspi only */ |
fbe5072b GU |
63 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
64 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
65 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
66 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
67 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
68 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
5ce0ba88 | 69 | |
6ab4865b GU |
70 | /* SPCR - Control Register */ |
71 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
72 | #define SPCR_SPE 0x40 /* Function Enable */ | |
73 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
74 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
75 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
76 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
77 | /* RSPI on SH only */ | |
78 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
79 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
80 | /* QSPI on R-Car M2 only */ |
81 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
82 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
83 | |
84 | /* SSLP - Slave Select Polarity Register */ | |
85 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
86 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
87 | ||
88 | /* SPPCR - Pin Control Register */ | |
89 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
90 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 91 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
92 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
93 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
94 | ||
fbe5072b GU |
95 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
96 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
97 | ||
6ab4865b GU |
98 | /* SPSR - Status Register */ |
99 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
100 | #define SPSR_TEND 0x40 /* Transmit End */ | |
101 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
102 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
103 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
104 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
105 | #define SPSR_OVRF 0x01 /* Overrun Error Flag */ | |
106 | ||
107 | /* SPSCR - Sequence Control Register */ | |
108 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
109 | ||
110 | /* SPSSR - Sequence Status Register */ | |
111 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
112 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
113 | ||
114 | /* SPDCR - Data Control Register */ | |
115 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
116 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
117 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
118 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
119 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
120 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
121 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
122 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ | |
0b2182dd SY |
123 | #define SPDCR_SLSEL1 0x08 |
124 | #define SPDCR_SLSEL0 0x04 | |
6ab4865b | 125 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ |
0b2182dd SY |
126 | #define SPDCR_SPFC1 0x02 |
127 | #define SPDCR_SPFC0 0x01 | |
6ab4865b | 128 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ |
0b2182dd | 129 | |
6ab4865b GU |
130 | /* SPCKD - Clock Delay Register */ |
131 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 132 | |
6ab4865b GU |
133 | /* SSLND - Slave Select Negation Delay Register */ |
134 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 135 | |
6ab4865b GU |
136 | /* SPND - Next-Access Delay Register */ |
137 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 138 | |
6ab4865b GU |
139 | /* SPCR2 - Control Register 2 */ |
140 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
141 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
142 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
143 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 144 | |
6ab4865b GU |
145 | /* SPCMDn - Command Registers */ |
146 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
147 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
148 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
149 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
150 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 151 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
5ce0ba88 HCM |
152 | #define SPCMD_SPB_8BIT 0x0000 /* qspi only */ |
153 | #define SPCMD_SPB_16BIT 0x0100 | |
0b2182dd SY |
154 | #define SPCMD_SPB_20BIT 0x0000 |
155 | #define SPCMD_SPB_24BIT 0x0100 | |
156 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 157 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
158 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
159 | #define SPCMD_SPIMOD1 0x0040 | |
160 | #define SPCMD_SPIMOD0 0x0020 | |
161 | #define SPCMD_SPIMOD_SINGLE 0 | |
162 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
163 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
164 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
165 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
166 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
167 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
168 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
169 | ||
170 | /* SPBFCR - Buffer Control Register */ | |
171 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ | |
172 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ | |
173 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ | |
174 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 175 | |
2aae80b2 GU |
176 | #define DUMMY_DATA 0x00 |
177 | ||
0b2182dd SY |
178 | struct rspi_data { |
179 | void __iomem *addr; | |
180 | u32 max_speed_hz; | |
181 | struct spi_master *master; | |
0b2182dd | 182 | wait_queue_head_t wait; |
0b2182dd | 183 | struct clk *clk; |
97b95c11 | 184 | u8 spsr; |
348e5153 | 185 | u16 spcmd; |
5ce0ba88 | 186 | const struct spi_ops *ops; |
a3633fe7 SY |
187 | |
188 | /* for dmaengine */ | |
a3633fe7 SY |
189 | struct dma_chan *chan_tx; |
190 | struct dma_chan *chan_rx; | |
191 | int irq; | |
192 | ||
193 | unsigned dma_width_16bit:1; | |
194 | unsigned dma_callbacked:1; | |
74da7686 | 195 | unsigned byte_access:1; |
0b2182dd SY |
196 | }; |
197 | ||
baf588f4 | 198 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
199 | { |
200 | iowrite8(data, rspi->addr + offset); | |
201 | } | |
202 | ||
baf588f4 | 203 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
204 | { |
205 | iowrite16(data, rspi->addr + offset); | |
206 | } | |
207 | ||
baf588f4 | 208 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
209 | { |
210 | iowrite32(data, rspi->addr + offset); | |
211 | } | |
212 | ||
baf588f4 | 213 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
214 | { |
215 | return ioread8(rspi->addr + offset); | |
216 | } | |
217 | ||
baf588f4 | 218 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
219 | { |
220 | return ioread16(rspi->addr + offset); | |
221 | } | |
222 | ||
74da7686 GU |
223 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
224 | { | |
225 | if (rspi->byte_access) | |
226 | rspi_write8(rspi, data, RSPI_SPDR); | |
227 | else /* 16 bit */ | |
228 | rspi_write16(rspi, data, RSPI_SPDR); | |
229 | } | |
230 | ||
231 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
232 | { | |
233 | if (rspi->byte_access) | |
234 | return rspi_read8(rspi, RSPI_SPDR); | |
235 | else /* 16 bit */ | |
236 | return rspi_read16(rspi, RSPI_SPDR); | |
237 | } | |
238 | ||
5ce0ba88 HCM |
239 | /* optional functions */ |
240 | struct spi_ops { | |
74da7686 | 241 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
91949a2d GU |
242 | int (*send_pio)(struct rspi_data *rspi, struct spi_transfer *t); |
243 | int (*receive_pio)(struct rspi_data *rspi, struct spi_transfer *t); | |
5ce0ba88 HCM |
244 | }; |
245 | ||
246 | /* | |
247 | * functions for RSPI | |
248 | */ | |
74da7686 | 249 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 250 | { |
5ce0ba88 HCM |
251 | int spbr; |
252 | ||
253 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ | |
254 | rspi_write8(rspi, 0x00, RSPI_SPPCR); | |
0b2182dd | 255 | |
5ce0ba88 HCM |
256 | /* Sets transfer bit rate */ |
257 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
258 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
259 | ||
74da7686 GU |
260 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
261 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
262 | rspi->byte_access = 0; | |
0b2182dd | 263 | |
5ce0ba88 HCM |
264 | /* Sets RSPCK, SSL, next-access delay value */ |
265 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
266 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
267 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
268 | ||
269 | /* Sets parity, interrupt mask */ | |
270 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
271 | ||
272 | /* Sets SPCMD */ | |
348e5153 | 273 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, |
5ce0ba88 HCM |
274 | RSPI_SPCMD0); |
275 | ||
276 | /* Sets RSPI mode */ | |
277 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
278 | ||
279 | return 0; | |
0b2182dd SY |
280 | } |
281 | ||
5ce0ba88 HCM |
282 | /* |
283 | * functions for QSPI | |
284 | */ | |
74da7686 | 285 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 HCM |
286 | { |
287 | u16 spcmd; | |
288 | int spbr; | |
289 | ||
290 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ | |
291 | rspi_write8(rspi, 0x00, RSPI_SPPCR); | |
292 | ||
293 | /* Sets transfer bit rate */ | |
294 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
295 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
296 | ||
74da7686 GU |
297 | /* Disable dummy transmission, set byte access */ |
298 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
299 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
300 | |
301 | /* Sets RSPCK, SSL, next-access delay value */ | |
302 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
303 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
304 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
305 | ||
306 | /* Data Length Setting */ | |
307 | if (access_size == 8) | |
308 | spcmd = SPCMD_SPB_8BIT; | |
309 | else if (access_size == 16) | |
310 | spcmd = SPCMD_SPB_16BIT; | |
8e1c8096 | 311 | else |
5ce0ba88 HCM |
312 | spcmd = SPCMD_SPB_32BIT; |
313 | ||
348e5153 | 314 | spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; |
5ce0ba88 HCM |
315 | |
316 | /* Resets transfer data length */ | |
317 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
318 | ||
319 | /* Resets transmit and receive buffer */ | |
320 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
321 | /* Sets buffer to allow normal operation */ | |
322 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
323 | ||
324 | /* Sets SPCMD */ | |
325 | rspi_write16(rspi, spcmd, RSPI_SPCMD0); | |
326 | ||
327 | /* Enables SPI function in a master mode */ | |
328 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
334 | ||
baf588f4 | 335 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
336 | { |
337 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
338 | } | |
339 | ||
baf588f4 | 340 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
341 | { |
342 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
343 | } | |
344 | ||
345 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
346 | u8 enable_bit) | |
347 | { | |
348 | int ret; | |
349 | ||
350 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
351 | rspi_enable_irq(rspi, enable_bit); | |
352 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
353 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
354 | return -ETIMEDOUT; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
91949a2d | 359 | static int rspi_send_pio(struct rspi_data *rspi, struct spi_transfer *t) |
0b2182dd SY |
360 | { |
361 | int remain = t->len; | |
c132f094 | 362 | const u8 *data = t->tx_buf; |
0b2182dd SY |
363 | while (remain > 0) { |
364 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, | |
365 | RSPI_SPCR); | |
366 | ||
367 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
368 | dev_err(&rspi->master->dev, | |
369 | "%s: tx empty timeout\n", __func__); | |
370 | return -ETIMEDOUT; | |
371 | } | |
372 | ||
74da7686 | 373 | rspi_write_data(rspi, *data); |
0b2182dd SY |
374 | data++; |
375 | remain--; | |
376 | } | |
377 | ||
b7ed6b88 | 378 | /* Waiting for the last transmission */ |
0b2182dd SY |
379 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
91949a2d | 384 | static int qspi_send_pio(struct rspi_data *rspi, struct spi_transfer *t) |
cb52c673 HCM |
385 | { |
386 | int remain = t->len; | |
c132f094 | 387 | const u8 *data = t->tx_buf; |
cb52c673 HCM |
388 | |
389 | rspi_write8(rspi, SPBFCR_TXRST, QSPI_SPBFCR); | |
390 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
391 | ||
cb52c673 HCM |
392 | while (remain > 0) { |
393 | ||
394 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
395 | dev_err(&rspi->master->dev, | |
396 | "%s: tx empty timeout\n", __func__); | |
397 | return -ETIMEDOUT; | |
398 | } | |
74da7686 | 399 | rspi_write_data(rspi, *data++); |
cb52c673 HCM |
400 | |
401 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
402 | dev_err(&rspi->master->dev, | |
403 | "%s: receive timeout\n", __func__); | |
404 | return -ETIMEDOUT; | |
405 | } | |
74da7686 | 406 | rspi_read_data(rspi); |
cb52c673 HCM |
407 | |
408 | remain--; | |
409 | } | |
410 | ||
b7ed6b88 | 411 | /* Waiting for the last transmission */ |
cb52c673 HCM |
412 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
91949a2d | 417 | #define send_pio(spi, t) spi->ops->send_pio(spi, t) |
cb52c673 | 418 | |
a3633fe7 SY |
419 | static void rspi_dma_complete(void *arg) |
420 | { | |
421 | struct rspi_data *rspi = arg; | |
422 | ||
423 | rspi->dma_callbacked = 1; | |
424 | wake_up_interruptible(&rspi->wait); | |
425 | } | |
426 | ||
c132f094 GU |
427 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
428 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
429 | enum dma_transfer_direction dir) |
430 | { | |
431 | sg_init_table(sg, 1); | |
432 | sg_set_buf(sg, buf, len); | |
433 | sg_dma_len(sg) = len; | |
434 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
435 | } | |
436 | ||
437 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
438 | enum dma_transfer_direction dir) | |
439 | { | |
440 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
441 | } | |
442 | ||
443 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
444 | { | |
445 | u16 *dst = buf; | |
446 | const u8 *src = data; | |
447 | ||
448 | while (len) { | |
449 | *dst++ = (u16)(*src++); | |
450 | len--; | |
451 | } | |
452 | } | |
453 | ||
454 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
455 | { | |
456 | u8 *dst = buf; | |
457 | const u16 *src = data; | |
458 | ||
459 | while (len) { | |
460 | *dst++ = (u8)*src++; | |
461 | len--; | |
462 | } | |
463 | } | |
464 | ||
465 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
466 | { | |
467 | struct scatterlist sg; | |
c132f094 | 468 | const void *buf = NULL; |
a3633fe7 SY |
469 | struct dma_async_tx_descriptor *desc; |
470 | unsigned len; | |
471 | int ret = 0; | |
472 | ||
473 | if (rspi->dma_width_16bit) { | |
c132f094 | 474 | void *tmp; |
a3633fe7 SY |
475 | /* |
476 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
477 | * buffer. And, the driver converts original data into the | |
478 | * DMAC data as the following format: | |
479 | * original data: 1st byte, 2nd byte ... | |
480 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
481 | */ | |
482 | len = t->len * 2; | |
c132f094 GU |
483 | tmp = kmalloc(len, GFP_KERNEL); |
484 | if (!tmp) | |
a3633fe7 | 485 | return -ENOMEM; |
c132f094 GU |
486 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
487 | buf = tmp; | |
a3633fe7 SY |
488 | } else { |
489 | len = t->len; | |
c132f094 | 490 | buf = t->tx_buf; |
a3633fe7 SY |
491 | } |
492 | ||
493 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
494 | ret = -EFAULT; | |
495 | goto end_nomap; | |
496 | } | |
497 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
498 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
499 | if (!desc) { | |
500 | ret = -EIO; | |
501 | goto end; | |
502 | } | |
503 | ||
504 | /* | |
505 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
506 | * called. So, this driver disables the IRQ while DMA transfer. | |
507 | */ | |
508 | disable_irq(rspi->irq); | |
509 | ||
510 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
511 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
512 | rspi->dma_callbacked = 0; | |
513 | ||
514 | desc->callback = rspi_dma_complete; | |
515 | desc->callback_param = rspi; | |
516 | dmaengine_submit(desc); | |
517 | dma_async_issue_pending(rspi->chan_tx); | |
518 | ||
519 | ret = wait_event_interruptible_timeout(rspi->wait, | |
520 | rspi->dma_callbacked, HZ); | |
521 | if (ret > 0 && rspi->dma_callbacked) | |
522 | ret = 0; | |
523 | else if (!ret) | |
524 | ret = -ETIMEDOUT; | |
525 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
526 | ||
527 | enable_irq(rspi->irq); | |
528 | ||
529 | end: | |
530 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
531 | end_nomap: | |
532 | if (rspi->dma_width_16bit) | |
533 | kfree(buf); | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
baf588f4 | 538 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 539 | { |
97b95c11 | 540 | u8 spsr; |
0b2182dd SY |
541 | |
542 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
543 | if (spsr & SPSR_SPRF) | |
74da7686 | 544 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
545 | if (spsr & SPSR_OVRF) |
546 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 547 | RSPI_SPSR); |
a3633fe7 SY |
548 | } |
549 | ||
91949a2d | 550 | static int rspi_receive_pio(struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
551 | { |
552 | int remain = t->len; | |
553 | u8 *data; | |
554 | ||
555 | rspi_receive_init(rspi); | |
0b2182dd | 556 | |
c132f094 | 557 | data = t->rx_buf; |
0b2182dd SY |
558 | while (remain > 0) { |
559 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, | |
560 | RSPI_SPCR); | |
561 | ||
562 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
563 | dev_err(&rspi->master->dev, | |
564 | "%s: tx empty timeout\n", __func__); | |
565 | return -ETIMEDOUT; | |
566 | } | |
567 | /* dummy write for generate clock */ | |
74da7686 | 568 | rspi_write_data(rspi, DUMMY_DATA); |
0b2182dd SY |
569 | |
570 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
571 | dev_err(&rspi->master->dev, | |
572 | "%s: receive timeout\n", __func__); | |
573 | return -ETIMEDOUT; | |
574 | } | |
74da7686 | 575 | *data = rspi_read_data(rspi); |
0b2182dd SY |
576 | |
577 | data++; | |
578 | remain--; | |
579 | } | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
baf588f4 | 584 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 585 | { |
97b95c11 | 586 | u8 spsr; |
cb52c673 HCM |
587 | |
588 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
589 | if (spsr & SPSR_SPRF) | |
74da7686 | 590 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 HCM |
591 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
592 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
593 | } | |
594 | ||
91949a2d | 595 | static int qspi_receive_pio(struct rspi_data *rspi, struct spi_transfer *t) |
cb52c673 HCM |
596 | { |
597 | int remain = t->len; | |
598 | u8 *data; | |
599 | ||
600 | qspi_receive_init(rspi); | |
601 | ||
c132f094 | 602 | data = t->rx_buf; |
cb52c673 HCM |
603 | while (remain > 0) { |
604 | ||
605 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
606 | dev_err(&rspi->master->dev, | |
607 | "%s: tx empty timeout\n", __func__); | |
608 | return -ETIMEDOUT; | |
609 | } | |
610 | /* dummy write for generate clock */ | |
74da7686 | 611 | rspi_write_data(rspi, DUMMY_DATA); |
cb52c673 HCM |
612 | |
613 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
614 | dev_err(&rspi->master->dev, | |
615 | "%s: receive timeout\n", __func__); | |
616 | return -ETIMEDOUT; | |
617 | } | |
74da7686 | 618 | *data++ = rspi_read_data(rspi); |
cb52c673 HCM |
619 | remain--; |
620 | } | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
91949a2d | 625 | #define receive_pio(spi, t) spi->ops->receive_pio(spi, t) |
cb52c673 | 626 | |
a3633fe7 SY |
627 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
628 | { | |
629 | struct scatterlist sg, sg_dummy; | |
630 | void *dummy = NULL, *rx_buf = NULL; | |
631 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
632 | unsigned len; | |
633 | int ret = 0; | |
634 | ||
635 | if (rspi->dma_width_16bit) { | |
636 | /* | |
637 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
638 | * buffer. And, finally the driver converts the DMAC data into | |
639 | * actual data as the following format: | |
640 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
641 | * actual data: 1st byte, 2nd byte ... | |
642 | */ | |
643 | len = t->len * 2; | |
644 | rx_buf = kmalloc(len, GFP_KERNEL); | |
645 | if (!rx_buf) | |
646 | return -ENOMEM; | |
647 | } else { | |
648 | len = t->len; | |
649 | rx_buf = t->rx_buf; | |
650 | } | |
651 | ||
652 | /* prepare dummy transfer to generate SPI clocks */ | |
653 | dummy = kzalloc(len, GFP_KERNEL); | |
654 | if (!dummy) { | |
655 | ret = -ENOMEM; | |
656 | goto end_nomap; | |
657 | } | |
658 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
659 | DMA_TO_DEVICE)) { | |
660 | ret = -EFAULT; | |
661 | goto end_nomap; | |
662 | } | |
663 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
664 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
665 | if (!desc_dummy) { | |
666 | ret = -EIO; | |
667 | goto end_dummy_mapped; | |
668 | } | |
669 | ||
670 | /* prepare receive transfer */ | |
671 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
672 | DMA_FROM_DEVICE)) { | |
673 | ret = -EFAULT; | |
674 | goto end_dummy_mapped; | |
675 | ||
676 | } | |
677 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
678 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
679 | if (!desc) { | |
680 | ret = -EIO; | |
681 | goto end; | |
682 | } | |
683 | ||
684 | rspi_receive_init(rspi); | |
685 | ||
686 | /* | |
687 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
688 | * called. So, this driver disables the IRQ while DMA transfer. | |
689 | */ | |
690 | disable_irq(rspi->irq); | |
691 | ||
692 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
693 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
694 | rspi->dma_callbacked = 0; | |
695 | ||
696 | desc->callback = rspi_dma_complete; | |
697 | desc->callback_param = rspi; | |
698 | dmaengine_submit(desc); | |
699 | dma_async_issue_pending(rspi->chan_rx); | |
700 | ||
701 | desc_dummy->callback = NULL; /* No callback */ | |
702 | dmaengine_submit(desc_dummy); | |
703 | dma_async_issue_pending(rspi->chan_tx); | |
704 | ||
705 | ret = wait_event_interruptible_timeout(rspi->wait, | |
706 | rspi->dma_callbacked, HZ); | |
707 | if (ret > 0 && rspi->dma_callbacked) | |
708 | ret = 0; | |
709 | else if (!ret) | |
710 | ret = -ETIMEDOUT; | |
711 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
712 | ||
713 | enable_irq(rspi->irq); | |
714 | ||
715 | end: | |
716 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
717 | end_dummy_mapped: | |
718 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
719 | end_nomap: | |
720 | if (rspi->dma_width_16bit) { | |
721 | if (!ret) | |
722 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
723 | kfree(rx_buf); | |
724 | } | |
725 | kfree(dummy); | |
726 | ||
727 | return ret; | |
728 | } | |
729 | ||
baf588f4 | 730 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
731 | { |
732 | if (t->tx_buf && rspi->chan_tx) | |
733 | return 1; | |
734 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
735 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
736 | return 1; | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
79d23495 GU |
741 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
742 | struct spi_transfer *xfer) | |
0b2182dd | 743 | { |
79d23495 GU |
744 | struct rspi_data *rspi = spi_master_get_devdata(master); |
745 | int ret = 0; | |
0b2182dd | 746 | |
79d23495 GU |
747 | if (xfer->tx_buf) { |
748 | if (rspi_is_dma(rspi, xfer)) | |
749 | ret = rspi_send_dma(rspi, xfer); | |
750 | else | |
751 | ret = send_pio(rspi, xfer); | |
752 | if (ret < 0) | |
753 | return ret; | |
0b2182dd | 754 | } |
79d23495 GU |
755 | if (xfer->rx_buf) { |
756 | if (rspi_is_dma(rspi, xfer)) | |
757 | ret = rspi_receive_dma(rspi, xfer); | |
758 | else | |
759 | ret = receive_pio(rspi, xfer); | |
760 | } | |
761 | return ret; | |
0b2182dd SY |
762 | } |
763 | ||
764 | static int rspi_setup(struct spi_device *spi) | |
765 | { | |
766 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
767 | ||
0b2182dd SY |
768 | rspi->max_speed_hz = spi->max_speed_hz; |
769 | ||
348e5153 GU |
770 | rspi->spcmd = SPCMD_SSLKP; |
771 | if (spi->mode & SPI_CPOL) | |
772 | rspi->spcmd |= SPCMD_CPOL; | |
773 | if (spi->mode & SPI_CPHA) | |
774 | rspi->spcmd |= SPCMD_CPHA; | |
775 | ||
5ce0ba88 | 776 | set_config_register(rspi, 8); |
0b2182dd SY |
777 | |
778 | return 0; | |
779 | } | |
780 | ||
79d23495 | 781 | static void rspi_cleanup(struct spi_device *spi) |
0b2182dd | 782 | { |
79d23495 | 783 | } |
0b2182dd | 784 | |
79d23495 GU |
785 | static int rspi_prepare_message(struct spi_master *master, |
786 | struct spi_message *message) | |
787 | { | |
788 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
0b2182dd | 789 | |
79d23495 | 790 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
791 | return 0; |
792 | } | |
793 | ||
79d23495 GU |
794 | static int rspi_unprepare_message(struct spi_master *master, |
795 | struct spi_message *message) | |
0b2182dd | 796 | { |
79d23495 GU |
797 | struct rspi_data *rspi = spi_master_get_devdata(master); |
798 | ||
799 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); | |
800 | return 0; | |
0b2182dd SY |
801 | } |
802 | ||
803 | static irqreturn_t rspi_irq(int irq, void *_sr) | |
804 | { | |
c132f094 | 805 | struct rspi_data *rspi = _sr; |
97b95c11 | 806 | u8 spsr; |
0b2182dd | 807 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 808 | u8 disable_irq = 0; |
0b2182dd SY |
809 | |
810 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
811 | if (spsr & SPSR_SPRF) | |
812 | disable_irq |= SPCR_SPRIE; | |
813 | if (spsr & SPSR_SPTEF) | |
814 | disable_irq |= SPCR_SPTIE; | |
815 | ||
816 | if (disable_irq) { | |
817 | ret = IRQ_HANDLED; | |
818 | rspi_disable_irq(rspi, disable_irq); | |
819 | wake_up(&rspi->wait); | |
820 | } | |
821 | ||
822 | return ret; | |
823 | } | |
824 | ||
fd4a319b | 825 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 826 | struct platform_device *pdev) |
a3633fe7 | 827 | { |
baf588f4 | 828 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 829 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 830 | dma_cap_mask_t mask; |
0243c536 SY |
831 | struct dma_slave_config cfg; |
832 | int ret; | |
a3633fe7 | 833 | |
e2b05099 | 834 | if (!res || !rspi_pd) |
0243c536 | 835 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
836 | |
837 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
838 | ||
839 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
840 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
841 | dma_cap_zero(mask); | |
842 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
843 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
844 | (void *)rspi_pd->dma_rx_id); | |
845 | if (rspi->chan_rx) { | |
846 | cfg.slave_id = rspi_pd->dma_rx_id; | |
847 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
848 | cfg.dst_addr = 0; |
849 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
850 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
851 | if (!ret) | |
852 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
853 | else | |
854 | return ret; | |
855 | } | |
a3633fe7 SY |
856 | } |
857 | if (rspi_pd->dma_tx_id) { | |
858 | dma_cap_zero(mask); | |
859 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
860 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
861 | (void *)rspi_pd->dma_tx_id); | |
862 | if (rspi->chan_tx) { | |
863 | cfg.slave_id = rspi_pd->dma_tx_id; | |
864 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
865 | cfg.dst_addr = res->start + RSPI_SPDR; |
866 | cfg.src_addr = 0; | |
0243c536 SY |
867 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
868 | if (!ret) | |
869 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
870 | else | |
871 | return ret; | |
872 | } | |
a3633fe7 | 873 | } |
0243c536 SY |
874 | |
875 | return 0; | |
a3633fe7 SY |
876 | } |
877 | ||
fd4a319b | 878 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
879 | { |
880 | if (rspi->chan_tx) | |
881 | dma_release_channel(rspi->chan_tx); | |
882 | if (rspi->chan_rx) | |
883 | dma_release_channel(rspi->chan_rx); | |
884 | } | |
885 | ||
fd4a319b | 886 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 887 | { |
5ffbe2d9 | 888 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 889 | |
a3633fe7 | 890 | rspi_release_dma(rspi); |
fcb4ed74 | 891 | clk_disable(rspi->clk); |
0b2182dd SY |
892 | |
893 | return 0; | |
894 | } | |
895 | ||
fd4a319b | 896 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
897 | { |
898 | struct resource *res; | |
899 | struct spi_master *master; | |
900 | struct rspi_data *rspi; | |
901 | int ret, irq; | |
902 | char clk_name[16]; | |
baf588f4 | 903 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
5ce0ba88 HCM |
904 | const struct spi_ops *ops; |
905 | const struct platform_device_id *id_entry = pdev->id_entry; | |
906 | ||
907 | ops = (struct spi_ops *)id_entry->driver_data; | |
908 | /* ops parameter check */ | |
909 | if (!ops->set_config_register) { | |
910 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
911 | return -ENODEV; | |
912 | } | |
0b2182dd SY |
913 | |
914 | irq = platform_get_irq(pdev, 0); | |
915 | if (irq < 0) { | |
916 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
917 | return -ENODEV; | |
918 | } | |
919 | ||
920 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); | |
921 | if (master == NULL) { | |
922 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
923 | return -ENOMEM; | |
924 | } | |
925 | ||
926 | rspi = spi_master_get_devdata(master); | |
24b5a82c | 927 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 928 | rspi->ops = ops; |
0b2182dd | 929 | rspi->master = master; |
5d79e9ac LP |
930 | |
931 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
932 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
933 | if (IS_ERR(rspi->addr)) { | |
934 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
935 | goto error1; |
936 | } | |
937 | ||
5ce0ba88 | 938 | snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); |
5d79e9ac | 939 | rspi->clk = devm_clk_get(&pdev->dev, clk_name); |
0b2182dd SY |
940 | if (IS_ERR(rspi->clk)) { |
941 | dev_err(&pdev->dev, "cannot get clock\n"); | |
942 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 943 | goto error1; |
0b2182dd SY |
944 | } |
945 | clk_enable(rspi->clk); | |
946 | ||
0b2182dd SY |
947 | init_waitqueue_head(&rspi->wait); |
948 | ||
efd85acb GU |
949 | if (rspi_pd && rspi_pd->num_chipselect) |
950 | master->num_chipselect = rspi_pd->num_chipselect; | |
951 | else | |
5ce0ba88 HCM |
952 | master->num_chipselect = 2; /* default */ |
953 | ||
0b2182dd SY |
954 | master->bus_num = pdev->id; |
955 | master->setup = rspi_setup; | |
79d23495 | 956 | master->transfer_one = rspi_transfer_one; |
0b2182dd | 957 | master->cleanup = rspi_cleanup; |
79d23495 GU |
958 | master->prepare_message = rspi_prepare_message; |
959 | master->unprepare_message = rspi_unprepare_message; | |
348e5153 | 960 | master->mode_bits = SPI_CPHA | SPI_CPOL; |
0b2182dd | 961 | |
5d79e9ac LP |
962 | ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, |
963 | dev_name(&pdev->dev), rspi); | |
0b2182dd SY |
964 | if (ret < 0) { |
965 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 966 | goto error2; |
0b2182dd SY |
967 | } |
968 | ||
a3633fe7 | 969 | rspi->irq = irq; |
0243c536 SY |
970 | ret = rspi_request_dma(rspi, pdev); |
971 | if (ret < 0) { | |
972 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 973 | goto error3; |
0243c536 | 974 | } |
a3633fe7 | 975 | |
9e03d05e | 976 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
977 | if (ret < 0) { |
978 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 979 | goto error3; |
0b2182dd SY |
980 | } |
981 | ||
982 | dev_info(&pdev->dev, "probed\n"); | |
983 | ||
984 | return 0; | |
985 | ||
fcb4ed74 | 986 | error3: |
5d79e9ac | 987 | rspi_release_dma(rspi); |
fcb4ed74 GU |
988 | error2: |
989 | clk_disable(rspi->clk); | |
0b2182dd SY |
990 | error1: |
991 | spi_master_put(master); | |
992 | ||
993 | return ret; | |
994 | } | |
995 | ||
5ce0ba88 HCM |
996 | static struct spi_ops rspi_ops = { |
997 | .set_config_register = rspi_set_config_register, | |
cb52c673 HCM |
998 | .send_pio = rspi_send_pio, |
999 | .receive_pio = rspi_receive_pio, | |
5ce0ba88 HCM |
1000 | }; |
1001 | ||
1002 | static struct spi_ops qspi_ops = { | |
1003 | .set_config_register = qspi_set_config_register, | |
cb52c673 HCM |
1004 | .send_pio = qspi_send_pio, |
1005 | .receive_pio = qspi_receive_pio, | |
5ce0ba88 HCM |
1006 | }; |
1007 | ||
1008 | static struct platform_device_id spi_driver_ids[] = { | |
1009 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
1010 | { "qspi", (kernel_ulong_t)&qspi_ops }, | |
1011 | {}, | |
1012 | }; | |
1013 | ||
1014 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1015 | ||
0b2182dd SY |
1016 | static struct platform_driver rspi_driver = { |
1017 | .probe = rspi_probe, | |
fd4a319b | 1018 | .remove = rspi_remove, |
5ce0ba88 | 1019 | .id_table = spi_driver_ids, |
0b2182dd | 1020 | .driver = { |
5ce0ba88 | 1021 | .name = "renesas_spi", |
0b2182dd SY |
1022 | .owner = THIS_MODULE, |
1023 | }, | |
1024 | }; | |
1025 | module_platform_driver(rspi_driver); | |
1026 | ||
1027 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1028 | MODULE_LICENSE("GPL v2"); | |
1029 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1030 | MODULE_ALIAS("platform:rspi"); |