Commit | Line | Data |
---|---|---|
0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 5 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
6 | * |
7 | * Based on spi-sh.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/errno.h> | |
0b2182dd SY |
29 | #include <linux/interrupt.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/clk.h> | |
a3633fe7 SY |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/dma-mapping.h> | |
426ef76d | 35 | #include <linux/of_device.h> |
490c9774 | 36 | #include <linux/pm_runtime.h> |
a3633fe7 | 37 | #include <linux/sh_dma.h> |
0b2182dd | 38 | #include <linux/spi/spi.h> |
a3633fe7 | 39 | #include <linux/spi/rspi.h> |
0b2182dd | 40 | |
6ab4865b GU |
41 | #define RSPI_SPCR 0x00 /* Control Register */ |
42 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
43 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
44 | #define RSPI_SPSR 0x03 /* Status Register */ | |
45 | #define RSPI_SPDR 0x04 /* Data Register */ | |
46 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
47 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
48 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
49 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
50 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
51 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
52 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 53 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
54 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
55 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
56 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
57 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
58 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
59 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
60 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
61 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
62 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
63 | #define RSPI_NUM_SPCMD 8 | |
64 | #define RSPI_RZ_NUM_SPCMD 4 | |
65 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
66 | |
67 | /* RSPI on RZ only */ | |
6ab4865b GU |
68 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
69 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 70 | |
862d357f | 71 | /* QSPI only */ |
fbe5072b GU |
72 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
73 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
74 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
75 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
76 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
77 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 78 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 79 | |
6ab4865b GU |
80 | /* SPCR - Control Register */ |
81 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
82 | #define SPCR_SPE 0x40 /* Function Enable */ | |
83 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
84 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
85 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
86 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
87 | /* RSPI on SH only */ | |
88 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
89 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
90 | /* QSPI on R-Car M2 only */ |
91 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
92 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
93 | |
94 | /* SSLP - Slave Select Polarity Register */ | |
95 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
96 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
97 | ||
98 | /* SPPCR - Pin Control Register */ | |
99 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
100 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 101 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
102 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
103 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
104 | ||
fbe5072b GU |
105 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
106 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
107 | ||
6ab4865b GU |
108 | /* SPSR - Status Register */ |
109 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
110 | #define SPSR_TEND 0x40 /* Transmit End */ | |
111 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
112 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
113 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
114 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 115 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
116 | |
117 | /* SPSCR - Sequence Control Register */ | |
118 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
119 | ||
120 | /* SPSSR - Sequence Status Register */ | |
121 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
122 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
123 | ||
124 | /* SPDCR - Data Control Register */ | |
125 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
126 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
127 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
128 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
129 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
130 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
131 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 132 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
133 | #define SPDCR_SLSEL1 0x08 |
134 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 135 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
136 | #define SPDCR_SPFC1 0x02 |
137 | #define SPDCR_SPFC0 0x01 | |
862d357f | 138 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 139 | |
6ab4865b GU |
140 | /* SPCKD - Clock Delay Register */ |
141 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 142 | |
6ab4865b GU |
143 | /* SSLND - Slave Select Negation Delay Register */ |
144 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 145 | |
6ab4865b GU |
146 | /* SPND - Next-Access Delay Register */ |
147 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 148 | |
6ab4865b GU |
149 | /* SPCR2 - Control Register 2 */ |
150 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
151 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
152 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
153 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 154 | |
6ab4865b GU |
155 | /* SPCMDn - Command Registers */ |
156 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
157 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
158 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
159 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
160 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 161 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 162 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 163 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
164 | #define SPCMD_SPB_20BIT 0x0000 |
165 | #define SPCMD_SPB_24BIT 0x0100 | |
166 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 167 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
168 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
169 | #define SPCMD_SPIMOD1 0x0040 | |
170 | #define SPCMD_SPIMOD0 0x0020 | |
171 | #define SPCMD_SPIMOD_SINGLE 0 | |
172 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
173 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
174 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
175 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
176 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
177 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
178 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
179 | ||
180 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
181 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
182 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
183 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
184 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 185 | |
2aae80b2 GU |
186 | #define DUMMY_DATA 0x00 |
187 | ||
0b2182dd SY |
188 | struct rspi_data { |
189 | void __iomem *addr; | |
190 | u32 max_speed_hz; | |
191 | struct spi_master *master; | |
0b2182dd | 192 | wait_queue_head_t wait; |
0b2182dd | 193 | struct clk *clk; |
348e5153 | 194 | u16 spcmd; |
06a7a3cf GU |
195 | u8 spsr; |
196 | u8 sppcr; | |
93722206 | 197 | int rx_irq, tx_irq; |
5ce0ba88 | 198 | const struct spi_ops *ops; |
a3633fe7 SY |
199 | |
200 | /* for dmaengine */ | |
a3633fe7 SY |
201 | struct dma_chan *chan_tx; |
202 | struct dma_chan *chan_rx; | |
a3633fe7 SY |
203 | |
204 | unsigned dma_width_16bit:1; | |
205 | unsigned dma_callbacked:1; | |
74da7686 | 206 | unsigned byte_access:1; |
0b2182dd SY |
207 | }; |
208 | ||
baf588f4 | 209 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
210 | { |
211 | iowrite8(data, rspi->addr + offset); | |
212 | } | |
213 | ||
baf588f4 | 214 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
215 | { |
216 | iowrite16(data, rspi->addr + offset); | |
217 | } | |
218 | ||
baf588f4 | 219 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
220 | { |
221 | iowrite32(data, rspi->addr + offset); | |
222 | } | |
223 | ||
baf588f4 | 224 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
225 | { |
226 | return ioread8(rspi->addr + offset); | |
227 | } | |
228 | ||
baf588f4 | 229 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
230 | { |
231 | return ioread16(rspi->addr + offset); | |
232 | } | |
233 | ||
74da7686 GU |
234 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
235 | { | |
236 | if (rspi->byte_access) | |
237 | rspi_write8(rspi, data, RSPI_SPDR); | |
238 | else /* 16 bit */ | |
239 | rspi_write16(rspi, data, RSPI_SPDR); | |
240 | } | |
241 | ||
242 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
243 | { | |
244 | if (rspi->byte_access) | |
245 | return rspi_read8(rspi, RSPI_SPDR); | |
246 | else /* 16 bit */ | |
247 | return rspi_read16(rspi, RSPI_SPDR); | |
248 | } | |
249 | ||
5ce0ba88 HCM |
250 | /* optional functions */ |
251 | struct spi_ops { | |
74da7686 | 252 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
253 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
254 | struct spi_transfer *xfer); | |
880c6d11 | 255 | u16 mode_bits; |
5ce0ba88 HCM |
256 | }; |
257 | ||
258 | /* | |
862d357f | 259 | * functions for RSPI on legacy SH |
5ce0ba88 | 260 | */ |
74da7686 | 261 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 262 | { |
5ce0ba88 HCM |
263 | int spbr; |
264 | ||
06a7a3cf GU |
265 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
266 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 267 | |
5ce0ba88 HCM |
268 | /* Sets transfer bit rate */ |
269 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
270 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
271 | ||
74da7686 GU |
272 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
273 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
274 | rspi->byte_access = 0; | |
0b2182dd | 275 | |
5ce0ba88 HCM |
276 | /* Sets RSPCK, SSL, next-access delay value */ |
277 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
278 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
279 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
280 | ||
281 | /* Sets parity, interrupt mask */ | |
282 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
283 | ||
284 | /* Sets SPCMD */ | |
880c6d11 GU |
285 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
286 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
287 | |
288 | /* Sets RSPI mode */ | |
289 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
290 | ||
291 | return 0; | |
0b2182dd SY |
292 | } |
293 | ||
862d357f GU |
294 | /* |
295 | * functions for RSPI on RZ | |
296 | */ | |
297 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
298 | { | |
299 | int spbr; | |
300 | ||
06a7a3cf GU |
301 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
302 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
303 | |
304 | /* Sets transfer bit rate */ | |
305 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
306 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
307 | ||
308 | /* Disable dummy transmission, set byte access */ | |
309 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
310 | rspi->byte_access = 1; | |
311 | ||
312 | /* Sets RSPCK, SSL, next-access delay value */ | |
313 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
314 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
315 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
316 | ||
317 | /* Sets SPCMD */ | |
318 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
319 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
320 | ||
321 | /* Sets RSPI mode */ | |
322 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
5ce0ba88 HCM |
327 | /* |
328 | * functions for QSPI | |
329 | */ | |
74da7686 | 330 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 331 | { |
5ce0ba88 HCM |
332 | int spbr; |
333 | ||
06a7a3cf GU |
334 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
335 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
336 | |
337 | /* Sets transfer bit rate */ | |
338 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
339 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
340 | ||
74da7686 GU |
341 | /* Disable dummy transmission, set byte access */ |
342 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
343 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
344 | |
345 | /* Sets RSPCK, SSL, next-access delay value */ | |
346 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
347 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
348 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
349 | ||
350 | /* Data Length Setting */ | |
351 | if (access_size == 8) | |
880c6d11 | 352 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 353 | else if (access_size == 16) |
880c6d11 | 354 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 355 | else |
880c6d11 | 356 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 357 | |
880c6d11 | 358 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
359 | |
360 | /* Resets transfer data length */ | |
361 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
362 | ||
363 | /* Resets transmit and receive buffer */ | |
364 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
365 | /* Sets buffer to allow normal operation */ | |
366 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
367 | ||
368 | /* Sets SPCMD */ | |
880c6d11 | 369 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 370 | |
880c6d11 | 371 | /* Enables SPI function in master mode */ |
5ce0ba88 HCM |
372 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
378 | ||
baf588f4 | 379 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
380 | { |
381 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
382 | } | |
383 | ||
baf588f4 | 384 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
385 | { |
386 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
387 | } | |
388 | ||
389 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
390 | u8 enable_bit) | |
391 | { | |
392 | int ret; | |
393 | ||
394 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
395 | if (rspi->spsr & wait_mask) |
396 | return 0; | |
397 | ||
0b2182dd SY |
398 | rspi_enable_irq(rspi, enable_bit); |
399 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
400 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
401 | return -ETIMEDOUT; | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
35301c99 GU |
406 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
407 | { | |
408 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
409 | dev_err(&rspi->master->dev, "transmit timeout\n"); | |
410 | return -ETIMEDOUT; | |
411 | } | |
412 | rspi_write_data(rspi, data); | |
413 | return 0; | |
414 | } | |
415 | ||
416 | static int rspi_data_in(struct rspi_data *rspi) | |
417 | { | |
418 | u8 data; | |
419 | ||
420 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
421 | dev_err(&rspi->master->dev, "receive timeout\n"); | |
422 | return -ETIMEDOUT; | |
423 | } | |
424 | data = rspi_read_data(rspi); | |
425 | return data; | |
426 | } | |
427 | ||
428 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
429 | { | |
430 | int ret; | |
431 | ||
432 | ret = rspi_data_out(rspi, data); | |
433 | if (ret < 0) | |
434 | return ret; | |
435 | ||
436 | return rspi_data_in(rspi); | |
437 | } | |
438 | ||
a3633fe7 SY |
439 | static void rspi_dma_complete(void *arg) |
440 | { | |
441 | struct rspi_data *rspi = arg; | |
442 | ||
443 | rspi->dma_callbacked = 1; | |
444 | wake_up_interruptible(&rspi->wait); | |
445 | } | |
446 | ||
c132f094 GU |
447 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
448 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
449 | enum dma_transfer_direction dir) |
450 | { | |
451 | sg_init_table(sg, 1); | |
452 | sg_set_buf(sg, buf, len); | |
453 | sg_dma_len(sg) = len; | |
454 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
455 | } | |
456 | ||
457 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
458 | enum dma_transfer_direction dir) | |
459 | { | |
460 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
461 | } | |
462 | ||
463 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
464 | { | |
465 | u16 *dst = buf; | |
466 | const u8 *src = data; | |
467 | ||
468 | while (len) { | |
469 | *dst++ = (u16)(*src++); | |
470 | len--; | |
471 | } | |
472 | } | |
473 | ||
474 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
475 | { | |
476 | u8 *dst = buf; | |
477 | const u16 *src = data; | |
478 | ||
479 | while (len) { | |
480 | *dst++ = (u8)*src++; | |
481 | len--; | |
482 | } | |
483 | } | |
484 | ||
485 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
486 | { | |
487 | struct scatterlist sg; | |
c132f094 | 488 | const void *buf = NULL; |
a3633fe7 | 489 | struct dma_async_tx_descriptor *desc; |
93722206 | 490 | unsigned int len; |
a3633fe7 SY |
491 | int ret = 0; |
492 | ||
493 | if (rspi->dma_width_16bit) { | |
c132f094 | 494 | void *tmp; |
a3633fe7 SY |
495 | /* |
496 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
497 | * buffer. And, the driver converts original data into the | |
498 | * DMAC data as the following format: | |
499 | * original data: 1st byte, 2nd byte ... | |
500 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
501 | */ | |
502 | len = t->len * 2; | |
c132f094 GU |
503 | tmp = kmalloc(len, GFP_KERNEL); |
504 | if (!tmp) | |
a3633fe7 | 505 | return -ENOMEM; |
c132f094 GU |
506 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
507 | buf = tmp; | |
a3633fe7 SY |
508 | } else { |
509 | len = t->len; | |
c132f094 | 510 | buf = t->tx_buf; |
a3633fe7 SY |
511 | } |
512 | ||
513 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
514 | ret = -EFAULT; | |
515 | goto end_nomap; | |
516 | } | |
517 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
518 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
519 | if (!desc) { | |
520 | ret = -EIO; | |
521 | goto end; | |
522 | } | |
523 | ||
524 | /* | |
525 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
526 | * called. So, this driver disables the IRQ while DMA transfer. | |
527 | */ | |
93722206 | 528 | disable_irq(rspi->tx_irq); |
a3633fe7 SY |
529 | |
530 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
531 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
532 | rspi->dma_callbacked = 0; | |
533 | ||
534 | desc->callback = rspi_dma_complete; | |
535 | desc->callback_param = rspi; | |
536 | dmaengine_submit(desc); | |
537 | dma_async_issue_pending(rspi->chan_tx); | |
538 | ||
539 | ret = wait_event_interruptible_timeout(rspi->wait, | |
540 | rspi->dma_callbacked, HZ); | |
541 | if (ret > 0 && rspi->dma_callbacked) | |
542 | ret = 0; | |
543 | else if (!ret) | |
544 | ret = -ETIMEDOUT; | |
545 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
546 | ||
93722206 | 547 | enable_irq(rspi->tx_irq); |
a3633fe7 SY |
548 | |
549 | end: | |
550 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
551 | end_nomap: | |
552 | if (rspi->dma_width_16bit) | |
553 | kfree(buf); | |
554 | ||
555 | return ret; | |
556 | } | |
557 | ||
baf588f4 | 558 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 559 | { |
97b95c11 | 560 | u8 spsr; |
0b2182dd SY |
561 | |
562 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
563 | if (spsr & SPSR_SPRF) | |
74da7686 | 564 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
565 | if (spsr & SPSR_OVRF) |
566 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 567 | RSPI_SPSR); |
a3633fe7 SY |
568 | } |
569 | ||
862d357f GU |
570 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
571 | { | |
572 | rspi_receive_init(rspi); | |
573 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
574 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
575 | } | |
576 | ||
baf588f4 | 577 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 578 | { |
97b95c11 | 579 | u8 spsr; |
cb52c673 HCM |
580 | |
581 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
582 | if (spsr & SPSR_SPRF) | |
74da7686 | 583 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 584 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 585 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
586 | } |
587 | ||
a3633fe7 SY |
588 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
589 | { | |
590 | struct scatterlist sg, sg_dummy; | |
591 | void *dummy = NULL, *rx_buf = NULL; | |
592 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
93722206 | 593 | unsigned int len; |
a3633fe7 SY |
594 | int ret = 0; |
595 | ||
596 | if (rspi->dma_width_16bit) { | |
597 | /* | |
598 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
599 | * buffer. And, finally the driver converts the DMAC data into | |
600 | * actual data as the following format: | |
601 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
602 | * actual data: 1st byte, 2nd byte ... | |
603 | */ | |
604 | len = t->len * 2; | |
605 | rx_buf = kmalloc(len, GFP_KERNEL); | |
606 | if (!rx_buf) | |
607 | return -ENOMEM; | |
608 | } else { | |
609 | len = t->len; | |
610 | rx_buf = t->rx_buf; | |
611 | } | |
612 | ||
613 | /* prepare dummy transfer to generate SPI clocks */ | |
614 | dummy = kzalloc(len, GFP_KERNEL); | |
615 | if (!dummy) { | |
616 | ret = -ENOMEM; | |
617 | goto end_nomap; | |
618 | } | |
619 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
620 | DMA_TO_DEVICE)) { | |
621 | ret = -EFAULT; | |
622 | goto end_nomap; | |
623 | } | |
624 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
625 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
626 | if (!desc_dummy) { | |
627 | ret = -EIO; | |
628 | goto end_dummy_mapped; | |
629 | } | |
630 | ||
631 | /* prepare receive transfer */ | |
632 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
633 | DMA_FROM_DEVICE)) { | |
634 | ret = -EFAULT; | |
635 | goto end_dummy_mapped; | |
636 | ||
637 | } | |
638 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
639 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
640 | if (!desc) { | |
641 | ret = -EIO; | |
642 | goto end; | |
643 | } | |
644 | ||
645 | rspi_receive_init(rspi); | |
646 | ||
647 | /* | |
648 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
649 | * called. So, this driver disables the IRQ while DMA transfer. | |
650 | */ | |
93722206 GU |
651 | disable_irq(rspi->tx_irq); |
652 | if (rspi->rx_irq != rspi->tx_irq) | |
653 | disable_irq(rspi->rx_irq); | |
a3633fe7 SY |
654 | |
655 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
656 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
657 | rspi->dma_callbacked = 0; | |
658 | ||
659 | desc->callback = rspi_dma_complete; | |
660 | desc->callback_param = rspi; | |
661 | dmaengine_submit(desc); | |
662 | dma_async_issue_pending(rspi->chan_rx); | |
663 | ||
664 | desc_dummy->callback = NULL; /* No callback */ | |
665 | dmaengine_submit(desc_dummy); | |
666 | dma_async_issue_pending(rspi->chan_tx); | |
667 | ||
668 | ret = wait_event_interruptible_timeout(rspi->wait, | |
669 | rspi->dma_callbacked, HZ); | |
670 | if (ret > 0 && rspi->dma_callbacked) | |
671 | ret = 0; | |
672 | else if (!ret) | |
673 | ret = -ETIMEDOUT; | |
674 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
675 | ||
93722206 GU |
676 | enable_irq(rspi->tx_irq); |
677 | if (rspi->rx_irq != rspi->tx_irq) | |
678 | enable_irq(rspi->rx_irq); | |
a3633fe7 SY |
679 | |
680 | end: | |
681 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
682 | end_dummy_mapped: | |
683 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
684 | end_nomap: | |
685 | if (rspi->dma_width_16bit) { | |
686 | if (!ret) | |
687 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
688 | kfree(rx_buf); | |
689 | } | |
690 | kfree(dummy); | |
691 | ||
692 | return ret; | |
693 | } | |
694 | ||
baf588f4 | 695 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
696 | { |
697 | if (t->tx_buf && rspi->chan_tx) | |
698 | return 1; | |
699 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
700 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
701 | return 1; | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
8449fd76 GU |
706 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
707 | struct spi_transfer *xfer) | |
708 | { | |
709 | int remain = xfer->len, ret; | |
710 | const u8 *tx_buf = xfer->tx_buf; | |
711 | u8 *rx_buf = xfer->rx_buf; | |
712 | u8 spcr, data; | |
713 | ||
714 | rspi_receive_init(rspi); | |
715 | ||
716 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
717 | if (rx_buf) | |
718 | spcr &= ~SPCR_TXMD; | |
719 | else | |
720 | spcr |= SPCR_TXMD; | |
721 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
722 | ||
723 | while (remain > 0) { | |
724 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
725 | ret = rspi_data_out(rspi, data); | |
726 | if (ret < 0) | |
727 | return ret; | |
728 | if (rx_buf) { | |
729 | ret = rspi_data_in(rspi); | |
730 | if (ret < 0) | |
731 | return ret; | |
732 | *rx_buf++ = ret; | |
733 | } | |
734 | remain--; | |
735 | } | |
736 | ||
737 | /* Wait for the last transmission */ | |
738 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
79d23495 GU |
743 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
744 | struct spi_transfer *xfer) | |
0b2182dd | 745 | { |
79d23495 | 746 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
747 | int ret; |
748 | ||
749 | if (!rspi_is_dma(rspi, xfer)) | |
750 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 751 | |
79d23495 | 752 | if (xfer->tx_buf) { |
8449fd76 | 753 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
754 | if (ret < 0) |
755 | return ret; | |
0b2182dd | 756 | } |
8449fd76 GU |
757 | if (xfer->rx_buf) |
758 | return rspi_receive_dma(rspi, xfer); | |
759 | ||
760 | return 0; | |
eb557f75 GU |
761 | } |
762 | ||
862d357f GU |
763 | static int rspi_rz_transfer_out_in(struct rspi_data *rspi, |
764 | struct spi_transfer *xfer) | |
765 | { | |
766 | int remain = xfer->len, ret; | |
767 | const u8 *tx_buf = xfer->tx_buf; | |
768 | u8 *rx_buf = xfer->rx_buf; | |
769 | u8 data; | |
770 | ||
771 | rspi_rz_receive_init(rspi); | |
772 | ||
773 | while (remain > 0) { | |
774 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
775 | ret = rspi_data_out_in(rspi, data); | |
776 | if (ret < 0) | |
777 | return ret; | |
778 | if (rx_buf) | |
779 | *rx_buf++ = ret; | |
780 | remain--; | |
781 | } | |
782 | ||
783 | /* Wait for the last transmission */ | |
784 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static int rspi_rz_transfer_one(struct spi_master *master, | |
790 | struct spi_device *spi, | |
791 | struct spi_transfer *xfer) | |
792 | { | |
793 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
794 | ||
795 | return rspi_rz_transfer_out_in(rspi, xfer); | |
796 | } | |
797 | ||
340a15e6 GU |
798 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
799 | struct spi_transfer *xfer) | |
eb557f75 | 800 | { |
340a15e6 GU |
801 | int remain = xfer->len, ret; |
802 | const u8 *tx_buf = xfer->tx_buf; | |
803 | u8 *rx_buf = xfer->rx_buf; | |
804 | u8 data; | |
eb557f75 | 805 | |
340a15e6 GU |
806 | qspi_receive_init(rspi); |
807 | ||
808 | while (remain > 0) { | |
809 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
810 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
811 | if (ret < 0) |
812 | return ret; | |
340a15e6 GU |
813 | if (rx_buf) |
814 | *rx_buf++ = ret; | |
815 | remain--; | |
79d23495 | 816 | } |
340a15e6 GU |
817 | |
818 | /* Wait for the last transmission */ | |
819 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
880c6d11 GU |
824 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
825 | { | |
826 | const u8 *buf = xfer->tx_buf; | |
827 | unsigned int i; | |
828 | int ret; | |
829 | ||
830 | for (i = 0; i < xfer->len; i++) { | |
831 | ret = rspi_data_out(rspi, *buf++); | |
832 | if (ret < 0) | |
833 | return ret; | |
834 | } | |
835 | ||
836 | /* Wait for the last transmission */ | |
837 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
843 | { | |
844 | u8 *buf = xfer->rx_buf; | |
845 | unsigned int i; | |
846 | int ret; | |
847 | ||
848 | for (i = 0; i < xfer->len; i++) { | |
849 | ret = rspi_data_in(rspi); | |
850 | if (ret < 0) | |
851 | return ret; | |
852 | *buf++ = ret; | |
853 | } | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
340a15e6 GU |
858 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
859 | struct spi_transfer *xfer) | |
860 | { | |
861 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
862 | ||
ba824d49 GU |
863 | if (spi->mode & SPI_LOOP) { |
864 | return qspi_transfer_out_in(rspi, xfer); | |
865 | } else if (xfer->tx_buf && xfer->tx_nbits > SPI_NBITS_SINGLE) { | |
880c6d11 GU |
866 | /* Quad or Dual SPI Write */ |
867 | return qspi_transfer_out(rspi, xfer); | |
868 | } else if (xfer->rx_buf && xfer->rx_nbits > SPI_NBITS_SINGLE) { | |
869 | /* Quad or Dual SPI Read */ | |
870 | return qspi_transfer_in(rspi, xfer); | |
871 | } else { | |
872 | /* Single SPI Transfer */ | |
873 | return qspi_transfer_out_in(rspi, xfer); | |
874 | } | |
0b2182dd SY |
875 | } |
876 | ||
877 | static int rspi_setup(struct spi_device *spi) | |
878 | { | |
879 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
880 | ||
0b2182dd SY |
881 | rspi->max_speed_hz = spi->max_speed_hz; |
882 | ||
348e5153 GU |
883 | rspi->spcmd = SPCMD_SSLKP; |
884 | if (spi->mode & SPI_CPOL) | |
885 | rspi->spcmd |= SPCMD_CPOL; | |
886 | if (spi->mode & SPI_CPHA) | |
887 | rspi->spcmd |= SPCMD_CPHA; | |
888 | ||
06a7a3cf GU |
889 | /* CMOS output mode and MOSI signal from previous transfer */ |
890 | rspi->sppcr = 0; | |
891 | if (spi->mode & SPI_LOOP) | |
892 | rspi->sppcr |= SPPCR_SPLP; | |
893 | ||
5ce0ba88 | 894 | set_config_register(rspi, 8); |
0b2182dd SY |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
880c6d11 GU |
899 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
900 | { | |
901 | if (xfer->tx_buf) | |
902 | switch (xfer->tx_nbits) { | |
903 | case SPI_NBITS_QUAD: | |
904 | return SPCMD_SPIMOD_QUAD; | |
905 | case SPI_NBITS_DUAL: | |
906 | return SPCMD_SPIMOD_DUAL; | |
907 | default: | |
908 | return 0; | |
909 | } | |
910 | if (xfer->rx_buf) | |
911 | switch (xfer->rx_nbits) { | |
912 | case SPI_NBITS_QUAD: | |
913 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
914 | case SPI_NBITS_DUAL: | |
915 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
916 | default: | |
917 | return 0; | |
918 | } | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
923 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
924 | const struct spi_message *msg) | |
925 | { | |
926 | const struct spi_transfer *xfer; | |
927 | unsigned int i = 0, len = 0; | |
928 | u16 current_mode = 0xffff, mode; | |
929 | ||
930 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
931 | mode = qspi_transfer_mode(xfer); | |
932 | if (mode == current_mode) { | |
933 | len += xfer->len; | |
934 | continue; | |
935 | } | |
936 | ||
937 | /* Transfer mode change */ | |
938 | if (i) { | |
939 | /* Set transfer data length of previous transfer */ | |
940 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
941 | } | |
942 | ||
943 | if (i >= QSPI_NUM_SPCMD) { | |
944 | dev_err(&msg->spi->dev, | |
945 | "Too many different transfer modes"); | |
946 | return -EINVAL; | |
947 | } | |
948 | ||
949 | /* Program transfer mode for this transfer */ | |
950 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
951 | current_mode = mode; | |
952 | len = xfer->len; | |
953 | i++; | |
954 | } | |
955 | if (i) { | |
956 | /* Set final transfer data length and sequence length */ | |
957 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
958 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
959 | } | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
79d23495 | 964 | static int rspi_prepare_message(struct spi_master *master, |
880c6d11 | 965 | struct spi_message *msg) |
79d23495 GU |
966 | { |
967 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
880c6d11 | 968 | int ret; |
0b2182dd | 969 | |
880c6d11 GU |
970 | if (msg->spi->mode & |
971 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
972 | /* Setup sequencer for messages with multiple transfer modes */ | |
973 | ret = qspi_setup_sequencer(rspi, msg); | |
974 | if (ret < 0) | |
975 | return ret; | |
976 | } | |
977 | ||
978 | /* Enable SPI function in master mode */ | |
79d23495 | 979 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
980 | return 0; |
981 | } | |
982 | ||
79d23495 | 983 | static int rspi_unprepare_message(struct spi_master *master, |
880c6d11 | 984 | struct spi_message *msg) |
0b2182dd | 985 | { |
79d23495 GU |
986 | struct rspi_data *rspi = spi_master_get_devdata(master); |
987 | ||
880c6d11 | 988 | /* Disable SPI function */ |
79d23495 | 989 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
990 | |
991 | /* Reset sequencer for Single SPI Transfers */ | |
992 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
993 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 994 | return 0; |
0b2182dd SY |
995 | } |
996 | ||
93722206 | 997 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 998 | { |
c132f094 | 999 | struct rspi_data *rspi = _sr; |
97b95c11 | 1000 | u8 spsr; |
0b2182dd | 1001 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 1002 | u8 disable_irq = 0; |
0b2182dd SY |
1003 | |
1004 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1005 | if (spsr & SPSR_SPRF) | |
1006 | disable_irq |= SPCR_SPRIE; | |
1007 | if (spsr & SPSR_SPTEF) | |
1008 | disable_irq |= SPCR_SPTIE; | |
1009 | ||
1010 | if (disable_irq) { | |
1011 | ret = IRQ_HANDLED; | |
1012 | rspi_disable_irq(rspi, disable_irq); | |
1013 | wake_up(&rspi->wait); | |
1014 | } | |
1015 | ||
1016 | return ret; | |
1017 | } | |
1018 | ||
93722206 GU |
1019 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
1020 | { | |
1021 | struct rspi_data *rspi = _sr; | |
1022 | u8 spsr; | |
1023 | ||
1024 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1025 | if (spsr & SPSR_SPRF) { | |
1026 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
1027 | wake_up(&rspi->wait); | |
1028 | return IRQ_HANDLED; | |
1029 | } | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
1035 | { | |
1036 | struct rspi_data *rspi = _sr; | |
1037 | u8 spsr; | |
1038 | ||
1039 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
1040 | if (spsr & SPSR_SPTEF) { | |
1041 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
1042 | wake_up(&rspi->wait); | |
1043 | return IRQ_HANDLED; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
fd4a319b | 1049 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 1050 | struct platform_device *pdev) |
a3633fe7 | 1051 | { |
baf588f4 | 1052 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 1053 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 1054 | dma_cap_mask_t mask; |
0243c536 SY |
1055 | struct dma_slave_config cfg; |
1056 | int ret; | |
a3633fe7 | 1057 | |
e2b05099 | 1058 | if (!res || !rspi_pd) |
0243c536 | 1059 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
1060 | |
1061 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
1062 | ||
1063 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
1064 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
1065 | dma_cap_zero(mask); | |
1066 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1067 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
1068 | (void *)rspi_pd->dma_rx_id); | |
1069 | if (rspi->chan_rx) { | |
1070 | cfg.slave_id = rspi_pd->dma_rx_id; | |
1071 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
1072 | cfg.dst_addr = 0; |
1073 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
1074 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
1075 | if (!ret) | |
1076 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
1077 | else | |
1078 | return ret; | |
1079 | } | |
a3633fe7 SY |
1080 | } |
1081 | if (rspi_pd->dma_tx_id) { | |
1082 | dma_cap_zero(mask); | |
1083 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
1084 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
1085 | (void *)rspi_pd->dma_tx_id); | |
1086 | if (rspi->chan_tx) { | |
1087 | cfg.slave_id = rspi_pd->dma_tx_id; | |
1088 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
1089 | cfg.dst_addr = res->start + RSPI_SPDR; |
1090 | cfg.src_addr = 0; | |
0243c536 SY |
1091 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
1092 | if (!ret) | |
1093 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
1094 | else | |
1095 | return ret; | |
1096 | } | |
a3633fe7 | 1097 | } |
0243c536 SY |
1098 | |
1099 | return 0; | |
a3633fe7 SY |
1100 | } |
1101 | ||
fd4a319b | 1102 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
1103 | { |
1104 | if (rspi->chan_tx) | |
1105 | dma_release_channel(rspi->chan_tx); | |
1106 | if (rspi->chan_rx) | |
1107 | dma_release_channel(rspi->chan_rx); | |
1108 | } | |
1109 | ||
fd4a319b | 1110 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 1111 | { |
5ffbe2d9 | 1112 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 1113 | |
a3633fe7 | 1114 | rspi_release_dma(rspi); |
490c9774 | 1115 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1116 | |
1117 | return 0; | |
1118 | } | |
1119 | ||
426ef76d GU |
1120 | static const struct spi_ops rspi_ops = { |
1121 | .set_config_register = rspi_set_config_register, | |
1122 | .transfer_one = rspi_transfer_one, | |
880c6d11 | 1123 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1124 | }; |
1125 | ||
1126 | static const struct spi_ops rspi_rz_ops = { | |
1127 | .set_config_register = rspi_rz_set_config_register, | |
1128 | .transfer_one = rspi_rz_transfer_one, | |
880c6d11 | 1129 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, |
426ef76d GU |
1130 | }; |
1131 | ||
1132 | static const struct spi_ops qspi_ops = { | |
1133 | .set_config_register = qspi_set_config_register, | |
1134 | .transfer_one = qspi_transfer_one, | |
880c6d11 GU |
1135 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | |
1136 | SPI_TX_DUAL | SPI_TX_QUAD | | |
1137 | SPI_RX_DUAL | SPI_RX_QUAD, | |
426ef76d GU |
1138 | }; |
1139 | ||
1140 | #ifdef CONFIG_OF | |
1141 | static const struct of_device_id rspi_of_match[] = { | |
1142 | /* RSPI on legacy SH */ | |
1143 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
1144 | /* RSPI on RZ/A1H */ | |
1145 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
1146 | /* QSPI on R-Car Gen2 */ | |
1147 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
1148 | { /* sentinel */ } | |
1149 | }; | |
1150 | ||
1151 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
1152 | ||
1153 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
1154 | { | |
1155 | u32 num_cs; | |
1156 | int error; | |
1157 | ||
1158 | /* Parse DT properties */ | |
1159 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
1160 | if (error) { | |
1161 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
1162 | return error; | |
1163 | } | |
1164 | ||
1165 | master->num_chipselect = num_cs; | |
1166 | return 0; | |
1167 | } | |
1168 | #else | |
64b67def | 1169 | #define rspi_of_match NULL |
426ef76d GU |
1170 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) |
1171 | { | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | #endif /* CONFIG_OF */ | |
1175 | ||
93722206 GU |
1176 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1177 | irq_handler_t handler, const char *suffix, | |
1178 | void *dev_id) | |
1179 | { | |
1180 | const char *base = dev_name(dev); | |
1181 | size_t len = strlen(base) + strlen(suffix) + 2; | |
1182 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
1183 | if (!name) | |
1184 | return -ENOMEM; | |
1185 | snprintf(name, len, "%s:%s", base, suffix); | |
1186 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
1187 | } | |
1188 | ||
fd4a319b | 1189 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1190 | { |
1191 | struct resource *res; | |
1192 | struct spi_master *master; | |
1193 | struct rspi_data *rspi; | |
93722206 | 1194 | int ret; |
426ef76d GU |
1195 | const struct of_device_id *of_id; |
1196 | const struct rspi_plat_data *rspi_pd; | |
5ce0ba88 | 1197 | const struct spi_ops *ops; |
0b2182dd | 1198 | |
0b2182dd SY |
1199 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1200 | if (master == NULL) { | |
1201 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1202 | return -ENOMEM; | |
1203 | } | |
1204 | ||
426ef76d GU |
1205 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
1206 | if (of_id) { | |
1207 | ops = of_id->data; | |
1208 | ret = rspi_parse_dt(&pdev->dev, master); | |
1209 | if (ret) | |
1210 | goto error1; | |
1211 | } else { | |
1212 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1213 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1214 | if (rspi_pd && rspi_pd->num_chipselect) | |
1215 | master->num_chipselect = rspi_pd->num_chipselect; | |
1216 | else | |
1217 | master->num_chipselect = 2; /* default */ | |
1218 | }; | |
1219 | ||
1220 | /* ops parameter check */ | |
1221 | if (!ops->set_config_register) { | |
1222 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1223 | ret = -ENODEV; | |
1224 | goto error1; | |
1225 | } | |
1226 | ||
0b2182dd | 1227 | rspi = spi_master_get_devdata(master); |
24b5a82c | 1228 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1229 | rspi->ops = ops; |
0b2182dd | 1230 | rspi->master = master; |
5d79e9ac LP |
1231 | |
1232 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1233 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1234 | if (IS_ERR(rspi->addr)) { | |
1235 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1236 | goto error1; |
1237 | } | |
1238 | ||
29f397b7 | 1239 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1240 | if (IS_ERR(rspi->clk)) { |
1241 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1242 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1243 | goto error1; |
0b2182dd | 1244 | } |
17fe0d9a | 1245 | |
490c9774 | 1246 | pm_runtime_enable(&pdev->dev); |
0b2182dd | 1247 | |
0b2182dd SY |
1248 | init_waitqueue_head(&rspi->wait); |
1249 | ||
0b2182dd SY |
1250 | master->bus_num = pdev->id; |
1251 | master->setup = rspi_setup; | |
490c9774 | 1252 | master->auto_runtime_pm = true; |
eb557f75 | 1253 | master->transfer_one = ops->transfer_one; |
79d23495 GU |
1254 | master->prepare_message = rspi_prepare_message; |
1255 | master->unprepare_message = rspi_unprepare_message; | |
880c6d11 | 1256 | master->mode_bits = ops->mode_bits; |
426ef76d | 1257 | master->dev.of_node = pdev->dev.of_node; |
0b2182dd | 1258 | |
93722206 GU |
1259 | ret = platform_get_irq_byname(pdev, "rx"); |
1260 | if (ret < 0) { | |
1261 | ret = platform_get_irq_byname(pdev, "mux"); | |
1262 | if (ret < 0) | |
1263 | ret = platform_get_irq(pdev, 0); | |
1264 | if (ret >= 0) | |
1265 | rspi->rx_irq = rspi->tx_irq = ret; | |
1266 | } else { | |
1267 | rspi->rx_irq = ret; | |
1268 | ret = platform_get_irq_byname(pdev, "tx"); | |
1269 | if (ret >= 0) | |
1270 | rspi->tx_irq = ret; | |
1271 | } | |
1272 | if (ret < 0) { | |
1273 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1274 | goto error2; | |
1275 | } | |
1276 | ||
1277 | if (rspi->rx_irq == rspi->tx_irq) { | |
1278 | /* Single multiplexed interrupt */ | |
1279 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1280 | "mux", rspi); | |
1281 | } else { | |
1282 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1283 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1284 | "rx", rspi); | |
1285 | if (!ret) | |
1286 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1287 | rspi_irq_tx, "tx", rspi); | |
1288 | } | |
0b2182dd SY |
1289 | if (ret < 0) { |
1290 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1291 | goto error2; |
0b2182dd SY |
1292 | } |
1293 | ||
0243c536 SY |
1294 | ret = rspi_request_dma(rspi, pdev); |
1295 | if (ret < 0) { | |
1296 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 1297 | goto error3; |
0243c536 | 1298 | } |
a3633fe7 | 1299 | |
9e03d05e | 1300 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1301 | if (ret < 0) { |
1302 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1303 | goto error3; |
0b2182dd SY |
1304 | } |
1305 | ||
1306 | dev_info(&pdev->dev, "probed\n"); | |
1307 | ||
1308 | return 0; | |
1309 | ||
fcb4ed74 | 1310 | error3: |
5d79e9ac | 1311 | rspi_release_dma(rspi); |
fcb4ed74 | 1312 | error2: |
490c9774 | 1313 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1314 | error1: |
1315 | spi_master_put(master); | |
1316 | ||
1317 | return ret; | |
1318 | } | |
1319 | ||
5ce0ba88 HCM |
1320 | static struct platform_device_id spi_driver_ids[] = { |
1321 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1322 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1323 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1324 | {}, | |
1325 | }; | |
1326 | ||
1327 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1328 | ||
0b2182dd SY |
1329 | static struct platform_driver rspi_driver = { |
1330 | .probe = rspi_probe, | |
fd4a319b | 1331 | .remove = rspi_remove, |
5ce0ba88 | 1332 | .id_table = spi_driver_ids, |
0b2182dd | 1333 | .driver = { |
5ce0ba88 | 1334 | .name = "renesas_spi", |
0b2182dd | 1335 | .owner = THIS_MODULE, |
426ef76d | 1336 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1337 | }, |
1338 | }; | |
1339 | module_platform_driver(rspi_driver); | |
1340 | ||
1341 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1342 | MODULE_LICENSE("GPL v2"); | |
1343 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1344 | MODULE_ALIAS("platform:rspi"); |