Commit | Line | Data |
---|---|---|
ca632f55 | 1 | /* |
7fba5340 | 2 | * Copyright (c) 2006 Ben Dooks |
bec0806c | 3 | * Copyright 2006-2009 Simtec Electronics |
7fba5340 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
7fba5340 | 12 | #include <linux/spinlock.h> |
7fba5340 BD |
13 | #include <linux/interrupt.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/platform_device.h> | |
ee9c1fbf | 19 | #include <linux/gpio.h> |
1a0c220f | 20 | #include <linux/io.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
7fba5340 BD |
22 | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/spi/spi_bitbang.h> | |
f35ef7ca | 25 | #include <linux/spi/s3c24xx.h> |
d7614de4 | 26 | #include <linux/module.h> |
7fba5340 | 27 | |
13622708 | 28 | #include <plat/regs-spi.h> |
7fba5340 | 29 | |
bec0806c BD |
30 | #include <asm/fiq.h> |
31 | ||
ca632f55 | 32 | #include "spi-s3c24xx-fiq.h" |
bec0806c | 33 | |
570327d9 BD |
34 | /** |
35 | * s3c24xx_spi_devstate - per device data | |
36 | * @hz: Last frequency calculated for @sppre field. | |
37 | * @mode: Last mode setting for the @spcon field. | |
38 | * @spcon: Value to write to the SPCON register. | |
39 | * @sppre: Value to write to the SPPRE register. | |
40 | */ | |
41 | struct s3c24xx_spi_devstate { | |
42 | unsigned int hz; | |
43 | unsigned int mode; | |
44 | u8 spcon; | |
45 | u8 sppre; | |
46 | }; | |
47 | ||
bec0806c BD |
48 | enum spi_fiq_mode { |
49 | FIQ_MODE_NONE = 0, | |
50 | FIQ_MODE_TX = 1, | |
51 | FIQ_MODE_RX = 2, | |
52 | FIQ_MODE_TXRX = 3, | |
53 | }; | |
54 | ||
7fba5340 BD |
55 | struct s3c24xx_spi { |
56 | /* bitbang has to be first */ | |
57 | struct spi_bitbang bitbang; | |
58 | struct completion done; | |
59 | ||
60 | void __iomem *regs; | |
61 | int irq; | |
62 | int len; | |
63 | int count; | |
64 | ||
bec0806c BD |
65 | struct fiq_handler fiq_handler; |
66 | enum spi_fiq_mode fiq_mode; | |
67 | unsigned char fiq_inuse; | |
68 | unsigned char fiq_claimed; | |
69 | ||
6c912a3d | 70 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
71 | int cs, int pol); |
72 | ||
7fba5340 BD |
73 | /* data buffers */ |
74 | const unsigned char *tx; | |
75 | unsigned char *rx; | |
76 | ||
77 | struct clk *clk; | |
7fba5340 BD |
78 | struct spi_master *master; |
79 | struct spi_device *curdev; | |
80 | struct device *dev; | |
81 | struct s3c2410_spi_info *pdata; | |
82 | }; | |
83 | ||
84 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
85 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
86 | ||
87 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
88 | { | |
89 | return spi_master_get_devdata(sdev->master); | |
90 | } | |
91 | ||
8736b927 BD |
92 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
93 | { | |
ee9c1fbf | 94 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
95 | } |
96 | ||
7fba5340 BD |
97 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
98 | { | |
570327d9 | 99 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
100 | struct s3c24xx_spi *hw = to_hw(spi); |
101 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
570327d9 BD |
102 | |
103 | /* change the chipselect state and the state of the spi engine clock */ | |
7fba5340 BD |
104 | |
105 | switch (value) { | |
106 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 107 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
570327d9 | 108 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
7fba5340 BD |
109 | break; |
110 | ||
111 | case BITBANG_CS_ACTIVE: | |
570327d9 BD |
112 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
113 | hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 114 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 | 115 | break; |
7fba5340 BD |
116 | } |
117 | } | |
118 | ||
570327d9 BD |
119 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
120 | struct spi_transfer *t) | |
7fba5340 BD |
121 | { |
122 | struct s3c24xx_spi *hw = to_hw(spi); | |
570327d9 | 123 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
7fba5340 BD |
124 | unsigned int hz; |
125 | unsigned int div; | |
b8978784 | 126 | unsigned long clk; |
7fba5340 | 127 | |
7fba5340 BD |
128 | hz = t ? t->speed_hz : spi->max_speed_hz; |
129 | ||
19152975 BD |
130 | if (!hz) |
131 | hz = spi->max_speed_hz; | |
132 | ||
570327d9 | 133 | if (spi->mode != cs->mode) { |
bec0806c | 134 | u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; |
570327d9 BD |
135 | |
136 | if (spi->mode & SPI_CPHA) | |
137 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
7fba5340 | 138 | |
570327d9 BD |
139 | if (spi->mode & SPI_CPOL) |
140 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
7fba5340 | 141 | |
570327d9 BD |
142 | cs->mode = spi->mode; |
143 | cs->spcon = spcon; | |
144 | } | |
b8978784 | 145 | |
570327d9 BD |
146 | if (cs->hz != hz) { |
147 | clk = clk_get_rate(hw->clk); | |
148 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
b8978784 | 149 | |
570327d9 BD |
150 | if (div > 255) |
151 | div = 255; | |
7fba5340 | 152 | |
570327d9 BD |
153 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
154 | div, hz, clk / (2 * (div + 1))); | |
155 | ||
156 | cs->hz = hz; | |
157 | cs->sppre = div; | |
7fba5340 | 158 | } |
7fba5340 BD |
159 | |
160 | return 0; | |
161 | } | |
162 | ||
570327d9 BD |
163 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
164 | struct spi_transfer *t) | |
165 | { | |
166 | struct s3c24xx_spi_devstate *cs = spi->controller_state; | |
167 | struct s3c24xx_spi *hw = to_hw(spi); | |
168 | int ret; | |
169 | ||
170 | ret = s3c24xx_spi_update_state(spi, t); | |
171 | if (!ret) | |
172 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
7fba5340 BD |
177 | static int s3c24xx_spi_setup(struct spi_device *spi) |
178 | { | |
570327d9 BD |
179 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
180 | struct s3c24xx_spi *hw = to_hw(spi); | |
7fba5340 BD |
181 | int ret; |
182 | ||
570327d9 BD |
183 | /* allocate settings on the first call */ |
184 | if (!cs) { | |
c586feba AL |
185 | cs = devm_kzalloc(&spi->dev, |
186 | sizeof(struct s3c24xx_spi_devstate), | |
187 | GFP_KERNEL); | |
0375cff5 | 188 | if (!cs) |
570327d9 | 189 | return -ENOMEM; |
570327d9 BD |
190 | |
191 | cs->spcon = SPCON_DEFAULT; | |
192 | cs->hz = -1; | |
193 | spi->controller_state = cs; | |
194 | } | |
195 | ||
196 | /* initialise the state from the device */ | |
197 | ret = s3c24xx_spi_update_state(spi, NULL); | |
198 | if (ret) | |
7fba5340 | 199 | return ret; |
570327d9 BD |
200 | |
201 | spin_lock(&hw->bitbang.lock); | |
202 | if (!hw->bitbang.busy) { | |
203 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
204 | /* need to ndelay for 0.5 clocktick ? */ | |
7fba5340 | 205 | } |
570327d9 | 206 | spin_unlock(&hw->bitbang.lock); |
7fba5340 | 207 | |
7fba5340 BD |
208 | return 0; |
209 | } | |
210 | ||
211 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) | |
212 | { | |
4b1badf5 | 213 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
214 | } |
215 | ||
bec0806c BD |
216 | #ifdef CONFIG_SPI_S3C24XX_FIQ |
217 | /* Support for FIQ based pseudo-DMA to improve the transfer speed. | |
218 | * | |
219 | * This code uses the assembly helper in spi_s3c24xx_spi.S which is | |
220 | * used by the FIQ core to move data between main memory and the peripheral | |
221 | * block. Since this is code running on the processor, there is no problem | |
222 | * with cache coherency of the buffers, so we can use any buffer we like. | |
223 | */ | |
224 | ||
225 | /** | |
226 | * struct spi_fiq_code - FIQ code and header | |
227 | * @length: The length of the code fragment, excluding this header. | |
228 | * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at. | |
229 | * @data: The code itself to install as a FIQ handler. | |
230 | */ | |
231 | struct spi_fiq_code { | |
232 | u32 length; | |
233 | u32 ack_offset; | |
234 | u8 data[0]; | |
235 | }; | |
236 | ||
237 | extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; | |
238 | extern struct spi_fiq_code s3c24xx_spi_fiq_tx; | |
239 | extern struct spi_fiq_code s3c24xx_spi_fiq_rx; | |
240 | ||
241 | /** | |
242 | * ack_bit - turn IRQ into IRQ acknowledgement bit | |
243 | * @irq: The interrupt number | |
244 | * | |
245 | * Returns the bit to write to the interrupt acknowledge register. | |
246 | */ | |
247 | static inline u32 ack_bit(unsigned int irq) | |
248 | { | |
249 | return 1 << (irq - IRQ_EINT0); | |
250 | } | |
251 | ||
252 | /** | |
253 | * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer | |
254 | * @hw: The hardware state. | |
255 | * | |
256 | * Claim the FIQ handler (only one can be active at any one time) and | |
257 | * then setup the correct transfer code for this transfer. | |
258 | * | |
3ad2f3fb | 259 | * This call updates all the necessary state information if successful, |
bec0806c BD |
260 | * so the caller does not need to do anything more than start the transfer |
261 | * as normal, since the IRQ will have been re-routed to the FIQ handler. | |
262 | */ | |
cfeb3312 | 263 | static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) |
bec0806c BD |
264 | { |
265 | struct pt_regs regs; | |
266 | enum spi_fiq_mode mode; | |
267 | struct spi_fiq_code *code; | |
268 | int ret; | |
269 | ||
270 | if (!hw->fiq_claimed) { | |
271 | /* try and claim fiq if we haven't got it, and if not | |
272 | * then return and simply use another transfer method */ | |
273 | ||
274 | ret = claim_fiq(&hw->fiq_handler); | |
275 | if (ret) | |
276 | return; | |
277 | } | |
278 | ||
279 | if (hw->tx && !hw->rx) | |
280 | mode = FIQ_MODE_TX; | |
281 | else if (hw->rx && !hw->tx) | |
282 | mode = FIQ_MODE_RX; | |
283 | else | |
284 | mode = FIQ_MODE_TXRX; | |
285 | ||
286 | regs.uregs[fiq_rspi] = (long)hw->regs; | |
287 | regs.uregs[fiq_rrx] = (long)hw->rx; | |
288 | regs.uregs[fiq_rtx] = (long)hw->tx + 1; | |
289 | regs.uregs[fiq_rcount] = hw->len - 1; | |
290 | regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ; | |
291 | ||
292 | set_fiq_regs(®s); | |
293 | ||
294 | if (hw->fiq_mode != mode) { | |
295 | u32 *ack_ptr; | |
296 | ||
297 | hw->fiq_mode = mode; | |
298 | ||
299 | switch (mode) { | |
300 | case FIQ_MODE_TX: | |
301 | code = &s3c24xx_spi_fiq_tx; | |
302 | break; | |
303 | case FIQ_MODE_RX: | |
304 | code = &s3c24xx_spi_fiq_rx; | |
305 | break; | |
306 | case FIQ_MODE_TXRX: | |
307 | code = &s3c24xx_spi_fiq_txrx; | |
308 | break; | |
309 | default: | |
310 | code = NULL; | |
311 | } | |
312 | ||
313 | BUG_ON(!code); | |
314 | ||
315 | ack_ptr = (u32 *)&code->data[code->ack_offset]; | |
316 | *ack_ptr = ack_bit(hw->irq); | |
317 | ||
318 | set_fiq_handler(&code->data, code->length); | |
319 | } | |
320 | ||
321 | s3c24xx_set_fiq(hw->irq, true); | |
322 | ||
323 | hw->fiq_mode = mode; | |
324 | hw->fiq_inuse = 1; | |
325 | } | |
326 | ||
327 | /** | |
328 | * s3c24xx_spi_fiqop - FIQ core code callback | |
329 | * @pw: Data registered with the handler | |
330 | * @release: Whether this is a release or a return. | |
331 | * | |
332 | * Called by the FIQ code when another module wants to use the FIQ, so | |
333 | * return whether we are currently using this or not and then update our | |
334 | * internal state. | |
335 | */ | |
336 | static int s3c24xx_spi_fiqop(void *pw, int release) | |
337 | { | |
338 | struct s3c24xx_spi *hw = pw; | |
339 | int ret = 0; | |
340 | ||
341 | if (release) { | |
342 | if (hw->fiq_inuse) | |
343 | ret = -EBUSY; | |
344 | ||
345 | /* note, we do not need to unroute the FIQ, as the FIQ | |
346 | * vector code de-routes it to signal the end of transfer */ | |
347 | ||
348 | hw->fiq_mode = FIQ_MODE_NONE; | |
349 | hw->fiq_claimed = 0; | |
350 | } else { | |
351 | hw->fiq_claimed = 1; | |
352 | } | |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
357 | /** | |
358 | * s3c24xx_spi_initfiq - setup the information for the FIQ core | |
359 | * @hw: The hardware state. | |
360 | * | |
361 | * Setup the fiq_handler block to pass to the FIQ core. | |
362 | */ | |
363 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) | |
364 | { | |
365 | hw->fiq_handler.dev_id = hw; | |
366 | hw->fiq_handler.name = dev_name(hw->dev); | |
367 | hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; | |
368 | } | |
369 | ||
370 | /** | |
371 | * s3c24xx_spi_usefiq - return if we should be using FIQ. | |
372 | * @hw: The hardware state. | |
373 | * | |
374 | * Return true if the platform data specifies whether this channel is | |
375 | * allowed to use the FIQ. | |
376 | */ | |
377 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) | |
378 | { | |
379 | return hw->pdata->use_fiq; | |
380 | } | |
381 | ||
382 | /** | |
383 | * s3c24xx_spi_usingfiq - return if channel is using FIQ | |
384 | * @spi: The hardware state. | |
385 | * | |
386 | * Return whether the channel is currently using the FIQ (separate from | |
387 | * whether the FIQ is claimed). | |
388 | */ | |
389 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi) | |
390 | { | |
391 | return spi->fiq_inuse; | |
392 | } | |
393 | #else | |
394 | ||
395 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { } | |
396 | static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { } | |
397 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; } | |
398 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; } | |
399 | ||
400 | #endif /* CONFIG_SPI_S3C24XX_FIQ */ | |
401 | ||
7fba5340 BD |
402 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) |
403 | { | |
404 | struct s3c24xx_spi *hw = to_hw(spi); | |
405 | ||
7fba5340 BD |
406 | hw->tx = t->tx_buf; |
407 | hw->rx = t->rx_buf; | |
408 | hw->len = t->len; | |
409 | hw->count = 0; | |
410 | ||
4bb5eba0 BD |
411 | init_completion(&hw->done); |
412 | ||
bec0806c BD |
413 | hw->fiq_inuse = 0; |
414 | if (s3c24xx_spi_usefiq(hw) && t->len >= 3) | |
415 | s3c24xx_spi_tryfiq(hw); | |
416 | ||
7fba5340 BD |
417 | /* send the first byte */ |
418 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 419 | |
7fba5340 | 420 | wait_for_completion(&hw->done); |
7fba5340 BD |
421 | return hw->count; |
422 | } | |
423 | ||
7d12e780 | 424 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
425 | { |
426 | struct s3c24xx_spi *hw = dev; | |
427 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
428 | unsigned int count = hw->count; | |
429 | ||
430 | if (spsta & S3C2410_SPSTA_DCOL) { | |
431 | dev_dbg(hw->dev, "data-collision\n"); | |
432 | complete(&hw->done); | |
433 | goto irq_done; | |
434 | } | |
435 | ||
436 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
437 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
438 | complete(&hw->done); | |
439 | goto irq_done; | |
440 | } | |
441 | ||
bec0806c BD |
442 | if (!s3c24xx_spi_usingfiq(hw)) { |
443 | hw->count++; | |
7fba5340 | 444 | |
bec0806c BD |
445 | if (hw->rx) |
446 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 447 | |
bec0806c BD |
448 | count++; |
449 | ||
450 | if (count < hw->len) | |
451 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
452 | else | |
453 | complete(&hw->done); | |
454 | } else { | |
455 | hw->count = hw->len; | |
456 | hw->fiq_inuse = 0; | |
457 | ||
458 | if (hw->rx) | |
459 | hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); | |
7fba5340 | 460 | |
7fba5340 | 461 | complete(&hw->done); |
bec0806c | 462 | } |
7fba5340 BD |
463 | |
464 | irq_done: | |
465 | return IRQ_HANDLED; | |
466 | } | |
467 | ||
5aa6cf30 BD |
468 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
469 | { | |
470 | /* for the moment, permanently enable the clock */ | |
471 | ||
472 | clk_enable(hw->clk); | |
473 | ||
474 | /* program defaults into the registers */ | |
475 | ||
476 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
477 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
478 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 479 | |
ee9c1fbf BD |
480 | if (hw->pdata) { |
481 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
482 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
483 | ||
484 | if (hw->pdata->gpio_setup) | |
485 | hw->pdata->gpio_setup(hw->pdata, 1); | |
486 | } | |
5aa6cf30 BD |
487 | } |
488 | ||
fd4a319b | 489 | static int s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 490 | { |
50f426b5 | 491 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
492 | struct s3c24xx_spi *hw; |
493 | struct spi_master *master; | |
7fba5340 BD |
494 | struct resource *res; |
495 | int err = 0; | |
7fba5340 BD |
496 | |
497 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
498 | if (master == NULL) { | |
499 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
c9f722e8 | 500 | return -ENOMEM; |
7fba5340 BD |
501 | } |
502 | ||
503 | hw = spi_master_get_devdata(master); | |
504 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
505 | ||
94c69f76 | 506 | hw->master = master; |
8074cf06 | 507 | hw->pdata = pdata = dev_get_platdata(&pdev->dev); |
7fba5340 BD |
508 | hw->dev = &pdev->dev; |
509 | ||
50f426b5 | 510 | if (pdata == NULL) { |
7fba5340 BD |
511 | dev_err(&pdev->dev, "No platform data supplied\n"); |
512 | err = -ENOENT; | |
513 | goto err_no_pdata; | |
514 | } | |
515 | ||
516 | platform_set_drvdata(pdev, hw); | |
517 | init_completion(&hw->done); | |
518 | ||
bec0806c BD |
519 | /* initialise fiq handler */ |
520 | ||
521 | s3c24xx_spi_initfiq(hw); | |
522 | ||
d1e77806 BD |
523 | /* setup the master state. */ |
524 | ||
e7db06b5 DB |
525 | /* the spi->mode bits understood by this driver: */ |
526 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
527 | ||
d1e77806 | 528 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 529 | master->bus_num = pdata->bus_num; |
08850fa9 | 530 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
d1e77806 | 531 | |
7fba5340 BD |
532 | /* setup the state for the bitbang driver */ |
533 | ||
534 | hw->bitbang.master = hw->master; | |
535 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
536 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
537 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
570327d9 BD |
538 | |
539 | hw->master->setup = s3c24xx_spi_setup; | |
7fba5340 BD |
540 | |
541 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
542 | ||
543 | /* find and map our resources */ | |
7fba5340 | 544 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9f722e8 JH |
545 | hw->regs = devm_ioremap_resource(&pdev->dev, res); |
546 | if (IS_ERR(hw->regs)) { | |
547 | err = PTR_ERR(hw->regs); | |
548 | goto err_no_pdata; | |
7fba5340 BD |
549 | } |
550 | ||
551 | hw->irq = platform_get_irq(pdev, 0); | |
552 | if (hw->irq < 0) { | |
553 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
554 | err = -ENOENT; | |
c9f722e8 | 555 | goto err_no_pdata; |
7fba5340 BD |
556 | } |
557 | ||
c9f722e8 JH |
558 | err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, |
559 | pdev->name, hw); | |
7fba5340 BD |
560 | if (err) { |
561 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
c9f722e8 | 562 | goto err_no_pdata; |
7fba5340 BD |
563 | } |
564 | ||
c9f722e8 | 565 | hw->clk = devm_clk_get(&pdev->dev, "spi"); |
7fba5340 BD |
566 | if (IS_ERR(hw->clk)) { |
567 | dev_err(&pdev->dev, "No clock for device\n"); | |
568 | err = PTR_ERR(hw->clk); | |
c9f722e8 | 569 | goto err_no_pdata; |
7fba5340 BD |
570 | } |
571 | ||
7fba5340 BD |
572 | /* setup any gpio we can */ |
573 | ||
50f426b5 | 574 | if (!pdata->set_cs) { |
ee9c1fbf BD |
575 | if (pdata->pin_cs < 0) { |
576 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
b2af045c | 577 | err = -EINVAL; |
ee9c1fbf BD |
578 | goto err_register; |
579 | } | |
8736b927 | 580 | |
c9f722e8 JH |
581 | err = devm_gpio_request(&pdev->dev, pdata->pin_cs, |
582 | dev_name(&pdev->dev)); | |
ee9c1fbf BD |
583 | if (err) { |
584 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
585 | goto err_register; | |
586 | } | |
587 | ||
588 | hw->set_cs = s3c24xx_spi_gpiocs; | |
589 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 590 | } else |
50f426b5 | 591 | hw->set_cs = pdata->set_cs; |
7fba5340 | 592 | |
ee9c1fbf BD |
593 | s3c24xx_spi_initialsetup(hw); |
594 | ||
7fba5340 BD |
595 | /* register our spi controller */ |
596 | ||
597 | err = spi_bitbang_start(&hw->bitbang); | |
598 | if (err) { | |
599 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
600 | goto err_register; | |
601 | } | |
602 | ||
7fba5340 BD |
603 | return 0; |
604 | ||
605 | err_register: | |
606 | clk_disable(hw->clk); | |
7fba5340 | 607 | |
7fba5340 | 608 | err_no_pdata: |
a419aef8 | 609 | spi_master_put(hw->master); |
7fba5340 BD |
610 | return err; |
611 | } | |
612 | ||
fd4a319b | 613 | static int s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
614 | { |
615 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
616 | ||
c6e7b8cb | 617 | spi_bitbang_stop(&hw->bitbang); |
7fba5340 | 618 | clk_disable(hw->clk); |
7fba5340 BD |
619 | spi_master_put(hw->master); |
620 | return 0; | |
621 | } | |
622 | ||
623 | ||
624 | #ifdef CONFIG_PM | |
625 | ||
6d613207 | 626 | static int s3c24xx_spi_suspend(struct device *dev) |
7fba5340 | 627 | { |
a1216394 | 628 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
38060371 AL |
629 | int ret; |
630 | ||
631 | ret = spi_master_suspend(hw->master); | |
632 | if (ret) | |
633 | return ret; | |
7fba5340 | 634 | |
cf46b973 BD |
635 | if (hw->pdata && hw->pdata->gpio_setup) |
636 | hw->pdata->gpio_setup(hw->pdata, 0); | |
637 | ||
7fba5340 BD |
638 | clk_disable(hw->clk); |
639 | return 0; | |
640 | } | |
641 | ||
6d613207 | 642 | static int s3c24xx_spi_resume(struct device *dev) |
7fba5340 | 643 | { |
a1216394 | 644 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
7fba5340 | 645 | |
5aa6cf30 | 646 | s3c24xx_spi_initialsetup(hw); |
38060371 | 647 | return spi_master_resume(hw->master); |
7fba5340 BD |
648 | } |
649 | ||
47145210 | 650 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
6d613207 BD |
651 | .suspend = s3c24xx_spi_suspend, |
652 | .resume = s3c24xx_spi_resume, | |
653 | }; | |
654 | ||
655 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops | |
7fba5340 | 656 | #else |
6d613207 BD |
657 | #define S3C24XX_SPI_PMOPS NULL |
658 | #endif /* CONFIG_PM */ | |
7fba5340 | 659 | |
7e38c3c4 | 660 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 661 | static struct platform_driver s3c24xx_spi_driver = { |
940ab889 | 662 | .probe = s3c24xx_spi_probe, |
fd4a319b | 663 | .remove = s3c24xx_spi_remove, |
7fba5340 BD |
664 | .driver = { |
665 | .name = "s3c2410-spi", | |
666 | .owner = THIS_MODULE, | |
6d613207 | 667 | .pm = S3C24XX_SPI_PMOPS, |
7fba5340 BD |
668 | }, |
669 | }; | |
940ab889 | 670 | module_platform_driver(s3c24xx_spi_driver); |
7fba5340 BD |
671 | |
672 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
673 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
674 | MODULE_LICENSE("GPL"); |