Commit | Line | Data |
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ca632f55 | 1 | /* |
230d42d4 JB |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/workqueue.h> | |
c2573128 | 23 | #include <linux/interrupt.h> |
230d42d4 JB |
24 | #include <linux/delay.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/dma-mapping.h> | |
78843727 | 27 | #include <linux/dmaengine.h> |
230d42d4 | 28 | #include <linux/platform_device.h> |
b97b6621 | 29 | #include <linux/pm_runtime.h> |
230d42d4 | 30 | #include <linux/spi/spi.h> |
1c20c200 | 31 | #include <linux/gpio.h> |
2b908075 TA |
32 | #include <linux/of.h> |
33 | #include <linux/of_gpio.h> | |
230d42d4 | 34 | |
436d42c6 | 35 | #include <linux/platform_data/spi-s3c64xx.h> |
230d42d4 | 36 | |
a5238e36 | 37 | #define MAX_SPI_PORTS 3 |
7e995556 | 38 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
a5238e36 | 39 | |
230d42d4 JB |
40 | /* Registers and bit-fields */ |
41 | ||
42 | #define S3C64XX_SPI_CH_CFG 0x00 | |
43 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
44 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
45 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
46 | #define S3C64XX_SPI_INT_EN 0x10 | |
47 | #define S3C64XX_SPI_STATUS 0x14 | |
48 | #define S3C64XX_SPI_TX_DATA 0x18 | |
49 | #define S3C64XX_SPI_RX_DATA 0x1C | |
50 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
51 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
52 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
53 | #define S3C64XX_SPI_FB_CLK 0x2C | |
54 | ||
55 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
56 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
57 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
58 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
59 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
60 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
61 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
62 | ||
63 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
64 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
65 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
75bf3361 | 66 | #define S3C64XX_SPI_PSR_MASK 0xff |
230d42d4 JB |
67 | |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
69 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
70 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
71 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
72 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
73 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
74 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
75 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
76 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
77 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
78 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
79 | ||
80 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
81 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
82 | ||
230d42d4 JB |
83 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
84 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
85 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
86 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
87 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
88 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
89 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
90 | ||
91 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
92 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
93 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
94 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
95 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
96 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
97 | ||
98 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
99 | ||
100 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
101 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
102 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
103 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
104 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
105 | ||
106 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
107 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
108 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
109 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
110 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
111 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
112 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
113 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
114 | ||
115 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
116 | ||
a5238e36 TA |
117 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
118 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | |
119 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | |
120 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | |
121 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | |
122 | FIFO_LVL_MASK(i)) | |
230d42d4 JB |
123 | |
124 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
125 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
126 | ||
127 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
128 | ||
129 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
7e995556 | 130 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
230d42d4 | 131 | |
230d42d4 JB |
132 | #define RXBUSY (1<<2) |
133 | #define TXBUSY (1<<3) | |
134 | ||
82ab8cd7 | 135 | struct s3c64xx_spi_dma_data { |
78843727 | 136 | struct dma_chan *ch; |
c10356b9 | 137 | enum dma_transfer_direction direction; |
78843727 | 138 | unsigned int dmach; |
82ab8cd7 BK |
139 | }; |
140 | ||
a5238e36 TA |
141 | /** |
142 | * struct s3c64xx_spi_info - SPI Controller hardware info | |
143 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | |
144 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | |
145 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | |
146 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | |
147 | * @clk_from_cmu: True, if the controller does not include a clock mux and | |
148 | * prescaler unit. | |
149 | * | |
150 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | |
151 | * differ in some aspects such as the size of the fifo and spi bus clock | |
152 | * setup. Such differences are specified to the driver using this structure | |
153 | * which is provided as driver data to the driver. | |
154 | */ | |
155 | struct s3c64xx_spi_port_config { | |
156 | int fifo_lvl_mask[MAX_SPI_PORTS]; | |
157 | int rx_lvl_offset; | |
158 | int tx_st_done; | |
7e995556 | 159 | int quirks; |
a5238e36 TA |
160 | bool high_speed; |
161 | bool clk_from_cmu; | |
162 | }; | |
163 | ||
230d42d4 JB |
164 | /** |
165 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
166 | * @clk: Pointer to the spi clock. | |
b0d5d6e5 | 167 | * @src_clk: Pointer to the clock used to generate SPI signals. |
230d42d4 | 168 | * @master: Pointer to the SPI Protocol master. |
230d42d4 JB |
169 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
170 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
230d42d4 JB |
171 | * @lock: Controller specific lock. |
172 | * @state: Set of FLAGS to indicate status. | |
173 | * @rx_dmach: Controller's DMA channel for Rx. | |
174 | * @tx_dmach: Controller's DMA channel for Tx. | |
175 | * @sfr_start: BUS address of SPI controller regs. | |
176 | * @regs: Pointer to ioremap'ed controller registers. | |
c2573128 | 177 | * @irq: interrupt |
230d42d4 JB |
178 | * @xfer_completion: To indicate completion of xfer task. |
179 | * @cur_mode: Stores the active configuration of the controller. | |
180 | * @cur_bpw: Stores the active bits per word settings. | |
181 | * @cur_speed: Stores the active xfer clock speed. | |
182 | */ | |
183 | struct s3c64xx_spi_driver_data { | |
184 | void __iomem *regs; | |
185 | struct clk *clk; | |
b0d5d6e5 | 186 | struct clk *src_clk; |
230d42d4 JB |
187 | struct platform_device *pdev; |
188 | struct spi_master *master; | |
ad7de729 | 189 | struct s3c64xx_spi_info *cntrlr_info; |
230d42d4 | 190 | struct spi_device *tgl_spi; |
230d42d4 | 191 | spinlock_t lock; |
230d42d4 JB |
192 | unsigned long sfr_start; |
193 | struct completion xfer_completion; | |
194 | unsigned state; | |
195 | unsigned cur_mode, cur_bpw; | |
196 | unsigned cur_speed; | |
82ab8cd7 BK |
197 | struct s3c64xx_spi_dma_data rx_dma; |
198 | struct s3c64xx_spi_dma_data tx_dma; | |
a5238e36 TA |
199 | struct s3c64xx_spi_port_config *port_conf; |
200 | unsigned int port_id; | |
3146beec | 201 | bool cs_gpio; |
230d42d4 JB |
202 | }; |
203 | ||
230d42d4 JB |
204 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
205 | { | |
230d42d4 JB |
206 | void __iomem *regs = sdd->regs; |
207 | unsigned long loops; | |
208 | u32 val; | |
209 | ||
210 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
211 | ||
7d859ff4 KK |
212 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
213 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
214 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
215 | ||
230d42d4 JB |
216 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
217 | val |= S3C64XX_SPI_CH_SW_RST; | |
218 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
219 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
220 | ||
221 | /* Flush TxFIFO*/ | |
222 | loops = msecs_to_loops(1); | |
223 | do { | |
224 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 225 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
230d42d4 | 226 | |
be7852a8 MB |
227 | if (loops == 0) |
228 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
229 | ||
230d42d4 JB |
230 | /* Flush RxFIFO*/ |
231 | loops = msecs_to_loops(1); | |
232 | do { | |
233 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 234 | if (RX_FIFO_LVL(val, sdd)) |
230d42d4 JB |
235 | readl(regs + S3C64XX_SPI_RX_DATA); |
236 | else | |
237 | break; | |
238 | } while (loops--); | |
239 | ||
be7852a8 MB |
240 | if (loops == 0) |
241 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
242 | ||
230d42d4 JB |
243 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
244 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
245 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
246 | ||
247 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
248 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
249 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
230d42d4 JB |
250 | } |
251 | ||
82ab8cd7 | 252 | static void s3c64xx_spi_dmacb(void *data) |
39d3e807 | 253 | { |
82ab8cd7 BK |
254 | struct s3c64xx_spi_driver_data *sdd; |
255 | struct s3c64xx_spi_dma_data *dma = data; | |
39d3e807 BK |
256 | unsigned long flags; |
257 | ||
054ebcc4 | 258 | if (dma->direction == DMA_DEV_TO_MEM) |
82ab8cd7 BK |
259 | sdd = container_of(data, |
260 | struct s3c64xx_spi_driver_data, rx_dma); | |
261 | else | |
262 | sdd = container_of(data, | |
263 | struct s3c64xx_spi_driver_data, tx_dma); | |
264 | ||
39d3e807 BK |
265 | spin_lock_irqsave(&sdd->lock, flags); |
266 | ||
054ebcc4 | 267 | if (dma->direction == DMA_DEV_TO_MEM) { |
82ab8cd7 BK |
268 | sdd->state &= ~RXBUSY; |
269 | if (!(sdd->state & TXBUSY)) | |
270 | complete(&sdd->xfer_completion); | |
271 | } else { | |
272 | sdd->state &= ~TXBUSY; | |
273 | if (!(sdd->state & RXBUSY)) | |
274 | complete(&sdd->xfer_completion); | |
275 | } | |
39d3e807 BK |
276 | |
277 | spin_unlock_irqrestore(&sdd->lock, flags); | |
278 | } | |
279 | ||
78843727 | 280 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
6ad45a27 | 281 | struct sg_table *sgt) |
78843727 AB |
282 | { |
283 | struct s3c64xx_spi_driver_data *sdd; | |
284 | struct dma_slave_config config; | |
78843727 AB |
285 | struct dma_async_tx_descriptor *desc; |
286 | ||
b1a8e78d TF |
287 | memset(&config, 0, sizeof(config)); |
288 | ||
78843727 AB |
289 | if (dma->direction == DMA_DEV_TO_MEM) { |
290 | sdd = container_of((void *)dma, | |
291 | struct s3c64xx_spi_driver_data, rx_dma); | |
292 | config.direction = dma->direction; | |
293 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
294 | config.src_addr_width = sdd->cur_bpw / 8; | |
295 | config.src_maxburst = 1; | |
296 | dmaengine_slave_config(dma->ch, &config); | |
297 | } else { | |
298 | sdd = container_of((void *)dma, | |
299 | struct s3c64xx_spi_driver_data, tx_dma); | |
300 | config.direction = dma->direction; | |
301 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
302 | config.dst_addr_width = sdd->cur_bpw / 8; | |
303 | config.dst_maxburst = 1; | |
304 | dmaengine_slave_config(dma->ch, &config); | |
305 | } | |
306 | ||
6ad45a27 MB |
307 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, |
308 | dma->direction, DMA_PREP_INTERRUPT); | |
78843727 AB |
309 | |
310 | desc->callback = s3c64xx_spi_dmacb; | |
311 | desc->callback_param = dma; | |
312 | ||
313 | dmaengine_submit(desc); | |
314 | dma_async_issue_pending(dma->ch); | |
315 | } | |
316 | ||
317 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) | |
318 | { | |
319 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
320 | dma_filter_fn filter = sdd->cntrlr_info->filter; | |
321 | struct device *dev = &sdd->pdev->dev; | |
322 | dma_cap_mask_t mask; | |
fb9d044e | 323 | int ret; |
78843727 | 324 | |
c12f9643 MB |
325 | if (!is_polling(sdd)) { |
326 | dma_cap_zero(mask); | |
327 | dma_cap_set(DMA_SLAVE, mask); | |
328 | ||
329 | /* Acquire DMA channels */ | |
330 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, | |
331 | (void *)sdd->rx_dma.dmach, dev, "rx"); | |
332 | if (!sdd->rx_dma.ch) { | |
333 | dev_err(dev, "Failed to get RX DMA channel\n"); | |
334 | ret = -EBUSY; | |
335 | goto out; | |
336 | } | |
3f295887 | 337 | spi->dma_rx = sdd->rx_dma.ch; |
fb9d044e | 338 | |
c12f9643 MB |
339 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
340 | (void *)sdd->tx_dma.dmach, dev, "tx"); | |
341 | if (!sdd->tx_dma.ch) { | |
342 | dev_err(dev, "Failed to get TX DMA channel\n"); | |
343 | ret = -EBUSY; | |
344 | goto out_rx; | |
345 | } | |
3f295887 | 346 | spi->dma_tx = sdd->tx_dma.ch; |
fb9d044e MB |
347 | } |
348 | ||
349 | ret = pm_runtime_get_sync(&sdd->pdev->dev); | |
6c6cf64b | 350 | if (ret < 0) { |
fb9d044e MB |
351 | dev_err(dev, "Failed to enable device: %d\n", ret); |
352 | goto out_tx; | |
353 | } | |
78843727 AB |
354 | |
355 | return 0; | |
fb9d044e MB |
356 | |
357 | out_tx: | |
358 | dma_release_channel(sdd->tx_dma.ch); | |
359 | out_rx: | |
360 | dma_release_channel(sdd->rx_dma.ch); | |
361 | out: | |
362 | return ret; | |
78843727 AB |
363 | } |
364 | ||
365 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | |
366 | { | |
367 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
368 | ||
369 | /* Free DMA channels */ | |
7e995556 G |
370 | if (!is_polling(sdd)) { |
371 | dma_release_channel(sdd->rx_dma.ch); | |
372 | dma_release_channel(sdd->tx_dma.ch); | |
373 | } | |
78843727 AB |
374 | |
375 | pm_runtime_put(&sdd->pdev->dev); | |
376 | return 0; | |
377 | } | |
378 | ||
3f295887 MB |
379 | static bool s3c64xx_spi_can_dma(struct spi_master *master, |
380 | struct spi_device *spi, | |
381 | struct spi_transfer *xfer) | |
382 | { | |
383 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
384 | ||
385 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
386 | } | |
387 | ||
230d42d4 JB |
388 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
389 | struct spi_device *spi, | |
390 | struct spi_transfer *xfer, int dma_mode) | |
391 | { | |
230d42d4 JB |
392 | void __iomem *regs = sdd->regs; |
393 | u32 modecfg, chcfg; | |
394 | ||
395 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
396 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
397 | ||
398 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
399 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
400 | ||
401 | if (dma_mode) { | |
402 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
403 | } else { | |
404 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
405 | * this helps setting PCKT_CNT value for generating clocks | |
406 | * as exactly needed. | |
407 | */ | |
408 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
409 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
410 | | S3C64XX_SPI_PACKET_CNT_EN, | |
411 | regs + S3C64XX_SPI_PACKET_CNT); | |
412 | } | |
413 | ||
414 | if (xfer->tx_buf != NULL) { | |
415 | sdd->state |= TXBUSY; | |
416 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
417 | if (dma_mode) { | |
418 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
6ad45a27 | 419 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); |
230d42d4 | 420 | } else { |
0c92ecf1 JB |
421 | switch (sdd->cur_bpw) { |
422 | case 32: | |
423 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
424 | xfer->tx_buf, xfer->len / 4); | |
425 | break; | |
426 | case 16: | |
427 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
428 | xfer->tx_buf, xfer->len / 2); | |
429 | break; | |
430 | default: | |
431 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
432 | xfer->tx_buf, xfer->len); | |
433 | break; | |
434 | } | |
230d42d4 JB |
435 | } |
436 | } | |
437 | ||
438 | if (xfer->rx_buf != NULL) { | |
439 | sdd->state |= RXBUSY; | |
440 | ||
a5238e36 | 441 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
230d42d4 JB |
442 | && !(sdd->cur_mode & SPI_CPHA)) |
443 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
444 | ||
445 | if (dma_mode) { | |
446 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
447 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
448 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
449 | | S3C64XX_SPI_PACKET_CNT_EN, | |
450 | regs + S3C64XX_SPI_PACKET_CNT); | |
6ad45a27 | 451 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); |
230d42d4 JB |
452 | } |
453 | } | |
454 | ||
455 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
456 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
457 | } | |
458 | ||
79617073 | 459 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
7e995556 G |
460 | int timeout_ms) |
461 | { | |
462 | void __iomem *regs = sdd->regs; | |
463 | unsigned long val = 1; | |
464 | u32 status; | |
465 | ||
466 | /* max fifo depth available */ | |
467 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
468 | ||
469 | if (timeout_ms) | |
470 | val = msecs_to_loops(timeout_ms); | |
471 | ||
472 | do { | |
473 | status = readl(regs + S3C64XX_SPI_STATUS); | |
474 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); | |
475 | ||
476 | /* return the actual received data length */ | |
477 | return RX_FIFO_LVL(status, sdd); | |
230d42d4 JB |
478 | } |
479 | ||
3700c6eb MB |
480 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
481 | struct spi_transfer *xfer) | |
230d42d4 | 482 | { |
230d42d4 JB |
483 | void __iomem *regs = sdd->regs; |
484 | unsigned long val; | |
3700c6eb | 485 | u32 status; |
230d42d4 JB |
486 | int ms; |
487 | ||
488 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
489 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
9d8f86b5 | 490 | ms += 10; /* some tolerance */ |
230d42d4 | 491 | |
3700c6eb MB |
492 | val = msecs_to_jiffies(ms) + 10; |
493 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
494 | ||
495 | /* | |
496 | * If the previous xfer was completed within timeout, then | |
497 | * proceed further else return -EIO. | |
498 | * DmaTx returns after simply writing data in the FIFO, | |
499 | * w/o waiting for real transmission on the bus to finish. | |
500 | * DmaRx returns only after Dma read data from FIFO which | |
501 | * needs bus transmission to finish, so we don't worry if | |
502 | * Xfer involved Rx(with or without Tx). | |
503 | */ | |
504 | if (val && !xfer->rx_buf) { | |
505 | val = msecs_to_loops(10); | |
506 | status = readl(regs + S3C64XX_SPI_STATUS); | |
507 | while ((TX_FIFO_LVL(status, sdd) | |
508 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | |
509 | && --val) { | |
510 | cpu_relax(); | |
c3f139b6 | 511 | status = readl(regs + S3C64XX_SPI_STATUS); |
3700c6eb MB |
512 | } |
513 | ||
230d42d4 JB |
514 | } |
515 | ||
3700c6eb MB |
516 | /* If timed out while checking rx/tx status return error */ |
517 | if (!val) | |
518 | return -EIO; | |
230d42d4 | 519 | |
3700c6eb MB |
520 | return 0; |
521 | } | |
7e995556 | 522 | |
3700c6eb MB |
523 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
524 | struct spi_transfer *xfer) | |
525 | { | |
526 | void __iomem *regs = sdd->regs; | |
527 | unsigned long val; | |
528 | u32 status; | |
529 | int loops; | |
530 | u32 cpy_len; | |
531 | u8 *buf; | |
532 | int ms; | |
230d42d4 | 533 | |
3700c6eb MB |
534 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
535 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
536 | ms += 10; /* some tolerance */ | |
7e995556 | 537 | |
3700c6eb MB |
538 | val = msecs_to_loops(ms); |
539 | do { | |
540 | status = readl(regs + S3C64XX_SPI_STATUS); | |
541 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | |
7e995556 | 542 | |
3700c6eb MB |
543 | |
544 | /* If it was only Tx */ | |
545 | if (!xfer->rx_buf) { | |
546 | sdd->state &= ~TXBUSY; | |
547 | return 0; | |
230d42d4 JB |
548 | } |
549 | ||
3700c6eb MB |
550 | /* |
551 | * If the receive length is bigger than the controller fifo | |
552 | * size, calculate the loops and read the fifo as many times. | |
553 | * loops = length / max fifo size (calculated by using the | |
554 | * fifo mask). | |
555 | * For any size less than the fifo size the below code is | |
556 | * executed atleast once. | |
557 | */ | |
558 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); | |
559 | buf = xfer->rx_buf; | |
560 | do { | |
561 | /* wait for data to be received in the fifo */ | |
562 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, | |
563 | (loops ? ms : 0)); | |
564 | ||
565 | switch (sdd->cur_bpw) { | |
566 | case 32: | |
567 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
568 | buf, cpy_len / 4); | |
569 | break; | |
570 | case 16: | |
571 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
572 | buf, cpy_len / 2); | |
573 | break; | |
574 | default: | |
575 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
576 | buf, cpy_len); | |
577 | break; | |
578 | } | |
579 | ||
580 | buf = buf + cpy_len; | |
581 | } while (loops--); | |
582 | sdd->state &= ~RXBUSY; | |
583 | ||
230d42d4 JB |
584 | return 0; |
585 | } | |
586 | ||
230d42d4 JB |
587 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
588 | { | |
230d42d4 JB |
589 | void __iomem *regs = sdd->regs; |
590 | u32 val; | |
591 | ||
592 | /* Disable Clock */ | |
a5238e36 | 593 | if (sdd->port_conf->clk_from_cmu) { |
9f667bff | 594 | clk_disable_unprepare(sdd->src_clk); |
b42a81ca JB |
595 | } else { |
596 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
597 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
598 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
599 | } | |
230d42d4 JB |
600 | |
601 | /* Set Polarity and Phase */ | |
602 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
603 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
604 | S3C64XX_SPI_CPOL_L | | |
605 | S3C64XX_SPI_CPHA_B); | |
606 | ||
607 | if (sdd->cur_mode & SPI_CPOL) | |
608 | val |= S3C64XX_SPI_CPOL_L; | |
609 | ||
610 | if (sdd->cur_mode & SPI_CPHA) | |
611 | val |= S3C64XX_SPI_CPHA_B; | |
612 | ||
613 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
614 | ||
615 | /* Set Channel & DMA Mode */ | |
616 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
617 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
618 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
619 | ||
620 | switch (sdd->cur_bpw) { | |
621 | case 32: | |
622 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
0c92ecf1 | 623 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
230d42d4 JB |
624 | break; |
625 | case 16: | |
626 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
0c92ecf1 | 627 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
230d42d4 JB |
628 | break; |
629 | default: | |
630 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
0c92ecf1 | 631 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
230d42d4 JB |
632 | break; |
633 | } | |
230d42d4 JB |
634 | |
635 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
636 | ||
a5238e36 | 637 | if (sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
638 | /* Configure Clock */ |
639 | /* There is half-multiplier before the SPI */ | |
640 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); | |
641 | /* Enable Clock */ | |
9f667bff | 642 | clk_prepare_enable(sdd->src_clk); |
b42a81ca JB |
643 | } else { |
644 | /* Configure Clock */ | |
645 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
646 | val &= ~S3C64XX_SPI_PSR_MASK; | |
647 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
648 | & S3C64XX_SPI_PSR_MASK); | |
649 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
650 | ||
651 | /* Enable Clock */ | |
652 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
653 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
654 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
655 | } | |
230d42d4 JB |
656 | } |
657 | ||
230d42d4 JB |
658 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
659 | ||
6bb9c0e3 MB |
660 | static int s3c64xx_spi_prepare_message(struct spi_master *master, |
661 | struct spi_message *msg) | |
230d42d4 | 662 | { |
ad2a99af | 663 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 JB |
664 | struct spi_device *spi = msg->spi; |
665 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
230d42d4 JB |
666 | |
667 | /* If Master's(controller) state differs from that needed by Slave */ | |
668 | if (sdd->cur_speed != spi->max_speed_hz | |
669 | || sdd->cur_mode != spi->mode | |
670 | || sdd->cur_bpw != spi->bits_per_word) { | |
671 | sdd->cur_bpw = spi->bits_per_word; | |
672 | sdd->cur_speed = spi->max_speed_hz; | |
673 | sdd->cur_mode = spi->mode; | |
674 | s3c64xx_spi_config(sdd); | |
675 | } | |
676 | ||
230d42d4 JB |
677 | /* Configure feedback delay */ |
678 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
679 | ||
6bb9c0e3 MB |
680 | return 0; |
681 | } | |
0c92ecf1 | 682 | |
0732a9d2 MB |
683 | static int s3c64xx_spi_transfer_one(struct spi_master *master, |
684 | struct spi_device *spi, | |
685 | struct spi_transfer *xfer) | |
6bb9c0e3 MB |
686 | { |
687 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
0732a9d2 | 688 | int status; |
6bb9c0e3 MB |
689 | u32 speed; |
690 | u8 bpw; | |
0732a9d2 MB |
691 | unsigned long flags; |
692 | int use_dma; | |
230d42d4 | 693 | |
3e83c194 | 694 | reinit_completion(&sdd->xfer_completion); |
230d42d4 | 695 | |
0732a9d2 MB |
696 | /* Only BPW and Speed may change across transfers */ |
697 | bpw = xfer->bits_per_word; | |
698 | speed = xfer->speed_hz ? : spi->max_speed_hz; | |
230d42d4 | 699 | |
0732a9d2 MB |
700 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
701 | sdd->cur_bpw = bpw; | |
702 | sdd->cur_speed = speed; | |
703 | s3c64xx_spi_config(sdd); | |
704 | } | |
230d42d4 | 705 | |
0732a9d2 MB |
706 | /* Polling method for xfers not bigger than FIFO capacity */ |
707 | use_dma = 0; | |
708 | if (!is_polling(sdd) && | |
709 | (sdd->rx_dma.ch && sdd->tx_dma.ch && | |
710 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) | |
711 | use_dma = 1; | |
230d42d4 | 712 | |
0732a9d2 | 713 | spin_lock_irqsave(&sdd->lock, flags); |
230d42d4 | 714 | |
0732a9d2 MB |
715 | /* Pending only which is to be done */ |
716 | sdd->state &= ~RXBUSY; | |
717 | sdd->state &= ~TXBUSY; | |
230d42d4 | 718 | |
0732a9d2 | 719 | enable_datapath(sdd, spi, xfer, use_dma); |
230d42d4 | 720 | |
0732a9d2 MB |
721 | /* Start the signals */ |
722 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
230d42d4 | 723 | |
0732a9d2 | 724 | spin_unlock_irqrestore(&sdd->lock, flags); |
230d42d4 | 725 | |
3700c6eb MB |
726 | if (use_dma) |
727 | status = wait_for_dma(sdd, xfer); | |
728 | else | |
729 | status = wait_for_pio(sdd, xfer); | |
0732a9d2 MB |
730 | |
731 | if (status) { | |
732 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
733 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | |
734 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
735 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
736 | xfer->len); | |
737 | ||
738 | if (use_dma) { | |
739 | if (xfer->tx_buf != NULL | |
740 | && (sdd->state & TXBUSY)) | |
1b5e1b69 | 741 | dmaengine_terminate_all(sdd->tx_dma.ch); |
0732a9d2 MB |
742 | if (xfer->rx_buf != NULL |
743 | && (sdd->state & RXBUSY)) | |
1b5e1b69 | 744 | dmaengine_terminate_all(sdd->rx_dma.ch); |
230d42d4 | 745 | } |
8c09daa1 | 746 | } else { |
230d42d4 JB |
747 | flush_fifo(sdd); |
748 | } | |
749 | ||
0732a9d2 | 750 | return status; |
230d42d4 | 751 | } |
230d42d4 | 752 | |
2b908075 | 753 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
2b908075 TA |
754 | struct spi_device *spi) |
755 | { | |
756 | struct s3c64xx_spi_csinfo *cs; | |
4732cc63 | 757 | struct device_node *slave_np, *data_np = NULL; |
3146beec | 758 | struct s3c64xx_spi_driver_data *sdd; |
2b908075 TA |
759 | u32 fb_delay = 0; |
760 | ||
3146beec | 761 | sdd = spi_master_get_devdata(spi->master); |
2b908075 TA |
762 | slave_np = spi->dev.of_node; |
763 | if (!slave_np) { | |
764 | dev_err(&spi->dev, "device node not found\n"); | |
765 | return ERR_PTR(-EINVAL); | |
766 | } | |
767 | ||
06455bbc | 768 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
2b908075 TA |
769 | if (!data_np) { |
770 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | |
771 | return ERR_PTR(-EINVAL); | |
772 | } | |
773 | ||
774 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | |
775 | if (!cs) { | |
75bf3361 | 776 | dev_err(&spi->dev, "could not allocate memory for controller data\n"); |
06455bbc | 777 | of_node_put(data_np); |
2b908075 TA |
778 | return ERR_PTR(-ENOMEM); |
779 | } | |
780 | ||
3146beec G |
781 | /* The CS line is asserted/deasserted by the gpio pin */ |
782 | if (sdd->cs_gpio) | |
783 | cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); | |
784 | ||
2b908075 | 785 | if (!gpio_is_valid(cs->line)) { |
75bf3361 | 786 | dev_err(&spi->dev, "chip select gpio is not specified or invalid\n"); |
2b908075 | 787 | kfree(cs); |
06455bbc | 788 | of_node_put(data_np); |
2b908075 TA |
789 | return ERR_PTR(-EINVAL); |
790 | } | |
791 | ||
792 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); | |
793 | cs->fb_delay = fb_delay; | |
06455bbc | 794 | of_node_put(data_np); |
2b908075 TA |
795 | return cs; |
796 | } | |
797 | ||
230d42d4 JB |
798 | /* |
799 | * Here we only check the validity of requested configuration | |
800 | * and save the configuration in a local data-structure. | |
801 | * The controller is actually configured only just before we | |
802 | * get a message to transfer. | |
803 | */ | |
804 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
805 | { | |
806 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
807 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 808 | struct s3c64xx_spi_info *sci; |
2b908075 | 809 | int err; |
230d42d4 | 810 | |
2b908075 TA |
811 | sdd = spi_master_get_devdata(spi->master); |
812 | if (!cs && spi->dev.of_node) { | |
5c725b34 | 813 | cs = s3c64xx_get_slave_ctrldata(spi); |
2b908075 TA |
814 | spi->controller_data = cs; |
815 | } | |
816 | ||
817 | if (IS_ERR_OR_NULL(cs)) { | |
230d42d4 JB |
818 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
819 | return -ENODEV; | |
820 | } | |
821 | ||
0149871c TF |
822 | if (!spi_get_ctldata(spi)) { |
823 | /* Request gpio only if cs line is asserted by gpio pins */ | |
824 | if (sdd->cs_gpio) { | |
825 | err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH, | |
826 | dev_name(&spi->dev)); | |
827 | if (err) { | |
828 | dev_err(&spi->dev, | |
829 | "Failed to get /CS gpio [%d]: %d\n", | |
830 | cs->line, err); | |
831 | goto err_gpio_req; | |
832 | } | |
dd97e268 MB |
833 | |
834 | spi->cs_gpio = cs->line; | |
1c20c200 | 835 | } |
1c20c200 | 836 | |
3146beec | 837 | spi_set_ctldata(spi, cs); |
230d42d4 JB |
838 | } |
839 | ||
230d42d4 | 840 | sci = sdd->cntrlr_info; |
230d42d4 | 841 | |
b97b6621 MB |
842 | pm_runtime_get_sync(&sdd->pdev->dev); |
843 | ||
230d42d4 | 844 | /* Check if we can provide the requested rate */ |
a5238e36 | 845 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
846 | u32 psr, speed; |
847 | ||
848 | /* Max possible */ | |
849 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
850 | ||
851 | if (spi->max_speed_hz > speed) | |
852 | spi->max_speed_hz = speed; | |
853 | ||
854 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
855 | psr &= S3C64XX_SPI_PSR_MASK; | |
856 | if (psr == S3C64XX_SPI_PSR_MASK) | |
857 | psr--; | |
858 | ||
859 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
860 | if (spi->max_speed_hz < speed) { | |
861 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
862 | psr++; | |
863 | } else { | |
864 | err = -EINVAL; | |
865 | goto setup_exit; | |
866 | } | |
867 | } | |
230d42d4 | 868 | |
b42a81ca | 869 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
2b908075 | 870 | if (spi->max_speed_hz >= speed) { |
b42a81ca | 871 | spi->max_speed_hz = speed; |
2b908075 | 872 | } else { |
e1b0f0df MB |
873 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
874 | spi->max_speed_hz); | |
230d42d4 | 875 | err = -EINVAL; |
2b908075 TA |
876 | goto setup_exit; |
877 | } | |
230d42d4 JB |
878 | } |
879 | ||
b97b6621 | 880 | pm_runtime_put(&sdd->pdev->dev); |
8c09daa1 | 881 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
2b908075 | 882 | return 0; |
b97b6621 | 883 | |
230d42d4 | 884 | setup_exit: |
7b8f7eef | 885 | pm_runtime_put(&sdd->pdev->dev); |
230d42d4 | 886 | /* setup() returns with device de-selected */ |
8c09daa1 | 887 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
230d42d4 | 888 | |
2b908075 TA |
889 | gpio_free(cs->line); |
890 | spi_set_ctldata(spi, NULL); | |
891 | ||
892 | err_gpio_req: | |
5bee3b94 SN |
893 | if (spi->dev.of_node) |
894 | kfree(cs); | |
2b908075 | 895 | |
230d42d4 JB |
896 | return err; |
897 | } | |
898 | ||
1c20c200 TA |
899 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
900 | { | |
901 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | |
3146beec | 902 | struct s3c64xx_spi_driver_data *sdd; |
1c20c200 | 903 | |
3146beec | 904 | sdd = spi_master_get_devdata(spi->master); |
dd97e268 MB |
905 | if (spi->cs_gpio) { |
906 | gpio_free(spi->cs_gpio); | |
2b908075 TA |
907 | if (spi->dev.of_node) |
908 | kfree(cs); | |
909 | } | |
1c20c200 TA |
910 | spi_set_ctldata(spi, NULL); |
911 | } | |
912 | ||
c2573128 MB |
913 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
914 | { | |
915 | struct s3c64xx_spi_driver_data *sdd = data; | |
916 | struct spi_master *spi = sdd->master; | |
375981f2 | 917 | unsigned int val, clr = 0; |
c2573128 | 918 | |
375981f2 | 919 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
c2573128 | 920 | |
375981f2 G |
921 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
922 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; | |
c2573128 | 923 | dev_err(&spi->dev, "RX overrun\n"); |
375981f2 G |
924 | } |
925 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { | |
926 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; | |
c2573128 | 927 | dev_err(&spi->dev, "RX underrun\n"); |
375981f2 G |
928 | } |
929 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { | |
930 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; | |
c2573128 | 931 | dev_err(&spi->dev, "TX overrun\n"); |
375981f2 G |
932 | } |
933 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { | |
934 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
c2573128 | 935 | dev_err(&spi->dev, "TX underrun\n"); |
375981f2 G |
936 | } |
937 | ||
938 | /* Clear the pending irq by setting and then clearing it */ | |
939 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
940 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
c2573128 MB |
941 | |
942 | return IRQ_HANDLED; | |
943 | } | |
944 | ||
230d42d4 JB |
945 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
946 | { | |
ad7de729 | 947 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
948 | void __iomem *regs = sdd->regs; |
949 | unsigned int val; | |
950 | ||
951 | sdd->cur_speed = 0; | |
952 | ||
5fc3e831 | 953 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
230d42d4 JB |
954 | |
955 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
956 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
957 | ||
a5238e36 | 958 | if (!sdd->port_conf->clk_from_cmu) |
b42a81ca | 959 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
230d42d4 JB |
960 | regs + S3C64XX_SPI_CLK_CFG); |
961 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
962 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
963 | ||
375981f2 G |
964 | /* Clear any irq pending bits, should set and clear the bits */ |
965 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
966 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
967 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
968 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
969 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); | |
970 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); | |
230d42d4 JB |
971 | |
972 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
973 | ||
974 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
975 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
976 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
977 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
978 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
979 | ||
980 | flush_fifo(sdd); | |
981 | } | |
982 | ||
2b908075 | 983 | #ifdef CONFIG_OF |
75bf3361 | 984 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
2b908075 TA |
985 | { |
986 | struct s3c64xx_spi_info *sci; | |
987 | u32 temp; | |
988 | ||
989 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | |
990 | if (!sci) { | |
991 | dev_err(dev, "memory allocation for spi_info failed\n"); | |
992 | return ERR_PTR(-ENOMEM); | |
993 | } | |
994 | ||
995 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | |
75bf3361 | 996 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
2b908075 TA |
997 | sci->src_clk_nr = 0; |
998 | } else { | |
999 | sci->src_clk_nr = temp; | |
1000 | } | |
1001 | ||
1002 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | |
75bf3361 | 1003 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
2b908075 TA |
1004 | sci->num_cs = 1; |
1005 | } else { | |
1006 | sci->num_cs = temp; | |
1007 | } | |
1008 | ||
1009 | return sci; | |
1010 | } | |
1011 | #else | |
1012 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1013 | { | |
8074cf06 | 1014 | return dev_get_platdata(dev); |
2b908075 | 1015 | } |
2b908075 TA |
1016 | #endif |
1017 | ||
1018 | static const struct of_device_id s3c64xx_spi_dt_match[]; | |
1019 | ||
a5238e36 TA |
1020 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
1021 | struct platform_device *pdev) | |
1022 | { | |
2b908075 TA |
1023 | #ifdef CONFIG_OF |
1024 | if (pdev->dev.of_node) { | |
1025 | const struct of_device_id *match; | |
1026 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | |
1027 | return (struct s3c64xx_spi_port_config *)match->data; | |
1028 | } | |
1029 | #endif | |
a5238e36 TA |
1030 | return (struct s3c64xx_spi_port_config *) |
1031 | platform_get_device_id(pdev)->driver_data; | |
1032 | } | |
1033 | ||
2deff8d6 | 1034 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
230d42d4 | 1035 | { |
2b908075 | 1036 | struct resource *mem_res; |
b5be04d3 | 1037 | struct resource *res; |
230d42d4 | 1038 | struct s3c64xx_spi_driver_data *sdd; |
8074cf06 | 1039 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); |
230d42d4 | 1040 | struct spi_master *master; |
c2573128 | 1041 | int ret, irq; |
a24d850b | 1042 | char clk_name[16]; |
230d42d4 | 1043 | |
2b908075 TA |
1044 | if (!sci && pdev->dev.of_node) { |
1045 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | |
1046 | if (IS_ERR(sci)) | |
1047 | return PTR_ERR(sci); | |
230d42d4 JB |
1048 | } |
1049 | ||
2b908075 | 1050 | if (!sci) { |
230d42d4 JB |
1051 | dev_err(&pdev->dev, "platform_data missing!\n"); |
1052 | return -ENODEV; | |
1053 | } | |
1054 | ||
230d42d4 JB |
1055 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1056 | if (mem_res == NULL) { | |
1057 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1058 | return -ENXIO; | |
1059 | } | |
1060 | ||
c2573128 MB |
1061 | irq = platform_get_irq(pdev, 0); |
1062 | if (irq < 0) { | |
1063 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1064 | return irq; | |
1065 | } | |
1066 | ||
230d42d4 JB |
1067 | master = spi_alloc_master(&pdev->dev, |
1068 | sizeof(struct s3c64xx_spi_driver_data)); | |
1069 | if (master == NULL) { | |
1070 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1071 | return -ENOMEM; | |
1072 | } | |
1073 | ||
230d42d4 JB |
1074 | platform_set_drvdata(pdev, master); |
1075 | ||
1076 | sdd = spi_master_get_devdata(master); | |
a5238e36 | 1077 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
230d42d4 JB |
1078 | sdd->master = master; |
1079 | sdd->cntrlr_info = sci; | |
1080 | sdd->pdev = pdev; | |
1081 | sdd->sfr_start = mem_res->start; | |
3146beec | 1082 | sdd->cs_gpio = true; |
2b908075 | 1083 | if (pdev->dev.of_node) { |
3146beec G |
1084 | if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL)) |
1085 | sdd->cs_gpio = false; | |
1086 | ||
2b908075 TA |
1087 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); |
1088 | if (ret < 0) { | |
75bf3361 JH |
1089 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
1090 | ret); | |
2b908075 TA |
1091 | goto err0; |
1092 | } | |
1093 | sdd->port_id = ret; | |
1094 | } else { | |
1095 | sdd->port_id = pdev->id; | |
1096 | } | |
230d42d4 JB |
1097 | |
1098 | sdd->cur_bpw = 8; | |
1099 | ||
b5be04d3 PV |
1100 | if (!sdd->pdev->dev.of_node) { |
1101 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1102 | if (!res) { | |
db0606ec | 1103 | dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); |
7e995556 G |
1104 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
1105 | } else | |
1106 | sdd->tx_dma.dmach = res->start; | |
b5be04d3 PV |
1107 | |
1108 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1109 | if (!res) { | |
db0606ec | 1110 | dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); |
7e995556 G |
1111 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; |
1112 | } else | |
1113 | sdd->rx_dma.dmach = res->start; | |
b5be04d3 | 1114 | } |
2b908075 | 1115 | |
b5be04d3 PV |
1116 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
1117 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; | |
2b908075 TA |
1118 | |
1119 | master->dev.of_node = pdev->dev.of_node; | |
a5238e36 | 1120 | master->bus_num = sdd->port_id; |
230d42d4 | 1121 | master->setup = s3c64xx_spi_setup; |
1c20c200 | 1122 | master->cleanup = s3c64xx_spi_cleanup; |
ad2a99af | 1123 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
6bb9c0e3 | 1124 | master->prepare_message = s3c64xx_spi_prepare_message; |
0732a9d2 | 1125 | master->transfer_one = s3c64xx_spi_transfer_one; |
ad2a99af | 1126 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
230d42d4 JB |
1127 | master->num_chipselect = sci->num_cs; |
1128 | master->dma_alignment = 8; | |
24778be2 SW |
1129 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
1130 | SPI_BPW_MASK(8); | |
230d42d4 JB |
1131 | /* the spi->mode bits understood by this driver: */ |
1132 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
fc0f81b7 | 1133 | master->auto_runtime_pm = true; |
3f295887 MB |
1134 | if (!is_polling(sdd)) |
1135 | master->can_dma = s3c64xx_spi_can_dma; | |
230d42d4 | 1136 | |
b0ee5605 TR |
1137 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
1138 | if (IS_ERR(sdd->regs)) { | |
1139 | ret = PTR_ERR(sdd->regs); | |
4eb77006 | 1140 | goto err0; |
230d42d4 JB |
1141 | } |
1142 | ||
00ab5392 | 1143 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
230d42d4 JB |
1144 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1145 | ret = -EBUSY; | |
4eb77006 | 1146 | goto err0; |
230d42d4 JB |
1147 | } |
1148 | ||
1149 | /* Setup clocks */ | |
4eb77006 | 1150 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
230d42d4 JB |
1151 | if (IS_ERR(sdd->clk)) { |
1152 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1153 | ret = PTR_ERR(sdd->clk); | |
00ab5392 | 1154 | goto err0; |
230d42d4 JB |
1155 | } |
1156 | ||
9f667bff | 1157 | if (clk_prepare_enable(sdd->clk)) { |
230d42d4 JB |
1158 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
1159 | ret = -EBUSY; | |
00ab5392 | 1160 | goto err0; |
230d42d4 JB |
1161 | } |
1162 | ||
a24d850b | 1163 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
4eb77006 | 1164 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
b0d5d6e5 | 1165 | if (IS_ERR(sdd->src_clk)) { |
230d42d4 | 1166 | dev_err(&pdev->dev, |
a24d850b | 1167 | "Unable to acquire clock '%s'\n", clk_name); |
b0d5d6e5 | 1168 | ret = PTR_ERR(sdd->src_clk); |
4eb77006 | 1169 | goto err2; |
230d42d4 JB |
1170 | } |
1171 | ||
9f667bff | 1172 | if (clk_prepare_enable(sdd->src_clk)) { |
a24d850b | 1173 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
230d42d4 | 1174 | ret = -EBUSY; |
4eb77006 | 1175 | goto err2; |
230d42d4 JB |
1176 | } |
1177 | ||
230d42d4 | 1178 | /* Setup Deufult Mode */ |
a5238e36 | 1179 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 JB |
1180 | |
1181 | spin_lock_init(&sdd->lock); | |
1182 | init_completion(&sdd->xfer_completion); | |
230d42d4 | 1183 | |
4eb77006 JH |
1184 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
1185 | "spi-s3c64xx", sdd); | |
c2573128 MB |
1186 | if (ret != 0) { |
1187 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1188 | irq, ret); | |
4eb77006 | 1189 | goto err3; |
c2573128 MB |
1190 | } |
1191 | ||
1192 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1193 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1194 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1195 | ||
38338250 | 1196 | pm_runtime_set_active(&pdev->dev); |
3e2bd64d MB |
1197 | pm_runtime_enable(&pdev->dev); |
1198 | ||
91800f0e MB |
1199 | ret = devm_spi_register_master(&pdev->dev, master); |
1200 | if (ret != 0) { | |
1201 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); | |
4eb77006 | 1202 | goto err3; |
230d42d4 JB |
1203 | } |
1204 | ||
75bf3361 | 1205 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
a5238e36 | 1206 | sdd->port_id, master->num_chipselect); |
c65bc4a8 JH |
1207 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n", |
1208 | mem_res, | |
82ab8cd7 | 1209 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
230d42d4 JB |
1210 | |
1211 | return 0; | |
1212 | ||
4eb77006 | 1213 | err3: |
9f667bff | 1214 | clk_disable_unprepare(sdd->src_clk); |
4eb77006 | 1215 | err2: |
9f667bff | 1216 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1217 | err0: |
230d42d4 JB |
1218 | spi_master_put(master); |
1219 | ||
1220 | return ret; | |
1221 | } | |
1222 | ||
1223 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1224 | { | |
1225 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
1226 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
230d42d4 | 1227 | |
b97b6621 MB |
1228 | pm_runtime_disable(&pdev->dev); |
1229 | ||
c2573128 MB |
1230 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1231 | ||
9f667bff | 1232 | clk_disable_unprepare(sdd->src_clk); |
230d42d4 | 1233 | |
9f667bff | 1234 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1235 | |
230d42d4 JB |
1236 | return 0; |
1237 | } | |
1238 | ||
997230d0 | 1239 | #ifdef CONFIG_PM_SLEEP |
e25d0bf9 | 1240 | static int s3c64xx_spi_suspend(struct device *dev) |
230d42d4 | 1241 | { |
9a2a5245 | 1242 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1243 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1244 | |
347de6ba KK |
1245 | int ret = spi_master_suspend(master); |
1246 | if (ret) | |
1247 | return ret; | |
230d42d4 | 1248 | |
9d7fd21a KK |
1249 | if (!pm_runtime_suspended(dev)) { |
1250 | clk_disable_unprepare(sdd->clk); | |
1251 | clk_disable_unprepare(sdd->src_clk); | |
1252 | } | |
230d42d4 JB |
1253 | |
1254 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
e25d0bf9 | 1259 | static int s3c64xx_spi_resume(struct device *dev) |
230d42d4 | 1260 | { |
9a2a5245 | 1261 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1262 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
ad7de729 | 1263 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 | 1264 | |
00ab5392 | 1265 | if (sci->cfg_gpio) |
2b908075 | 1266 | sci->cfg_gpio(); |
230d42d4 | 1267 | |
9d7fd21a KK |
1268 | if (!pm_runtime_suspended(dev)) { |
1269 | clk_prepare_enable(sdd->src_clk); | |
1270 | clk_prepare_enable(sdd->clk); | |
1271 | } | |
230d42d4 | 1272 | |
a5238e36 | 1273 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 | 1274 | |
347de6ba | 1275 | return spi_master_resume(master); |
230d42d4 | 1276 | } |
997230d0 | 1277 | #endif /* CONFIG_PM_SLEEP */ |
230d42d4 | 1278 | |
b97b6621 MB |
1279 | #ifdef CONFIG_PM_RUNTIME |
1280 | static int s3c64xx_spi_runtime_suspend(struct device *dev) | |
1281 | { | |
9a2a5245 | 1282 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 MB |
1283 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1284 | ||
9f667bff TA |
1285 | clk_disable_unprepare(sdd->clk); |
1286 | clk_disable_unprepare(sdd->src_clk); | |
b97b6621 MB |
1287 | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1292 | { | |
9a2a5245 | 1293 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 | 1294 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
8b06d5b8 | 1295 | int ret; |
b97b6621 | 1296 | |
8b06d5b8 MB |
1297 | ret = clk_prepare_enable(sdd->src_clk); |
1298 | if (ret != 0) | |
1299 | return ret; | |
1300 | ||
1301 | ret = clk_prepare_enable(sdd->clk); | |
1302 | if (ret != 0) { | |
1303 | clk_disable_unprepare(sdd->src_clk); | |
1304 | return ret; | |
1305 | } | |
b97b6621 MB |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | #endif /* CONFIG_PM_RUNTIME */ | |
1310 | ||
e25d0bf9 MB |
1311 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1312 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
b97b6621 MB |
1313 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1314 | s3c64xx_spi_runtime_resume, NULL) | |
e25d0bf9 MB |
1315 | }; |
1316 | ||
10ce0473 | 1317 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
a5238e36 TA |
1318 | .fifo_lvl_mask = { 0x7f }, |
1319 | .rx_lvl_offset = 13, | |
1320 | .tx_st_done = 21, | |
1321 | .high_speed = true, | |
1322 | }; | |
1323 | ||
10ce0473 | 1324 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
a5238e36 TA |
1325 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1326 | .rx_lvl_offset = 13, | |
1327 | .tx_st_done = 21, | |
1328 | }; | |
1329 | ||
10ce0473 | 1330 | static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { |
a5238e36 TA |
1331 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1332 | .rx_lvl_offset = 15, | |
1333 | .tx_st_done = 25, | |
1334 | }; | |
1335 | ||
10ce0473 | 1336 | static struct s3c64xx_spi_port_config s5pc100_spi_port_config = { |
a5238e36 TA |
1337 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1338 | .rx_lvl_offset = 13, | |
1339 | .tx_st_done = 21, | |
1340 | .high_speed = true, | |
1341 | }; | |
1342 | ||
10ce0473 | 1343 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
a5238e36 TA |
1344 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1345 | .rx_lvl_offset = 15, | |
1346 | .tx_st_done = 25, | |
1347 | .high_speed = true, | |
1348 | }; | |
1349 | ||
10ce0473 | 1350 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
a5238e36 TA |
1351 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
1352 | .rx_lvl_offset = 15, | |
1353 | .tx_st_done = 25, | |
1354 | .high_speed = true, | |
1355 | .clk_from_cmu = true, | |
1356 | }; | |
1357 | ||
bff82038 G |
1358 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
1359 | .fifo_lvl_mask = { 0x1ff }, | |
1360 | .rx_lvl_offset = 15, | |
1361 | .tx_st_done = 25, | |
1362 | .high_speed = true, | |
1363 | .clk_from_cmu = true, | |
1364 | .quirks = S3C64XX_SPI_QUIRK_POLL, | |
1365 | }; | |
1366 | ||
a5238e36 TA |
1367 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { |
1368 | { | |
1369 | .name = "s3c2443-spi", | |
1370 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | |
1371 | }, { | |
1372 | .name = "s3c6410-spi", | |
1373 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | |
1374 | }, { | |
1375 | .name = "s5p64x0-spi", | |
1376 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, | |
1377 | }, { | |
1378 | .name = "s5pc100-spi", | |
1379 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, | |
1380 | }, { | |
1381 | .name = "s5pv210-spi", | |
1382 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, | |
1383 | }, { | |
1384 | .name = "exynos4210-spi", | |
1385 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, | |
1386 | }, | |
1387 | { }, | |
1388 | }; | |
1389 | ||
2b908075 | 1390 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
a3b924df MK |
1391 | { .compatible = "samsung,s3c2443-spi", |
1392 | .data = (void *)&s3c2443_spi_port_config, | |
1393 | }, | |
1394 | { .compatible = "samsung,s3c6410-spi", | |
1395 | .data = (void *)&s3c6410_spi_port_config, | |
1396 | }, | |
1397 | { .compatible = "samsung,s5pc100-spi", | |
1398 | .data = (void *)&s5pc100_spi_port_config, | |
1399 | }, | |
1400 | { .compatible = "samsung,s5pv210-spi", | |
1401 | .data = (void *)&s5pv210_spi_port_config, | |
1402 | }, | |
2b908075 TA |
1403 | { .compatible = "samsung,exynos4210-spi", |
1404 | .data = (void *)&exynos4_spi_port_config, | |
1405 | }, | |
bff82038 G |
1406 | { .compatible = "samsung,exynos5440-spi", |
1407 | .data = (void *)&exynos5440_spi_port_config, | |
1408 | }, | |
2b908075 TA |
1409 | { }, |
1410 | }; | |
1411 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | |
2b908075 | 1412 | |
230d42d4 JB |
1413 | static struct platform_driver s3c64xx_spi_driver = { |
1414 | .driver = { | |
1415 | .name = "s3c64xx-spi", | |
1416 | .owner = THIS_MODULE, | |
e25d0bf9 | 1417 | .pm = &s3c64xx_spi_pm, |
2b908075 | 1418 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
230d42d4 | 1419 | }, |
50c959fc | 1420 | .probe = s3c64xx_spi_probe, |
230d42d4 | 1421 | .remove = s3c64xx_spi_remove, |
a5238e36 | 1422 | .id_table = s3c64xx_spi_driver_ids, |
230d42d4 JB |
1423 | }; |
1424 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1425 | ||
50c959fc | 1426 | module_platform_driver(s3c64xx_spi_driver); |
230d42d4 JB |
1427 | |
1428 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1429 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1430 | MODULE_LICENSE("GPL"); |