Commit | Line | Data |
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ca632f55 | 1 | /* |
230d42d4 JB |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
230d42d4 JB |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
c2573128 | 18 | #include <linux/interrupt.h> |
230d42d4 JB |
19 | #include <linux/delay.h> |
20 | #include <linux/clk.h> | |
21 | #include <linux/dma-mapping.h> | |
78843727 | 22 | #include <linux/dmaengine.h> |
230d42d4 | 23 | #include <linux/platform_device.h> |
b97b6621 | 24 | #include <linux/pm_runtime.h> |
230d42d4 | 25 | #include <linux/spi/spi.h> |
1c20c200 | 26 | #include <linux/gpio.h> |
2b908075 TA |
27 | #include <linux/of.h> |
28 | #include <linux/of_gpio.h> | |
230d42d4 | 29 | |
436d42c6 | 30 | #include <linux/platform_data/spi-s3c64xx.h> |
230d42d4 | 31 | |
bf77cba9 | 32 | #define MAX_SPI_PORTS 6 |
7e995556 | 33 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
bf77cba9 | 34 | #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) |
483867ee | 35 | #define AUTOSUSPEND_TIMEOUT 2000 |
a5238e36 | 36 | |
230d42d4 JB |
37 | /* Registers and bit-fields */ |
38 | ||
39 | #define S3C64XX_SPI_CH_CFG 0x00 | |
40 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
41 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
42 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
43 | #define S3C64XX_SPI_INT_EN 0x10 | |
44 | #define S3C64XX_SPI_STATUS 0x14 | |
45 | #define S3C64XX_SPI_TX_DATA 0x18 | |
46 | #define S3C64XX_SPI_RX_DATA 0x1C | |
47 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
48 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
49 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
50 | #define S3C64XX_SPI_FB_CLK 0x2C | |
51 | ||
52 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
53 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
54 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
55 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
56 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
57 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
58 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
59 | ||
60 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
61 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
62 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
75bf3361 | 63 | #define S3C64XX_SPI_PSR_MASK 0xff |
230d42d4 JB |
64 | |
65 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
66 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
67 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
69 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
70 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
71 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
72 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
73 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
74 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
75 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
76 | ||
77 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
78 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
bf77cba9 | 79 | #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) |
230d42d4 | 80 | |
230d42d4 JB |
81 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
82 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
83 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
84 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
85 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
86 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
87 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
88 | ||
89 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
90 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
91 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
92 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
93 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
94 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
95 | ||
96 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
97 | ||
98 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
99 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
100 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
101 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
102 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
103 | ||
104 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
105 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
106 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
107 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
108 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
109 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
110 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
111 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
112 | ||
113 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
114 | ||
a5238e36 TA |
115 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
116 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | |
117 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | |
118 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | |
119 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | |
120 | FIFO_LVL_MASK(i)) | |
230d42d4 JB |
121 | |
122 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
123 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
124 | ||
125 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
126 | ||
127 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
7e995556 | 128 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
230d42d4 | 129 | |
230d42d4 JB |
130 | #define RXBUSY (1<<2) |
131 | #define TXBUSY (1<<3) | |
132 | ||
82ab8cd7 | 133 | struct s3c64xx_spi_dma_data { |
78843727 | 134 | struct dma_chan *ch; |
c10356b9 | 135 | enum dma_transfer_direction direction; |
82ab8cd7 BK |
136 | }; |
137 | ||
a5238e36 TA |
138 | /** |
139 | * struct s3c64xx_spi_info - SPI Controller hardware info | |
140 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | |
141 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | |
142 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | |
143 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | |
144 | * @clk_from_cmu: True, if the controller does not include a clock mux and | |
145 | * prescaler unit. | |
146 | * | |
147 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | |
148 | * differ in some aspects such as the size of the fifo and spi bus clock | |
149 | * setup. Such differences are specified to the driver using this structure | |
150 | * which is provided as driver data to the driver. | |
151 | */ | |
152 | struct s3c64xx_spi_port_config { | |
153 | int fifo_lvl_mask[MAX_SPI_PORTS]; | |
154 | int rx_lvl_offset; | |
155 | int tx_st_done; | |
7e995556 | 156 | int quirks; |
a5238e36 TA |
157 | bool high_speed; |
158 | bool clk_from_cmu; | |
7990b008 | 159 | bool clk_ioclk; |
a5238e36 TA |
160 | }; |
161 | ||
230d42d4 JB |
162 | /** |
163 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
164 | * @clk: Pointer to the spi clock. | |
b0d5d6e5 | 165 | * @src_clk: Pointer to the clock used to generate SPI signals. |
7990b008 | 166 | * @ioclk: Pointer to the i/o clock between master and slave |
230d42d4 | 167 | * @master: Pointer to the SPI Protocol master. |
230d42d4 JB |
168 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
169 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
230d42d4 JB |
170 | * @lock: Controller specific lock. |
171 | * @state: Set of FLAGS to indicate status. | |
172 | * @rx_dmach: Controller's DMA channel for Rx. | |
173 | * @tx_dmach: Controller's DMA channel for Tx. | |
174 | * @sfr_start: BUS address of SPI controller regs. | |
175 | * @regs: Pointer to ioremap'ed controller registers. | |
c2573128 | 176 | * @irq: interrupt |
230d42d4 JB |
177 | * @xfer_completion: To indicate completion of xfer task. |
178 | * @cur_mode: Stores the active configuration of the controller. | |
179 | * @cur_bpw: Stores the active bits per word settings. | |
180 | * @cur_speed: Stores the active xfer clock speed. | |
181 | */ | |
182 | struct s3c64xx_spi_driver_data { | |
183 | void __iomem *regs; | |
184 | struct clk *clk; | |
b0d5d6e5 | 185 | struct clk *src_clk; |
7990b008 | 186 | struct clk *ioclk; |
230d42d4 JB |
187 | struct platform_device *pdev; |
188 | struct spi_master *master; | |
ad7de729 | 189 | struct s3c64xx_spi_info *cntrlr_info; |
230d42d4 | 190 | struct spi_device *tgl_spi; |
230d42d4 | 191 | spinlock_t lock; |
230d42d4 JB |
192 | unsigned long sfr_start; |
193 | struct completion xfer_completion; | |
194 | unsigned state; | |
195 | unsigned cur_mode, cur_bpw; | |
196 | unsigned cur_speed; | |
82ab8cd7 BK |
197 | struct s3c64xx_spi_dma_data rx_dma; |
198 | struct s3c64xx_spi_dma_data tx_dma; | |
a5238e36 TA |
199 | struct s3c64xx_spi_port_config *port_conf; |
200 | unsigned int port_id; | |
230d42d4 JB |
201 | }; |
202 | ||
230d42d4 JB |
203 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
204 | { | |
230d42d4 JB |
205 | void __iomem *regs = sdd->regs; |
206 | unsigned long loops; | |
207 | u32 val; | |
208 | ||
209 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
210 | ||
7d859ff4 KK |
211 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
212 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
213 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
214 | ||
230d42d4 JB |
215 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
216 | val |= S3C64XX_SPI_CH_SW_RST; | |
217 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
218 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
219 | ||
220 | /* Flush TxFIFO*/ | |
221 | loops = msecs_to_loops(1); | |
222 | do { | |
223 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 224 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
230d42d4 | 225 | |
be7852a8 MB |
226 | if (loops == 0) |
227 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
228 | ||
230d42d4 JB |
229 | /* Flush RxFIFO*/ |
230 | loops = msecs_to_loops(1); | |
231 | do { | |
232 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 233 | if (RX_FIFO_LVL(val, sdd)) |
230d42d4 JB |
234 | readl(regs + S3C64XX_SPI_RX_DATA); |
235 | else | |
236 | break; | |
237 | } while (loops--); | |
238 | ||
be7852a8 MB |
239 | if (loops == 0) |
240 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
241 | ||
230d42d4 JB |
242 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
243 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
244 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
245 | ||
246 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
247 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
248 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
230d42d4 JB |
249 | } |
250 | ||
82ab8cd7 | 251 | static void s3c64xx_spi_dmacb(void *data) |
39d3e807 | 252 | { |
82ab8cd7 BK |
253 | struct s3c64xx_spi_driver_data *sdd; |
254 | struct s3c64xx_spi_dma_data *dma = data; | |
39d3e807 BK |
255 | unsigned long flags; |
256 | ||
054ebcc4 | 257 | if (dma->direction == DMA_DEV_TO_MEM) |
82ab8cd7 BK |
258 | sdd = container_of(data, |
259 | struct s3c64xx_spi_driver_data, rx_dma); | |
260 | else | |
261 | sdd = container_of(data, | |
262 | struct s3c64xx_spi_driver_data, tx_dma); | |
263 | ||
39d3e807 BK |
264 | spin_lock_irqsave(&sdd->lock, flags); |
265 | ||
054ebcc4 | 266 | if (dma->direction == DMA_DEV_TO_MEM) { |
82ab8cd7 BK |
267 | sdd->state &= ~RXBUSY; |
268 | if (!(sdd->state & TXBUSY)) | |
269 | complete(&sdd->xfer_completion); | |
270 | } else { | |
271 | sdd->state &= ~TXBUSY; | |
272 | if (!(sdd->state & RXBUSY)) | |
273 | complete(&sdd->xfer_completion); | |
274 | } | |
39d3e807 BK |
275 | |
276 | spin_unlock_irqrestore(&sdd->lock, flags); | |
277 | } | |
278 | ||
78843727 | 279 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
6ad45a27 | 280 | struct sg_table *sgt) |
78843727 AB |
281 | { |
282 | struct s3c64xx_spi_driver_data *sdd; | |
283 | struct dma_slave_config config; | |
78843727 AB |
284 | struct dma_async_tx_descriptor *desc; |
285 | ||
b1a8e78d TF |
286 | memset(&config, 0, sizeof(config)); |
287 | ||
78843727 AB |
288 | if (dma->direction == DMA_DEV_TO_MEM) { |
289 | sdd = container_of((void *)dma, | |
290 | struct s3c64xx_spi_driver_data, rx_dma); | |
291 | config.direction = dma->direction; | |
292 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
293 | config.src_addr_width = sdd->cur_bpw / 8; | |
294 | config.src_maxburst = 1; | |
295 | dmaengine_slave_config(dma->ch, &config); | |
296 | } else { | |
297 | sdd = container_of((void *)dma, | |
298 | struct s3c64xx_spi_driver_data, tx_dma); | |
299 | config.direction = dma->direction; | |
300 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
301 | config.dst_addr_width = sdd->cur_bpw / 8; | |
302 | config.dst_maxburst = 1; | |
303 | dmaengine_slave_config(dma->ch, &config); | |
304 | } | |
305 | ||
6ad45a27 MB |
306 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, |
307 | dma->direction, DMA_PREP_INTERRUPT); | |
78843727 AB |
308 | |
309 | desc->callback = s3c64xx_spi_dmacb; | |
310 | desc->callback_param = dma; | |
311 | ||
312 | dmaengine_submit(desc); | |
313 | dma_async_issue_pending(dma->ch); | |
314 | } | |
315 | ||
aa4964c4 AS |
316 | static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) |
317 | { | |
318 | struct s3c64xx_spi_driver_data *sdd = | |
319 | spi_master_get_devdata(spi->master); | |
320 | ||
a92e7c3d AS |
321 | if (sdd->cntrlr_info->no_cs) |
322 | return; | |
323 | ||
aa4964c4 AS |
324 | if (enable) { |
325 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { | |
326 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
327 | } else { | |
328 | u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
329 | ||
330 | ssel |= (S3C64XX_SPI_SLAVE_AUTO | | |
331 | S3C64XX_SPI_SLAVE_NSC_CNT_2); | |
332 | writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
333 | } | |
334 | } else { | |
335 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
47c169ee DC |
336 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, |
337 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
aa4964c4 AS |
338 | } |
339 | } | |
340 | ||
78843727 AB |
341 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
342 | { | |
343 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
344 | dma_filter_fn filter = sdd->cntrlr_info->filter; | |
345 | struct device *dev = &sdd->pdev->dev; | |
346 | dma_cap_mask_t mask; | |
347 | ||
730d9d4d AS |
348 | if (is_polling(sdd)) |
349 | return 0; | |
350 | ||
351 | dma_cap_zero(mask); | |
352 | dma_cap_set(DMA_SLAVE, mask); | |
353 | ||
354 | /* Acquire DMA channels */ | |
355 | sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, | |
356 | sdd->cntrlr_info->dma_rx, dev, "rx"); | |
357 | if (!sdd->rx_dma.ch) { | |
358 | dev_err(dev, "Failed to get RX DMA channel\n"); | |
359 | return -EBUSY; | |
fb9d044e | 360 | } |
730d9d4d | 361 | spi->dma_rx = sdd->rx_dma.ch; |
fb9d044e | 362 | |
730d9d4d AS |
363 | sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, |
364 | sdd->cntrlr_info->dma_tx, dev, "tx"); | |
365 | if (!sdd->tx_dma.ch) { | |
366 | dev_err(dev, "Failed to get TX DMA channel\n"); | |
367 | dma_release_channel(sdd->rx_dma.ch); | |
368 | return -EBUSY; | |
369 | } | |
370 | spi->dma_tx = sdd->tx_dma.ch; | |
fb9d044e | 371 | |
730d9d4d | 372 | return 0; |
78843727 AB |
373 | } |
374 | ||
375 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | |
376 | { | |
377 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
378 | ||
379 | /* Free DMA channels */ | |
7e995556 G |
380 | if (!is_polling(sdd)) { |
381 | dma_release_channel(sdd->rx_dma.ch); | |
382 | dma_release_channel(sdd->tx_dma.ch); | |
383 | } | |
78843727 | 384 | |
78843727 AB |
385 | return 0; |
386 | } | |
387 | ||
3f295887 MB |
388 | static bool s3c64xx_spi_can_dma(struct spi_master *master, |
389 | struct spi_device *spi, | |
390 | struct spi_transfer *xfer) | |
391 | { | |
392 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
393 | ||
394 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
395 | } | |
396 | ||
230d42d4 JB |
397 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
398 | struct spi_device *spi, | |
399 | struct spi_transfer *xfer, int dma_mode) | |
400 | { | |
230d42d4 JB |
401 | void __iomem *regs = sdd->regs; |
402 | u32 modecfg, chcfg; | |
403 | ||
404 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
405 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
406 | ||
407 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
408 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
409 | ||
410 | if (dma_mode) { | |
411 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
412 | } else { | |
413 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
414 | * this helps setting PCKT_CNT value for generating clocks | |
415 | * as exactly needed. | |
416 | */ | |
417 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
418 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
419 | | S3C64XX_SPI_PACKET_CNT_EN, | |
420 | regs + S3C64XX_SPI_PACKET_CNT); | |
421 | } | |
422 | ||
423 | if (xfer->tx_buf != NULL) { | |
424 | sdd->state |= TXBUSY; | |
425 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
426 | if (dma_mode) { | |
427 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
6ad45a27 | 428 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); |
230d42d4 | 429 | } else { |
0c92ecf1 JB |
430 | switch (sdd->cur_bpw) { |
431 | case 32: | |
432 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
433 | xfer->tx_buf, xfer->len / 4); | |
434 | break; | |
435 | case 16: | |
436 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
437 | xfer->tx_buf, xfer->len / 2); | |
438 | break; | |
439 | default: | |
440 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
441 | xfer->tx_buf, xfer->len); | |
442 | break; | |
443 | } | |
230d42d4 JB |
444 | } |
445 | } | |
446 | ||
447 | if (xfer->rx_buf != NULL) { | |
448 | sdd->state |= RXBUSY; | |
449 | ||
a5238e36 | 450 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
230d42d4 JB |
451 | && !(sdd->cur_mode & SPI_CPHA)) |
452 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
453 | ||
454 | if (dma_mode) { | |
455 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
456 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
457 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
458 | | S3C64XX_SPI_PACKET_CNT_EN, | |
459 | regs + S3C64XX_SPI_PACKET_CNT); | |
6ad45a27 | 460 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); |
230d42d4 JB |
461 | } |
462 | } | |
463 | ||
464 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
465 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
466 | } | |
467 | ||
79617073 | 468 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
7e995556 G |
469 | int timeout_ms) |
470 | { | |
471 | void __iomem *regs = sdd->regs; | |
472 | unsigned long val = 1; | |
473 | u32 status; | |
474 | ||
475 | /* max fifo depth available */ | |
476 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
477 | ||
478 | if (timeout_ms) | |
479 | val = msecs_to_loops(timeout_ms); | |
480 | ||
481 | do { | |
482 | status = readl(regs + S3C64XX_SPI_STATUS); | |
483 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); | |
484 | ||
485 | /* return the actual received data length */ | |
486 | return RX_FIFO_LVL(status, sdd); | |
230d42d4 JB |
487 | } |
488 | ||
3700c6eb MB |
489 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
490 | struct spi_transfer *xfer) | |
230d42d4 | 491 | { |
230d42d4 JB |
492 | void __iomem *regs = sdd->regs; |
493 | unsigned long val; | |
3700c6eb | 494 | u32 status; |
230d42d4 JB |
495 | int ms; |
496 | ||
497 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
498 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
9d8f86b5 | 499 | ms += 10; /* some tolerance */ |
230d42d4 | 500 | |
3700c6eb MB |
501 | val = msecs_to_jiffies(ms) + 10; |
502 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
503 | ||
504 | /* | |
505 | * If the previous xfer was completed within timeout, then | |
506 | * proceed further else return -EIO. | |
507 | * DmaTx returns after simply writing data in the FIFO, | |
508 | * w/o waiting for real transmission on the bus to finish. | |
509 | * DmaRx returns only after Dma read data from FIFO which | |
510 | * needs bus transmission to finish, so we don't worry if | |
511 | * Xfer involved Rx(with or without Tx). | |
512 | */ | |
513 | if (val && !xfer->rx_buf) { | |
514 | val = msecs_to_loops(10); | |
515 | status = readl(regs + S3C64XX_SPI_STATUS); | |
516 | while ((TX_FIFO_LVL(status, sdd) | |
517 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | |
518 | && --val) { | |
519 | cpu_relax(); | |
c3f139b6 | 520 | status = readl(regs + S3C64XX_SPI_STATUS); |
3700c6eb MB |
521 | } |
522 | ||
230d42d4 JB |
523 | } |
524 | ||
3700c6eb MB |
525 | /* If timed out while checking rx/tx status return error */ |
526 | if (!val) | |
527 | return -EIO; | |
230d42d4 | 528 | |
3700c6eb MB |
529 | return 0; |
530 | } | |
7e995556 | 531 | |
3700c6eb MB |
532 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
533 | struct spi_transfer *xfer) | |
534 | { | |
535 | void __iomem *regs = sdd->regs; | |
536 | unsigned long val; | |
537 | u32 status; | |
538 | int loops; | |
539 | u32 cpy_len; | |
540 | u8 *buf; | |
541 | int ms; | |
230d42d4 | 542 | |
3700c6eb MB |
543 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
544 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
545 | ms += 10; /* some tolerance */ | |
7e995556 | 546 | |
3700c6eb MB |
547 | val = msecs_to_loops(ms); |
548 | do { | |
549 | status = readl(regs + S3C64XX_SPI_STATUS); | |
550 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | |
7e995556 | 551 | |
3700c6eb MB |
552 | |
553 | /* If it was only Tx */ | |
554 | if (!xfer->rx_buf) { | |
555 | sdd->state &= ~TXBUSY; | |
556 | return 0; | |
230d42d4 JB |
557 | } |
558 | ||
3700c6eb MB |
559 | /* |
560 | * If the receive length is bigger than the controller fifo | |
561 | * size, calculate the loops and read the fifo as many times. | |
562 | * loops = length / max fifo size (calculated by using the | |
563 | * fifo mask). | |
564 | * For any size less than the fifo size the below code is | |
565 | * executed atleast once. | |
566 | */ | |
567 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); | |
568 | buf = xfer->rx_buf; | |
569 | do { | |
570 | /* wait for data to be received in the fifo */ | |
571 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, | |
572 | (loops ? ms : 0)); | |
573 | ||
574 | switch (sdd->cur_bpw) { | |
575 | case 32: | |
576 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
577 | buf, cpy_len / 4); | |
578 | break; | |
579 | case 16: | |
580 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
581 | buf, cpy_len / 2); | |
582 | break; | |
583 | default: | |
584 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
585 | buf, cpy_len); | |
586 | break; | |
587 | } | |
588 | ||
589 | buf = buf + cpy_len; | |
590 | } while (loops--); | |
591 | sdd->state &= ~RXBUSY; | |
592 | ||
230d42d4 JB |
593 | return 0; |
594 | } | |
595 | ||
230d42d4 JB |
596 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
597 | { | |
230d42d4 JB |
598 | void __iomem *regs = sdd->regs; |
599 | u32 val; | |
600 | ||
601 | /* Disable Clock */ | |
d9aaf1dc | 602 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
603 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
604 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
605 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
606 | } | |
230d42d4 JB |
607 | |
608 | /* Set Polarity and Phase */ | |
609 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
610 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
611 | S3C64XX_SPI_CPOL_L | | |
612 | S3C64XX_SPI_CPHA_B); | |
613 | ||
614 | if (sdd->cur_mode & SPI_CPOL) | |
615 | val |= S3C64XX_SPI_CPOL_L; | |
616 | ||
617 | if (sdd->cur_mode & SPI_CPHA) | |
618 | val |= S3C64XX_SPI_CPHA_B; | |
619 | ||
620 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
621 | ||
622 | /* Set Channel & DMA Mode */ | |
623 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
624 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
625 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
626 | ||
627 | switch (sdd->cur_bpw) { | |
628 | case 32: | |
629 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
0c92ecf1 | 630 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
230d42d4 JB |
631 | break; |
632 | case 16: | |
633 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
0c92ecf1 | 634 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
230d42d4 JB |
635 | break; |
636 | default: | |
637 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
0c92ecf1 | 638 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
230d42d4 JB |
639 | break; |
640 | } | |
230d42d4 JB |
641 | |
642 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
643 | ||
a5238e36 | 644 | if (sdd->port_conf->clk_from_cmu) { |
b42a81ca | 645 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
b42a81ca JB |
646 | } else { |
647 | /* Configure Clock */ | |
648 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
649 | val &= ~S3C64XX_SPI_PSR_MASK; | |
650 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
651 | & S3C64XX_SPI_PSR_MASK); | |
652 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
653 | ||
654 | /* Enable Clock */ | |
655 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
656 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
657 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
658 | } | |
230d42d4 JB |
659 | } |
660 | ||
230d42d4 JB |
661 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
662 | ||
6bb9c0e3 MB |
663 | static int s3c64xx_spi_prepare_message(struct spi_master *master, |
664 | struct spi_message *msg) | |
230d42d4 | 665 | { |
ad2a99af | 666 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 JB |
667 | struct spi_device *spi = msg->spi; |
668 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
230d42d4 | 669 | |
230d42d4 JB |
670 | /* Configure feedback delay */ |
671 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
672 | ||
6bb9c0e3 MB |
673 | return 0; |
674 | } | |
0c92ecf1 | 675 | |
0732a9d2 MB |
676 | static int s3c64xx_spi_transfer_one(struct spi_master *master, |
677 | struct spi_device *spi, | |
678 | struct spi_transfer *xfer) | |
6bb9c0e3 MB |
679 | { |
680 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
0732a9d2 | 681 | int status; |
6bb9c0e3 MB |
682 | u32 speed; |
683 | u8 bpw; | |
0732a9d2 MB |
684 | unsigned long flags; |
685 | int use_dma; | |
230d42d4 | 686 | |
3e83c194 | 687 | reinit_completion(&sdd->xfer_completion); |
230d42d4 | 688 | |
0732a9d2 MB |
689 | /* Only BPW and Speed may change across transfers */ |
690 | bpw = xfer->bits_per_word; | |
88d4a744 | 691 | speed = xfer->speed_hz; |
230d42d4 | 692 | |
0732a9d2 MB |
693 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
694 | sdd->cur_bpw = bpw; | |
695 | sdd->cur_speed = speed; | |
11f66f09 | 696 | sdd->cur_mode = spi->mode; |
0732a9d2 MB |
697 | s3c64xx_spi_config(sdd); |
698 | } | |
230d42d4 | 699 | |
0732a9d2 MB |
700 | /* Polling method for xfers not bigger than FIFO capacity */ |
701 | use_dma = 0; | |
702 | if (!is_polling(sdd) && | |
703 | (sdd->rx_dma.ch && sdd->tx_dma.ch && | |
704 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) | |
705 | use_dma = 1; | |
230d42d4 | 706 | |
0732a9d2 | 707 | spin_lock_irqsave(&sdd->lock, flags); |
230d42d4 | 708 | |
0732a9d2 MB |
709 | /* Pending only which is to be done */ |
710 | sdd->state &= ~RXBUSY; | |
711 | sdd->state &= ~TXBUSY; | |
230d42d4 | 712 | |
0732a9d2 | 713 | enable_datapath(sdd, spi, xfer, use_dma); |
230d42d4 | 714 | |
0732a9d2 | 715 | /* Start the signals */ |
aa4964c4 | 716 | s3c64xx_spi_set_cs(spi, true); |
230d42d4 | 717 | |
0732a9d2 | 718 | spin_unlock_irqrestore(&sdd->lock, flags); |
230d42d4 | 719 | |
3700c6eb MB |
720 | if (use_dma) |
721 | status = wait_for_dma(sdd, xfer); | |
722 | else | |
723 | status = wait_for_pio(sdd, xfer); | |
0732a9d2 MB |
724 | |
725 | if (status) { | |
726 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
727 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | |
728 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
729 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
730 | xfer->len); | |
731 | ||
732 | if (use_dma) { | |
733 | if (xfer->tx_buf != NULL | |
734 | && (sdd->state & TXBUSY)) | |
1b5e1b69 | 735 | dmaengine_terminate_all(sdd->tx_dma.ch); |
0732a9d2 MB |
736 | if (xfer->rx_buf != NULL |
737 | && (sdd->state & RXBUSY)) | |
1b5e1b69 | 738 | dmaengine_terminate_all(sdd->rx_dma.ch); |
230d42d4 | 739 | } |
8c09daa1 | 740 | } else { |
230d42d4 JB |
741 | flush_fifo(sdd); |
742 | } | |
743 | ||
0732a9d2 | 744 | return status; |
230d42d4 | 745 | } |
230d42d4 | 746 | |
2b908075 | 747 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
2b908075 TA |
748 | struct spi_device *spi) |
749 | { | |
750 | struct s3c64xx_spi_csinfo *cs; | |
4732cc63 | 751 | struct device_node *slave_np, *data_np = NULL; |
2b908075 TA |
752 | u32 fb_delay = 0; |
753 | ||
754 | slave_np = spi->dev.of_node; | |
755 | if (!slave_np) { | |
756 | dev_err(&spi->dev, "device node not found\n"); | |
757 | return ERR_PTR(-EINVAL); | |
758 | } | |
759 | ||
06455bbc | 760 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
2b908075 TA |
761 | if (!data_np) { |
762 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | |
763 | return ERR_PTR(-EINVAL); | |
764 | } | |
765 | ||
766 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | |
767 | if (!cs) { | |
06455bbc | 768 | of_node_put(data_np); |
2b908075 TA |
769 | return ERR_PTR(-ENOMEM); |
770 | } | |
771 | ||
2b908075 TA |
772 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); |
773 | cs->fb_delay = fb_delay; | |
06455bbc | 774 | of_node_put(data_np); |
2b908075 TA |
775 | return cs; |
776 | } | |
777 | ||
230d42d4 JB |
778 | /* |
779 | * Here we only check the validity of requested configuration | |
780 | * and save the configuration in a local data-structure. | |
781 | * The controller is actually configured only just before we | |
782 | * get a message to transfer. | |
783 | */ | |
784 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
785 | { | |
786 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
787 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 788 | struct s3c64xx_spi_info *sci; |
2b908075 | 789 | int err; |
230d42d4 | 790 | |
2b908075 | 791 | sdd = spi_master_get_devdata(spi->master); |
306972ce | 792 | if (spi->dev.of_node) { |
5c725b34 | 793 | cs = s3c64xx_get_slave_ctrldata(spi); |
2b908075 | 794 | spi->controller_data = cs; |
306972ce NKC |
795 | } else if (cs) { |
796 | /* On non-DT platforms the SPI core will set spi->cs_gpio | |
797 | * to -ENOENT. The GPIO pin used to drive the chip select | |
798 | * is defined by using platform data so spi->cs_gpio value | |
799 | * has to be override to have the proper GPIO pin number. | |
800 | */ | |
801 | spi->cs_gpio = cs->line; | |
2b908075 TA |
802 | } |
803 | ||
804 | if (IS_ERR_OR_NULL(cs)) { | |
230d42d4 JB |
805 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
806 | return -ENODEV; | |
807 | } | |
808 | ||
0149871c | 809 | if (!spi_get_ctldata(spi)) { |
306972ce NKC |
810 | if (gpio_is_valid(spi->cs_gpio)) { |
811 | err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, | |
812 | dev_name(&spi->dev)); | |
813 | if (err) { | |
814 | dev_err(&spi->dev, | |
815 | "Failed to get /CS gpio [%d]: %d\n", | |
816 | spi->cs_gpio, err); | |
817 | goto err_gpio_req; | |
818 | } | |
1c20c200 | 819 | } |
1c20c200 | 820 | |
3146beec | 821 | spi_set_ctldata(spi, cs); |
230d42d4 JB |
822 | } |
823 | ||
230d42d4 | 824 | sci = sdd->cntrlr_info; |
230d42d4 | 825 | |
b97b6621 MB |
826 | pm_runtime_get_sync(&sdd->pdev->dev); |
827 | ||
230d42d4 | 828 | /* Check if we can provide the requested rate */ |
a5238e36 | 829 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
830 | u32 psr, speed; |
831 | ||
832 | /* Max possible */ | |
833 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
834 | ||
835 | if (spi->max_speed_hz > speed) | |
836 | spi->max_speed_hz = speed; | |
837 | ||
838 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
839 | psr &= S3C64XX_SPI_PSR_MASK; | |
840 | if (psr == S3C64XX_SPI_PSR_MASK) | |
841 | psr--; | |
842 | ||
843 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
844 | if (spi->max_speed_hz < speed) { | |
845 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
846 | psr++; | |
847 | } else { | |
848 | err = -EINVAL; | |
849 | goto setup_exit; | |
850 | } | |
851 | } | |
230d42d4 | 852 | |
b42a81ca | 853 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
2b908075 | 854 | if (spi->max_speed_hz >= speed) { |
b42a81ca | 855 | spi->max_speed_hz = speed; |
2b908075 | 856 | } else { |
e1b0f0df MB |
857 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
858 | spi->max_speed_hz); | |
230d42d4 | 859 | err = -EINVAL; |
2b908075 TA |
860 | goto setup_exit; |
861 | } | |
230d42d4 JB |
862 | } |
863 | ||
483867ee HK |
864 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
865 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
aa4964c4 AS |
866 | s3c64xx_spi_set_cs(spi, false); |
867 | ||
2b908075 | 868 | return 0; |
b97b6621 | 869 | |
230d42d4 | 870 | setup_exit: |
483867ee HK |
871 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
872 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
230d42d4 | 873 | /* setup() returns with device de-selected */ |
aa4964c4 | 874 | s3c64xx_spi_set_cs(spi, false); |
230d42d4 | 875 | |
306972ce NKC |
876 | if (gpio_is_valid(spi->cs_gpio)) |
877 | gpio_free(spi->cs_gpio); | |
2b908075 TA |
878 | spi_set_ctldata(spi, NULL); |
879 | ||
880 | err_gpio_req: | |
5bee3b94 SN |
881 | if (spi->dev.of_node) |
882 | kfree(cs); | |
2b908075 | 883 | |
230d42d4 JB |
884 | return err; |
885 | } | |
886 | ||
1c20c200 TA |
887 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
888 | { | |
889 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | |
890 | ||
306972ce | 891 | if (gpio_is_valid(spi->cs_gpio)) { |
dd97e268 | 892 | gpio_free(spi->cs_gpio); |
2b908075 TA |
893 | if (spi->dev.of_node) |
894 | kfree(cs); | |
306972ce NKC |
895 | else { |
896 | /* On non-DT platforms, the SPI core sets | |
897 | * spi->cs_gpio to -ENOENT and .setup() | |
898 | * overrides it with the GPIO pin value | |
899 | * passed using platform data. | |
900 | */ | |
901 | spi->cs_gpio = -ENOENT; | |
902 | } | |
2b908075 | 903 | } |
306972ce | 904 | |
1c20c200 TA |
905 | spi_set_ctldata(spi, NULL); |
906 | } | |
907 | ||
c2573128 MB |
908 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
909 | { | |
910 | struct s3c64xx_spi_driver_data *sdd = data; | |
911 | struct spi_master *spi = sdd->master; | |
375981f2 | 912 | unsigned int val, clr = 0; |
c2573128 | 913 | |
375981f2 | 914 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
c2573128 | 915 | |
375981f2 G |
916 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
917 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; | |
c2573128 | 918 | dev_err(&spi->dev, "RX overrun\n"); |
375981f2 G |
919 | } |
920 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { | |
921 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; | |
c2573128 | 922 | dev_err(&spi->dev, "RX underrun\n"); |
375981f2 G |
923 | } |
924 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { | |
925 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; | |
c2573128 | 926 | dev_err(&spi->dev, "TX overrun\n"); |
375981f2 G |
927 | } |
928 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { | |
929 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
c2573128 | 930 | dev_err(&spi->dev, "TX underrun\n"); |
375981f2 G |
931 | } |
932 | ||
933 | /* Clear the pending irq by setting and then clearing it */ | |
934 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
935 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
c2573128 MB |
936 | |
937 | return IRQ_HANDLED; | |
938 | } | |
939 | ||
230d42d4 JB |
940 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
941 | { | |
ad7de729 | 942 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
943 | void __iomem *regs = sdd->regs; |
944 | unsigned int val; | |
945 | ||
946 | sdd->cur_speed = 0; | |
947 | ||
a92e7c3d AS |
948 | if (sci->no_cs) |
949 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
950 | else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
bf77cba9 | 951 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
230d42d4 JB |
952 | |
953 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
954 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
955 | ||
a5238e36 | 956 | if (!sdd->port_conf->clk_from_cmu) |
b42a81ca | 957 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
230d42d4 JB |
958 | regs + S3C64XX_SPI_CLK_CFG); |
959 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
960 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
961 | ||
375981f2 G |
962 | /* Clear any irq pending bits, should set and clear the bits */ |
963 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
964 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
965 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
966 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
967 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); | |
968 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); | |
230d42d4 JB |
969 | |
970 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
971 | ||
972 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
973 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
974 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
975 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
976 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
977 | ||
978 | flush_fifo(sdd); | |
979 | } | |
980 | ||
2b908075 | 981 | #ifdef CONFIG_OF |
75bf3361 | 982 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
2b908075 TA |
983 | { |
984 | struct s3c64xx_spi_info *sci; | |
985 | u32 temp; | |
986 | ||
987 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | |
1273eb05 | 988 | if (!sci) |
2b908075 | 989 | return ERR_PTR(-ENOMEM); |
2b908075 TA |
990 | |
991 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | |
75bf3361 | 992 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
2b908075 TA |
993 | sci->src_clk_nr = 0; |
994 | } else { | |
995 | sci->src_clk_nr = temp; | |
996 | } | |
997 | ||
998 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | |
75bf3361 | 999 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
2b908075 TA |
1000 | sci->num_cs = 1; |
1001 | } else { | |
1002 | sci->num_cs = temp; | |
1003 | } | |
1004 | ||
a92e7c3d AS |
1005 | sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs"); |
1006 | ||
2b908075 TA |
1007 | return sci; |
1008 | } | |
1009 | #else | |
1010 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1011 | { | |
8074cf06 | 1012 | return dev_get_platdata(dev); |
2b908075 | 1013 | } |
2b908075 TA |
1014 | #endif |
1015 | ||
1016 | static const struct of_device_id s3c64xx_spi_dt_match[]; | |
1017 | ||
a5238e36 TA |
1018 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
1019 | struct platform_device *pdev) | |
1020 | { | |
2b908075 TA |
1021 | #ifdef CONFIG_OF |
1022 | if (pdev->dev.of_node) { | |
1023 | const struct of_device_id *match; | |
1024 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | |
1025 | return (struct s3c64xx_spi_port_config *)match->data; | |
1026 | } | |
1027 | #endif | |
a5238e36 TA |
1028 | return (struct s3c64xx_spi_port_config *) |
1029 | platform_get_device_id(pdev)->driver_data; | |
1030 | } | |
1031 | ||
2deff8d6 | 1032 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
230d42d4 | 1033 | { |
2b908075 | 1034 | struct resource *mem_res; |
230d42d4 | 1035 | struct s3c64xx_spi_driver_data *sdd; |
8074cf06 | 1036 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); |
230d42d4 | 1037 | struct spi_master *master; |
c2573128 | 1038 | int ret, irq; |
a24d850b | 1039 | char clk_name[16]; |
230d42d4 | 1040 | |
2b908075 TA |
1041 | if (!sci && pdev->dev.of_node) { |
1042 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | |
1043 | if (IS_ERR(sci)) | |
1044 | return PTR_ERR(sci); | |
230d42d4 JB |
1045 | } |
1046 | ||
2b908075 | 1047 | if (!sci) { |
230d42d4 JB |
1048 | dev_err(&pdev->dev, "platform_data missing!\n"); |
1049 | return -ENODEV; | |
1050 | } | |
1051 | ||
230d42d4 JB |
1052 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1053 | if (mem_res == NULL) { | |
1054 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1055 | return -ENXIO; | |
1056 | } | |
1057 | ||
c2573128 MB |
1058 | irq = platform_get_irq(pdev, 0); |
1059 | if (irq < 0) { | |
1060 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1061 | return irq; | |
1062 | } | |
1063 | ||
230d42d4 JB |
1064 | master = spi_alloc_master(&pdev->dev, |
1065 | sizeof(struct s3c64xx_spi_driver_data)); | |
1066 | if (master == NULL) { | |
1067 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1068 | return -ENOMEM; | |
1069 | } | |
1070 | ||
230d42d4 JB |
1071 | platform_set_drvdata(pdev, master); |
1072 | ||
1073 | sdd = spi_master_get_devdata(master); | |
a5238e36 | 1074 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
230d42d4 JB |
1075 | sdd->master = master; |
1076 | sdd->cntrlr_info = sci; | |
1077 | sdd->pdev = pdev; | |
1078 | sdd->sfr_start = mem_res->start; | |
2b908075 TA |
1079 | if (pdev->dev.of_node) { |
1080 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | |
1081 | if (ret < 0) { | |
75bf3361 JH |
1082 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
1083 | ret); | |
60a9a964 | 1084 | goto err_deref_master; |
2b908075 TA |
1085 | } |
1086 | sdd->port_id = ret; | |
1087 | } else { | |
1088 | sdd->port_id = pdev->id; | |
1089 | } | |
230d42d4 JB |
1090 | |
1091 | sdd->cur_bpw = 8; | |
1092 | ||
a0067db3 AB |
1093 | if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) { |
1094 | dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n"); | |
1095 | sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; | |
b5be04d3 | 1096 | } |
2b908075 | 1097 | |
b5be04d3 PV |
1098 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
1099 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; | |
2b908075 TA |
1100 | |
1101 | master->dev.of_node = pdev->dev.of_node; | |
a5238e36 | 1102 | master->bus_num = sdd->port_id; |
230d42d4 | 1103 | master->setup = s3c64xx_spi_setup; |
1c20c200 | 1104 | master->cleanup = s3c64xx_spi_cleanup; |
ad2a99af | 1105 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
6bb9c0e3 | 1106 | master->prepare_message = s3c64xx_spi_prepare_message; |
0732a9d2 | 1107 | master->transfer_one = s3c64xx_spi_transfer_one; |
ad2a99af | 1108 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
230d42d4 JB |
1109 | master->num_chipselect = sci->num_cs; |
1110 | master->dma_alignment = 8; | |
24778be2 SW |
1111 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
1112 | SPI_BPW_MASK(8); | |
230d42d4 JB |
1113 | /* the spi->mode bits understood by this driver: */ |
1114 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
fc0f81b7 | 1115 | master->auto_runtime_pm = true; |
3f295887 MB |
1116 | if (!is_polling(sdd)) |
1117 | master->can_dma = s3c64xx_spi_can_dma; | |
230d42d4 | 1118 | |
b0ee5605 TR |
1119 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
1120 | if (IS_ERR(sdd->regs)) { | |
1121 | ret = PTR_ERR(sdd->regs); | |
60a9a964 | 1122 | goto err_deref_master; |
230d42d4 JB |
1123 | } |
1124 | ||
00ab5392 | 1125 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
230d42d4 JB |
1126 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1127 | ret = -EBUSY; | |
60a9a964 | 1128 | goto err_deref_master; |
230d42d4 JB |
1129 | } |
1130 | ||
1131 | /* Setup clocks */ | |
4eb77006 | 1132 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
230d42d4 JB |
1133 | if (IS_ERR(sdd->clk)) { |
1134 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1135 | ret = PTR_ERR(sdd->clk); | |
60a9a964 | 1136 | goto err_deref_master; |
230d42d4 JB |
1137 | } |
1138 | ||
25981d82 AS |
1139 | ret = clk_prepare_enable(sdd->clk); |
1140 | if (ret) { | |
230d42d4 | 1141 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
60a9a964 | 1142 | goto err_deref_master; |
230d42d4 JB |
1143 | } |
1144 | ||
a24d850b | 1145 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
4eb77006 | 1146 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
b0d5d6e5 | 1147 | if (IS_ERR(sdd->src_clk)) { |
230d42d4 | 1148 | dev_err(&pdev->dev, |
a24d850b | 1149 | "Unable to acquire clock '%s'\n", clk_name); |
b0d5d6e5 | 1150 | ret = PTR_ERR(sdd->src_clk); |
60a9a964 | 1151 | goto err_disable_clk; |
230d42d4 JB |
1152 | } |
1153 | ||
25981d82 AS |
1154 | ret = clk_prepare_enable(sdd->src_clk); |
1155 | if (ret) { | |
a24d850b | 1156 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
60a9a964 | 1157 | goto err_disable_clk; |
230d42d4 JB |
1158 | } |
1159 | ||
7990b008 AS |
1160 | if (sdd->port_conf->clk_ioclk) { |
1161 | sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); | |
1162 | if (IS_ERR(sdd->ioclk)) { | |
1163 | dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); | |
1164 | ret = PTR_ERR(sdd->ioclk); | |
1165 | goto err_disable_src_clk; | |
1166 | } | |
1167 | ||
1168 | ret = clk_prepare_enable(sdd->ioclk); | |
1169 | if (ret) { | |
1170 | dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); | |
1171 | goto err_disable_src_clk; | |
1172 | } | |
1173 | } | |
1174 | ||
483867ee HK |
1175 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); |
1176 | pm_runtime_use_autosuspend(&pdev->dev); | |
1177 | pm_runtime_set_active(&pdev->dev); | |
1178 | pm_runtime_enable(&pdev->dev); | |
1179 | pm_runtime_get_sync(&pdev->dev); | |
1180 | ||
230d42d4 | 1181 | /* Setup Deufult Mode */ |
a5238e36 | 1182 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 JB |
1183 | |
1184 | spin_lock_init(&sdd->lock); | |
1185 | init_completion(&sdd->xfer_completion); | |
230d42d4 | 1186 | |
4eb77006 JH |
1187 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
1188 | "spi-s3c64xx", sdd); | |
c2573128 MB |
1189 | if (ret != 0) { |
1190 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1191 | irq, ret); | |
60a9a964 | 1192 | goto err_pm_put; |
c2573128 MB |
1193 | } |
1194 | ||
1195 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1196 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1197 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1198 | ||
91800f0e MB |
1199 | ret = devm_spi_register_master(&pdev->dev, master); |
1200 | if (ret != 0) { | |
1201 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); | |
60a9a964 | 1202 | goto err_pm_put; |
230d42d4 JB |
1203 | } |
1204 | ||
75bf3361 | 1205 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
a5238e36 | 1206 | sdd->port_id, master->num_chipselect); |
a0067db3 | 1207 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n", |
ed425dcf | 1208 | mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1, |
a0067db3 | 1209 | sci->dma_rx, sci->dma_tx); |
230d42d4 | 1210 | |
483867ee HK |
1211 | pm_runtime_mark_last_busy(&pdev->dev); |
1212 | pm_runtime_put_autosuspend(&pdev->dev); | |
1213 | ||
230d42d4 JB |
1214 | return 0; |
1215 | ||
60a9a964 | 1216 | err_pm_put: |
483867ee | 1217 | pm_runtime_put_noidle(&pdev->dev); |
3c863792 HK |
1218 | pm_runtime_disable(&pdev->dev); |
1219 | pm_runtime_set_suspended(&pdev->dev); | |
483867ee | 1220 | |
7990b008 AS |
1221 | clk_disable_unprepare(sdd->ioclk); |
1222 | err_disable_src_clk: | |
9f667bff | 1223 | clk_disable_unprepare(sdd->src_clk); |
60a9a964 | 1224 | err_disable_clk: |
9f667bff | 1225 | clk_disable_unprepare(sdd->clk); |
60a9a964 | 1226 | err_deref_master: |
230d42d4 JB |
1227 | spi_master_put(master); |
1228 | ||
1229 | return ret; | |
1230 | } | |
1231 | ||
1232 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1233 | { | |
9f135787 | 1234 | struct spi_master *master = platform_get_drvdata(pdev); |
230d42d4 | 1235 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1236 | |
8ebe9d16 | 1237 | pm_runtime_get_sync(&pdev->dev); |
b97b6621 | 1238 | |
c2573128 MB |
1239 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1240 | ||
7990b008 AS |
1241 | clk_disable_unprepare(sdd->ioclk); |
1242 | ||
9f667bff | 1243 | clk_disable_unprepare(sdd->src_clk); |
230d42d4 | 1244 | |
9f667bff | 1245 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1246 | |
8ebe9d16 HK |
1247 | pm_runtime_put_noidle(&pdev->dev); |
1248 | pm_runtime_disable(&pdev->dev); | |
1249 | pm_runtime_set_suspended(&pdev->dev); | |
1250 | ||
230d42d4 JB |
1251 | return 0; |
1252 | } | |
1253 | ||
997230d0 | 1254 | #ifdef CONFIG_PM_SLEEP |
e25d0bf9 | 1255 | static int s3c64xx_spi_suspend(struct device *dev) |
230d42d4 | 1256 | { |
9a2a5245 | 1257 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1258 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1259 | |
347de6ba KK |
1260 | int ret = spi_master_suspend(master); |
1261 | if (ret) | |
1262 | return ret; | |
230d42d4 | 1263 | |
4fcd9b9e HK |
1264 | ret = pm_runtime_force_suspend(dev); |
1265 | if (ret < 0) | |
1266 | return ret; | |
230d42d4 JB |
1267 | |
1268 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
e25d0bf9 | 1273 | static int s3c64xx_spi_resume(struct device *dev) |
230d42d4 | 1274 | { |
9a2a5245 | 1275 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1276 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
ad7de729 | 1277 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
4fcd9b9e | 1278 | int ret; |
230d42d4 | 1279 | |
00ab5392 | 1280 | if (sci->cfg_gpio) |
2b908075 | 1281 | sci->cfg_gpio(); |
230d42d4 | 1282 | |
4fcd9b9e HK |
1283 | ret = pm_runtime_force_resume(dev); |
1284 | if (ret < 0) | |
1285 | return ret; | |
230d42d4 | 1286 | |
a5238e36 | 1287 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 | 1288 | |
347de6ba | 1289 | return spi_master_resume(master); |
230d42d4 | 1290 | } |
997230d0 | 1291 | #endif /* CONFIG_PM_SLEEP */ |
230d42d4 | 1292 | |
ec833050 | 1293 | #ifdef CONFIG_PM |
b97b6621 MB |
1294 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
1295 | { | |
9a2a5245 | 1296 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 MB |
1297 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1298 | ||
9f667bff TA |
1299 | clk_disable_unprepare(sdd->clk); |
1300 | clk_disable_unprepare(sdd->src_clk); | |
7990b008 | 1301 | clk_disable_unprepare(sdd->ioclk); |
b97b6621 MB |
1302 | |
1303 | return 0; | |
1304 | } | |
1305 | ||
1306 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1307 | { | |
9a2a5245 | 1308 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 | 1309 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
8b06d5b8 | 1310 | int ret; |
b97b6621 | 1311 | |
7990b008 AS |
1312 | if (sdd->port_conf->clk_ioclk) { |
1313 | ret = clk_prepare_enable(sdd->ioclk); | |
1314 | if (ret != 0) | |
1315 | return ret; | |
1316 | } | |
1317 | ||
8b06d5b8 MB |
1318 | ret = clk_prepare_enable(sdd->src_clk); |
1319 | if (ret != 0) | |
7990b008 | 1320 | goto err_disable_ioclk; |
8b06d5b8 MB |
1321 | |
1322 | ret = clk_prepare_enable(sdd->clk); | |
7990b008 AS |
1323 | if (ret != 0) |
1324 | goto err_disable_src_clk; | |
b97b6621 MB |
1325 | |
1326 | return 0; | |
7990b008 AS |
1327 | |
1328 | err_disable_src_clk: | |
1329 | clk_disable_unprepare(sdd->src_clk); | |
1330 | err_disable_ioclk: | |
1331 | clk_disable_unprepare(sdd->ioclk); | |
1332 | ||
1333 | return ret; | |
b97b6621 | 1334 | } |
ec833050 | 1335 | #endif /* CONFIG_PM */ |
b97b6621 | 1336 | |
e25d0bf9 MB |
1337 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1338 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
b97b6621 MB |
1339 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1340 | s3c64xx_spi_runtime_resume, NULL) | |
e25d0bf9 MB |
1341 | }; |
1342 | ||
10ce0473 | 1343 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
a5238e36 TA |
1344 | .fifo_lvl_mask = { 0x7f }, |
1345 | .rx_lvl_offset = 13, | |
1346 | .tx_st_done = 21, | |
1347 | .high_speed = true, | |
1348 | }; | |
1349 | ||
10ce0473 | 1350 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
a5238e36 TA |
1351 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1352 | .rx_lvl_offset = 13, | |
1353 | .tx_st_done = 21, | |
1354 | }; | |
1355 | ||
10ce0473 | 1356 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
a5238e36 TA |
1357 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1358 | .rx_lvl_offset = 15, | |
1359 | .tx_st_done = 25, | |
1360 | .high_speed = true, | |
1361 | }; | |
1362 | ||
10ce0473 | 1363 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
a5238e36 TA |
1364 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
1365 | .rx_lvl_offset = 15, | |
1366 | .tx_st_done = 25, | |
1367 | .high_speed = true, | |
1368 | .clk_from_cmu = true, | |
1369 | }; | |
1370 | ||
bff82038 G |
1371 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
1372 | .fifo_lvl_mask = { 0x1ff }, | |
1373 | .rx_lvl_offset = 15, | |
1374 | .tx_st_done = 25, | |
1375 | .high_speed = true, | |
1376 | .clk_from_cmu = true, | |
1377 | .quirks = S3C64XX_SPI_QUIRK_POLL, | |
1378 | }; | |
1379 | ||
bf77cba9 PV |
1380 | static struct s3c64xx_spi_port_config exynos7_spi_port_config = { |
1381 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, | |
1382 | .rx_lvl_offset = 15, | |
1383 | .tx_st_done = 25, | |
1384 | .high_speed = true, | |
1385 | .clk_from_cmu = true, | |
1386 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1387 | }; | |
1388 | ||
7990b008 AS |
1389 | static struct s3c64xx_spi_port_config exynos5433_spi_port_config = { |
1390 | .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, | |
1391 | .rx_lvl_offset = 15, | |
1392 | .tx_st_done = 25, | |
1393 | .high_speed = true, | |
1394 | .clk_from_cmu = true, | |
1395 | .clk_ioclk = true, | |
1396 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1397 | }; | |
1398 | ||
23f6d39e | 1399 | static const struct platform_device_id s3c64xx_spi_driver_ids[] = { |
a5238e36 TA |
1400 | { |
1401 | .name = "s3c2443-spi", | |
1402 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | |
1403 | }, { | |
1404 | .name = "s3c6410-spi", | |
1405 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | |
a5238e36 TA |
1406 | }, |
1407 | { }, | |
1408 | }; | |
1409 | ||
2b908075 | 1410 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
a3b924df MK |
1411 | { .compatible = "samsung,s3c2443-spi", |
1412 | .data = (void *)&s3c2443_spi_port_config, | |
1413 | }, | |
1414 | { .compatible = "samsung,s3c6410-spi", | |
1415 | .data = (void *)&s3c6410_spi_port_config, | |
1416 | }, | |
a3b924df MK |
1417 | { .compatible = "samsung,s5pv210-spi", |
1418 | .data = (void *)&s5pv210_spi_port_config, | |
1419 | }, | |
2b908075 TA |
1420 | { .compatible = "samsung,exynos4210-spi", |
1421 | .data = (void *)&exynos4_spi_port_config, | |
1422 | }, | |
bff82038 G |
1423 | { .compatible = "samsung,exynos5440-spi", |
1424 | .data = (void *)&exynos5440_spi_port_config, | |
1425 | }, | |
bf77cba9 PV |
1426 | { .compatible = "samsung,exynos7-spi", |
1427 | .data = (void *)&exynos7_spi_port_config, | |
1428 | }, | |
7990b008 AS |
1429 | { .compatible = "samsung,exynos5433-spi", |
1430 | .data = (void *)&exynos5433_spi_port_config, | |
1431 | }, | |
2b908075 TA |
1432 | { }, |
1433 | }; | |
1434 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | |
2b908075 | 1435 | |
230d42d4 JB |
1436 | static struct platform_driver s3c64xx_spi_driver = { |
1437 | .driver = { | |
1438 | .name = "s3c64xx-spi", | |
e25d0bf9 | 1439 | .pm = &s3c64xx_spi_pm, |
2b908075 | 1440 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
230d42d4 | 1441 | }, |
50c959fc | 1442 | .probe = s3c64xx_spi_probe, |
230d42d4 | 1443 | .remove = s3c64xx_spi_remove, |
a5238e36 | 1444 | .id_table = s3c64xx_spi_driver_ids, |
230d42d4 JB |
1445 | }; |
1446 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1447 | ||
50c959fc | 1448 | module_platform_driver(s3c64xx_spi_driver); |
230d42d4 JB |
1449 | |
1450 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1451 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1452 | MODULE_LICENSE("GPL"); |