projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'next/dt-samsung' into next/devel-samsung-spi
[deliverable/linux.git] / drivers / spi / spi-s3c64xx.c
CommitLineData
ca632f55 1/*
230d42d4
JB		 2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
c2573128 23#include <linux/interrupt.h>
230d42d4
JB		 24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
b97b6621 28#include <linux/pm_runtime.h>
230d42d4 29#include <linux/spi/spi.h>
1c20c200 30#include <linux/gpio.h>
2b908075
TA		 31#include <linux/of.h>
32#include <linux/of_gpio.h>
230d42d4
JB		 33
34#include <mach/dma.h>
e6b873c9 35#include <plat/s3c64xx-spi.h>
230d42d4 36
a5238e36
TA		 37#define MAX_SPI_PORTS 3
38
230d42d4
JB		 39/* Registers and bit-fields */
40
41#define S3C64XX_SPI_CH_CFG 0x00
42#define S3C64XX_SPI_CLK_CFG 0x04
43#define S3C64XX_SPI_MODE_CFG 0x08
44#define S3C64XX_SPI_SLAVE_SEL 0x0C
45#define S3C64XX_SPI_INT_EN 0x10
46#define S3C64XX_SPI_STATUS 0x14
47#define S3C64XX_SPI_TX_DATA 0x18
48#define S3C64XX_SPI_RX_DATA 0x1C
49#define S3C64XX_SPI_PACKET_CNT 0x20
50#define S3C64XX_SPI_PENDING_CLR 0x24
51#define S3C64XX_SPI_SWAP_CFG 0x28
52#define S3C64XX_SPI_FB_CLK 0x2C
53
54#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
55#define S3C64XX_SPI_CH_SW_RST (1<<5)
56#define S3C64XX_SPI_CH_SLAVE (1<<4)
57#define S3C64XX_SPI_CPOL_L (1<<3)
58#define S3C64XX_SPI_CPHA_B (1<<2)
59#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
60#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
61
62#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
63#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
64#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
65#define S3C64XX_SPI_PSR_MASK 0xff
66
67#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
68#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
69#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
70#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
71#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
72#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
73#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
74#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
75#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
76#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
77#define S3C64XX_SPI_MODE_4BURST (1<<0)
78
79#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
80#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
81
82#define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
83
84#define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
85 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
86
87#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
88#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
89#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
90#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
91#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
92#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
93#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
94
95#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
96#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
97#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
98#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
99#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
100#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
101
102#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
103
104#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
105#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
106#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
107#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
108#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
109
110#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
111#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
112#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
113#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
114#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
115#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
116#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
117#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
118
119#define S3C64XX_SPI_FBCLK_MSK (3<<0)
120
a5238e36
TA		 121#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
122#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
123 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
124#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
125#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
126 FIFO_LVL_MASK(i))
230d42d4
JB		 127
128#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
129#define S3C64XX_SPI_TRAILCNT_OFF 19
130
131#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
132
133#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
134
230d42d4
JB		 135#define RXBUSY (1<<2)
136#define TXBUSY (1<<3)
137
82ab8cd7
BK		 138struct s3c64xx_spi_dma_data {
139 unsigned ch;
140 enum dma_data_direction direction;
141 enum dma_ch dmach;
2b908075 142 struct property *dma_prop;
82ab8cd7
BK		 143};
144
a5238e36
TA		 145/**
146 * struct s3c64xx_spi_info - SPI Controller hardware info
147 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
148 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
149 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
151 * @clk_from_cmu: True, if the controller does not include a clock mux and
152 * prescaler unit.
153 *
154 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
155 * differ in some aspects such as the size of the fifo and spi bus clock
156 * setup. Such differences are specified to the driver using this structure
157 * which is provided as driver data to the driver.
158 */
159struct s3c64xx_spi_port_config {
160 int fifo_lvl_mask[MAX_SPI_PORTS];
161 int rx_lvl_offset;
162 int tx_st_done;
163 bool high_speed;
164 bool clk_from_cmu;
165};
166
230d42d4
JB		 167/**
168 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
169 * @clk: Pointer to the spi clock.
b0d5d6e5 170 * @src_clk: Pointer to the clock used to generate SPI signals.
230d42d4 171 * @master: Pointer to the SPI Protocol master.
230d42d4
JB		 172 * @cntrlr_info: Platform specific data for the controller this driver manages.
173 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
230d42d4
JB		 174 * @queue: To log SPI xfer requests.
175 * @lock: Controller specific lock.
176 * @state: Set of FLAGS to indicate status.
177 * @rx_dmach: Controller's DMA channel for Rx.
178 * @tx_dmach: Controller's DMA channel for Tx.
179 * @sfr_start: BUS address of SPI controller regs.
180 * @regs: Pointer to ioremap'ed controller registers.
c2573128 181 * @irq: interrupt
230d42d4
JB		 182 * @xfer_completion: To indicate completion of xfer task.
183 * @cur_mode: Stores the active configuration of the controller.
184 * @cur_bpw: Stores the active bits per word settings.
185 * @cur_speed: Stores the active xfer clock speed.
186 */
187struct s3c64xx_spi_driver_data {
188 void __iomem *regs;
189 struct clk *clk;
b0d5d6e5 190 struct clk *src_clk;
230d42d4
JB		 191 struct platform_device *pdev;
192 struct spi_master *master;
ad7de729 193 struct s3c64xx_spi_info *cntrlr_info;
230d42d4 194 struct spi_device *tgl_spi;
230d42d4
JB		 195 struct list_head queue;
196 spinlock_t lock;
230d42d4
JB		 197 unsigned long sfr_start;
198 struct completion xfer_completion;
199 unsigned state;
200 unsigned cur_mode, cur_bpw;
201 unsigned cur_speed;
82ab8cd7
BK		 202 struct s3c64xx_spi_dma_data rx_dma;
203 struct s3c64xx_spi_dma_data tx_dma;
39d3e807 204 struct samsung_dma_ops *ops;
a5238e36
TA		 205 struct s3c64xx_spi_port_config *port_conf;
206 unsigned int port_id;
2b908075 207 unsigned long gpios[4];
230d42d4
JB		 208};
209
210static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
211 .name = "samsung-spi-dma",
212};
213
214static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
215{
230d42d4
JB		 216 void __iomem *regs = sdd->regs;
217 unsigned long loops;
218 u32 val;
219
220 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
221
222 val = readl(regs + S3C64XX_SPI_CH_CFG);
223 val |= S3C64XX_SPI_CH_SW_RST;
224 val &= ~S3C64XX_SPI_CH_HS_EN;
225 writel(val, regs + S3C64XX_SPI_CH_CFG);
226
227 /* Flush TxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
a5238e36 231 } while (TX_FIFO_LVL(val, sdd) && loops--);
230d42d4 232
be7852a8
MB		 233 if (loops == 0)
234 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
235
230d42d4
JB		 236 /* Flush RxFIFO*/
237 loops = msecs_to_loops(1);
238 do {
239 val = readl(regs + S3C64XX_SPI_STATUS);
a5238e36 240 if (RX_FIFO_LVL(val, sdd))
230d42d4
JB		 241 readl(regs + S3C64XX_SPI_RX_DATA);
242 else
243 break;
244 } while (loops--);
245
be7852a8
MB		 246 if (loops == 0)
247 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
248
230d42d4
JB		 249 val = readl(regs + S3C64XX_SPI_CH_CFG);
250 val &= ~S3C64XX_SPI_CH_SW_RST;
251 writel(val, regs + S3C64XX_SPI_CH_CFG);
252
253 val = readl(regs + S3C64XX_SPI_MODE_CFG);
254 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
255 writel(val, regs + S3C64XX_SPI_MODE_CFG);
256
257 val = readl(regs + S3C64XX_SPI_CH_CFG);
258 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
259 writel(val, regs + S3C64XX_SPI_CH_CFG);
260}
261
82ab8cd7 262static void s3c64xx_spi_dmacb(void *data)
39d3e807 263{
82ab8cd7
BK		 264 struct s3c64xx_spi_driver_data *sdd;
265 struct s3c64xx_spi_dma_data *dma = data;
39d3e807
BK		 266 unsigned long flags;
267
054ebcc4 268 if (dma->direction == DMA_DEV_TO_MEM)
82ab8cd7
BK		 269 sdd = container_of(data,
270 struct s3c64xx_spi_driver_data, rx_dma);
271 else
272 sdd = container_of(data,
273 struct s3c64xx_spi_driver_data, tx_dma);
274
39d3e807
BK		 275 spin_lock_irqsave(&sdd->lock, flags);
276
054ebcc4 277 if (dma->direction == DMA_DEV_TO_MEM) {
82ab8cd7
BK		 278 sdd->state &= ~RXBUSY;
279 if (!(sdd->state & TXBUSY))
280 complete(&sdd->xfer_completion);
281 } else {
282 sdd->state &= ~TXBUSY;
283 if (!(sdd->state & RXBUSY))
284 complete(&sdd->xfer_completion);
285 }
39d3e807
BK		 286
287 spin_unlock_irqrestore(&sdd->lock, flags);
288}
289
82ab8cd7
BK		 290static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
291 unsigned len, dma_addr_t buf)
39d3e807 292{
82ab8cd7 293 struct s3c64xx_spi_driver_data *sdd;
4969c32b
BK		 294 struct samsung_dma_prep info;
295 struct samsung_dma_config config;
39d3e807 296
4969c32b 297 if (dma->direction == DMA_DEV_TO_MEM) {
82ab8cd7
BK		 298 sdd = container_of((void *)dma,
299 struct s3c64xx_spi_driver_data, rx_dma);
4969c32b
BK		 300 config.direction = sdd->rx_dma.direction;
301 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
302 config.width = sdd->cur_bpw / 8;
303 sdd->ops->config(sdd->rx_dma.ch, &config);
304 } else {
82ab8cd7
BK		 305 sdd = container_of((void *)dma,
306 struct s3c64xx_spi_driver_data, tx_dma);
4969c32b
BK		 307 config.direction = sdd->tx_dma.direction;
308 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
309 config.width = sdd->cur_bpw / 8;
310 sdd->ops->config(sdd->tx_dma.ch, &config);
311 }
39d3e807 312
82ab8cd7
BK		 313 info.cap = DMA_SLAVE;
314 info.len = len;
315 info.fp = s3c64xx_spi_dmacb;
316 info.fp_param = dma;
317 info.direction = dma->direction;
318 info.buf = buf;
319
320 sdd->ops->prepare(dma->ch, &info);
321 sdd->ops->trigger(dma->ch);
322}
39d3e807 323
82ab8cd7
BK		 324static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
325{
4969c32b 326 struct samsung_dma_req req;
82ab8cd7
BK		 327
328 sdd->ops = samsung_dma_get_ops();
329
4969c32b
BK		 330 req.cap = DMA_SLAVE;
331 req.client = &s3c64xx_spi_dma_client;
332
2b908075 333 req.dt_dmach_prop = sdd->rx_dma.dma_prop;
4969c32b 334 sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req);
2b908075 335 req.dt_dmach_prop = sdd->tx_dma.dma_prop;
4969c32b 336 sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req);
82ab8cd7
BK		 337
338 return 1;
39d3e807
BK		 339}
340
230d42d4
JB		 341static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
342 struct spi_device *spi,
343 struct spi_transfer *xfer, int dma_mode)
344{
230d42d4
JB		 345 void __iomem *regs = sdd->regs;
346 u32 modecfg, chcfg;
347
348 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
349 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
350
351 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
352 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
353
354 if (dma_mode) {
355 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
356 } else {
357 /* Always shift in data in FIFO, even if xfer is Tx only,
358 * this helps setting PCKT_CNT value for generating clocks
359 * as exactly needed.
360 */
361 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
362 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
363 | S3C64XX_SPI_PACKET_CNT_EN,
364 regs + S3C64XX_SPI_PACKET_CNT);
365 }
366
367 if (xfer->tx_buf != NULL) {
368 sdd->state |= TXBUSY;
369 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
370 if (dma_mode) {
371 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
82ab8cd7 372 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
230d42d4 373 } else {
0c92ecf1
JB		 374 switch (sdd->cur_bpw) {
375 case 32:
376 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
377 xfer->tx_buf, xfer->len / 4);
378 break;
379 case 16:
380 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
381 xfer->tx_buf, xfer->len / 2);
382 break;
383 default:
384 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
385 xfer->tx_buf, xfer->len);
386 break;
387 }
230d42d4
JB		 388 }
389 }
390
391 if (xfer->rx_buf != NULL) {
392 sdd->state |= RXBUSY;
393
a5238e36 394 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
230d42d4
JB		 395 && !(sdd->cur_mode & SPI_CPHA))
396 chcfg |= S3C64XX_SPI_CH_HS_EN;
397
398 if (dma_mode) {
399 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
400 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
401 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
402 | S3C64XX_SPI_PACKET_CNT_EN,
403 regs + S3C64XX_SPI_PACKET_CNT);
82ab8cd7 404 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
230d42d4
JB		 405 }
406 }
407
408 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
409 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
410}
411
412static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
413 struct spi_device *spi)
414{
415 struct s3c64xx_spi_csinfo *cs;
416
417 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
418 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
419 /* Deselect the last toggled device */
420 cs = sdd->tgl_spi->controller_data;
1c20c200
TA		 421 gpio_set_value(cs->line,
422 spi->mode & SPI_CS_HIGH ? 0 : 1);
230d42d4
JB		 423 }
424 sdd->tgl_spi = NULL;
425 }
426
427 cs = spi->controller_data;
1c20c200 428 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
230d42d4
JB		 429}
430
431static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
432 struct spi_transfer *xfer, int dma_mode)
433{
230d42d4
JB		 434 void __iomem *regs = sdd->regs;
435 unsigned long val;
436 int ms;
437
438 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
439 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
9d8f86b5 440 ms += 10; /* some tolerance */
230d42d4
JB		 441
442 if (dma_mode) {
443 val = msecs_to_jiffies(ms) + 10;
444 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
445 } else {
c3f139b6 446 u32 status;
230d42d4
JB		 447 val = msecs_to_loops(ms);
448 do {
c3f139b6 449 status = readl(regs + S3C64XX_SPI_STATUS);
a5238e36 450 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
230d42d4
JB		 451 }
452
453 if (!val)
454 return -EIO;
455
456 if (dma_mode) {
457 u32 status;
458
459 /*
460 * DmaTx returns after simply writing data in the FIFO,
461 * w/o waiting for real transmission on the bus to finish.
462 * DmaRx returns only after Dma read data from FIFO which
463 * needs bus transmission to finish, so we don't worry if
464 * Xfer involved Rx(with or without Tx).
465 */
466 if (xfer->rx_buf == NULL) {
467 val = msecs_to_loops(10);
468 status = readl(regs + S3C64XX_SPI_STATUS);
a5238e36
TA		 469 while ((TX_FIFO_LVL(status, sdd)
470 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
230d42d4
JB		 471 && --val) {
472 cpu_relax();
473 status = readl(regs + S3C64XX_SPI_STATUS);
474 }
475
476 if (!val)
477 return -EIO;
478 }
479 } else {
230d42d4
JB		 480 /* If it was only Tx */
481 if (xfer->rx_buf == NULL) {
482 sdd->state &= ~TXBUSY;
483 return 0;
484 }
485
0c92ecf1
JB		 486 switch (sdd->cur_bpw) {
487 case 32:
488 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
489 xfer->rx_buf, xfer->len / 4);
490 break;
491 case 16:
492 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
493 xfer->rx_buf, xfer->len / 2);
494 break;
495 default:
496 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
497 xfer->rx_buf, xfer->len);
498 break;
499 }
230d42d4
JB		 500 sdd->state &= ~RXBUSY;
501 }
502
503 return 0;
504}
505
506static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
507 struct spi_device *spi)
508{
509 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
510
511 if (sdd->tgl_spi == spi)
512 sdd->tgl_spi = NULL;
513
1c20c200 514 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
230d42d4
JB		 515}
516
517static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
518{
230d42d4
JB		 519 void __iomem *regs = sdd->regs;
520 u32 val;
521
522 /* Disable Clock */
a5238e36 523 if (sdd->port_conf->clk_from_cmu) {
b42a81ca
JB		 524 clk_disable(sdd->src_clk);
525 } else {
526 val = readl(regs + S3C64XX_SPI_CLK_CFG);
527 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
528 writel(val, regs + S3C64XX_SPI_CLK_CFG);
529 }
230d42d4
JB		 530
531 /* Set Polarity and Phase */
532 val = readl(regs + S3C64XX_SPI_CH_CFG);
533 val &= ~(S3C64XX_SPI_CH_SLAVE |
534 S3C64XX_SPI_CPOL_L |
535 S3C64XX_SPI_CPHA_B);
536
537 if (sdd->cur_mode & SPI_CPOL)
538 val |= S3C64XX_SPI_CPOL_L;
539
540 if (sdd->cur_mode & SPI_CPHA)
541 val |= S3C64XX_SPI_CPHA_B;
542
543 writel(val, regs + S3C64XX_SPI_CH_CFG);
544
545 /* Set Channel & DMA Mode */
546 val = readl(regs + S3C64XX_SPI_MODE_CFG);
547 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
548 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
549
550 switch (sdd->cur_bpw) {
551 case 32:
552 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
0c92ecf1 553 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
230d42d4
JB		 554 break;
555 case 16:
556 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
0c92ecf1 557 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
230d42d4
JB		 558 break;
559 default:
560 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
0c92ecf1 561 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
230d42d4
JB		 562 break;
563 }
230d42d4
JB		 564
565 writel(val, regs + S3C64XX_SPI_MODE_CFG);
566
a5238e36 567 if (sdd->port_conf->clk_from_cmu) {
b42a81ca
JB		 568 /* Configure Clock */
569 /* There is half-multiplier before the SPI */
570 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
571 /* Enable Clock */
572 clk_enable(sdd->src_clk);
573 } else {
574 /* Configure Clock */
575 val = readl(regs + S3C64XX_SPI_CLK_CFG);
576 val &= ~S3C64XX_SPI_PSR_MASK;
577 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
578 & S3C64XX_SPI_PSR_MASK);
579 writel(val, regs + S3C64XX_SPI_CLK_CFG);
580
581 /* Enable Clock */
582 val = readl(regs + S3C64XX_SPI_CLK_CFG);
583 val |= S3C64XX_SPI_ENCLK_ENABLE;
584 writel(val, regs + S3C64XX_SPI_CLK_CFG);
585 }
230d42d4
JB		 586}
587
230d42d4
JB		 588#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
589
590static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
591 struct spi_message *msg)
592{
593 struct device *dev = &sdd->pdev->dev;
594 struct spi_transfer *xfer;
595
596 if (msg->is_dma_mapped)
597 return 0;
598
599 /* First mark all xfer unmapped */
600 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
601 xfer->rx_dma = XFER_DMAADDR_INVALID;
602 xfer->tx_dma = XFER_DMAADDR_INVALID;
603 }
604
605 /* Map until end or first fail */
606 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
607
a5238e36 608 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
e02ddd44
JB		 609 continue;
610
230d42d4 611 if (xfer->tx_buf != NULL) {
251ee478
JB		 612 xfer->tx_dma = dma_map_single(dev,
613 (void *)xfer->tx_buf, xfer->len,
614 DMA_TO_DEVICE);
230d42d4
JB		 615 if (dma_mapping_error(dev, xfer->tx_dma)) {
616 dev_err(dev, "dma_map_single Tx failed\n");
617 xfer->tx_dma = XFER_DMAADDR_INVALID;
618 return -ENOMEM;
619 }
620 }
621
622 if (xfer->rx_buf != NULL) {
623 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
624 xfer->len, DMA_FROM_DEVICE);
625 if (dma_mapping_error(dev, xfer->rx_dma)) {
626 dev_err(dev, "dma_map_single Rx failed\n");
627 dma_unmap_single(dev, xfer->tx_dma,
628 xfer->len, DMA_TO_DEVICE);
629 xfer->tx_dma = XFER_DMAADDR_INVALID;
630 xfer->rx_dma = XFER_DMAADDR_INVALID;
631 return -ENOMEM;
632 }
633 }
634 }
635
636 return 0;
637}
638
639static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
640 struct spi_message *msg)
641{
642 struct device *dev = &sdd->pdev->dev;
643 struct spi_transfer *xfer;
644
645 if (msg->is_dma_mapped)
646 return;
647
648 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
649
a5238e36 650 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
e02ddd44
JB		 651 continue;
652
230d42d4
JB		 653 if (xfer->rx_buf != NULL
654 && xfer->rx_dma != XFER_DMAADDR_INVALID)
655 dma_unmap_single(dev, xfer->rx_dma,
656 xfer->len, DMA_FROM_DEVICE);
657
658 if (xfer->tx_buf != NULL
659 && xfer->tx_dma != XFER_DMAADDR_INVALID)
660 dma_unmap_single(dev, xfer->tx_dma,
661 xfer->len, DMA_TO_DEVICE);
662 }
663}
664
ad2a99af
MB		 665static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
666 struct spi_message *msg)
230d42d4 667{
ad2a99af 668 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
230d42d4
JB		 669 struct spi_device *spi = msg->spi;
670 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
671 struct spi_transfer *xfer;
672 int status = 0, cs_toggle = 0;
673 u32 speed;
674 u8 bpw;
675
676 /* If Master's(controller) state differs from that needed by Slave */
677 if (sdd->cur_speed != spi->max_speed_hz
678 || sdd->cur_mode != spi->mode
679 || sdd->cur_bpw != spi->bits_per_word) {
680 sdd->cur_bpw = spi->bits_per_word;
681 sdd->cur_speed = spi->max_speed_hz;
682 sdd->cur_mode = spi->mode;
683 s3c64xx_spi_config(sdd);
684 }
685
686 /* Map all the transfers if needed */
687 if (s3c64xx_spi_map_mssg(sdd, msg)) {
688 dev_err(&spi->dev,
689 "Xfer: Unable to map message buffers!\n");
690 status = -ENOMEM;
691 goto out;
692 }
693
694 /* Configure feedback delay */
695 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
696
697 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
698
699 unsigned long flags;
700 int use_dma;
701
702 INIT_COMPLETION(sdd->xfer_completion);
703
704 /* Only BPW and Speed may change across transfers */
705 bpw = xfer->bits_per_word ? : spi->bits_per_word;
706 speed = xfer->speed_hz ? : spi->max_speed_hz;
707
0c92ecf1
JB		 708 if (xfer->len % (bpw / 8)) {
709 dev_err(&spi->dev,
710 "Xfer length(%u) not a multiple of word size(%u)\n",
711 xfer->len, bpw / 8);
712 status = -EIO;
713 goto out;
714 }
715
230d42d4
JB		 716 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
717 sdd->cur_bpw = bpw;
718 sdd->cur_speed = speed;
719 s3c64xx_spi_config(sdd);
720 }
721
722 /* Polling method for xfers not bigger than FIFO capacity */
a5238e36 723 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
230d42d4
JB		 724 use_dma = 0;
725 else
726 use_dma = 1;
727
728 spin_lock_irqsave(&sdd->lock, flags);
729
730 /* Pending only which is to be done */
731 sdd->state &= ~RXBUSY;
732 sdd->state &= ~TXBUSY;
733
734 enable_datapath(sdd, spi, xfer, use_dma);
735
736 /* Slave Select */
737 enable_cs(sdd, spi);
738
739 /* Start the signals */
740 S3C64XX_SPI_ACT(sdd);
741
742 spin_unlock_irqrestore(&sdd->lock, flags);
743
744 status = wait_for_xfer(sdd, xfer, use_dma);
745
746 /* Quiese the signals */
747 S3C64XX_SPI_DEACT(sdd);
748
749 if (status) {
8a349d4b
JP		 750 dev_err(&spi->dev, "I/O Error: "
751 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
230d42d4
JB		 752 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
753 (sdd->state & RXBUSY) ? 'f' : 'p',
754 (sdd->state & TXBUSY) ? 'f' : 'p',
755 xfer->len);
756
757 if (use_dma) {
758 if (xfer->tx_buf != NULL
759 && (sdd->state & TXBUSY))
82ab8cd7 760 sdd->ops->stop(sdd->tx_dma.ch);
230d42d4
JB		 761 if (xfer->rx_buf != NULL
762 && (sdd->state & RXBUSY))
82ab8cd7 763 sdd->ops->stop(sdd->rx_dma.ch);
230d42d4
JB		 764 }
765
766 goto out;
767 }
768
769 if (xfer->delay_usecs)
770 udelay(xfer->delay_usecs);
771
772 if (xfer->cs_change) {
773 /* Hint that the next mssg is gonna be
774 for the same device */
775 if (list_is_last(&xfer->transfer_list,
776 &msg->transfers))
777 cs_toggle = 1;
778 else
779 disable_cs(sdd, spi);
780 }
781
782 msg->actual_length += xfer->len;
783
784 flush_fifo(sdd);
785 }
786
787out:
788 if (!cs_toggle || status)
789 disable_cs(sdd, spi);
790 else
791 sdd->tgl_spi = spi;
792
793 s3c64xx_spi_unmap_mssg(sdd, msg);
794
795 msg->status = status;
796
ad2a99af
MB		 797 spi_finalize_current_message(master);
798
799 return 0;
230d42d4
JB		 800}
801
ad2a99af 802static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
230d42d4 803{
ad2a99af 804 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
230d42d4
JB		 805
806 /* Acquire DMA channels */
807 while (!acquire_dma(sdd))
808 msleep(10);
809
b97b6621
MB		 810 pm_runtime_get_sync(&sdd->pdev->dev);
811
ad2a99af
MB		 812 return 0;
813}
230d42d4 814
ad2a99af
MB		 815static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
816{
817 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
230d42d4
JB		 818
819 /* Free DMA channels */
82ab8cd7
BK		 820 sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
821 sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
b97b6621
MB		 822
823 pm_runtime_put(&sdd->pdev->dev);
230d42d4
JB		 824
825 return 0;
826}
827
2b908075
TA		 828static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
829 struct s3c64xx_spi_driver_data *sdd,
830 struct spi_device *spi)
831{
832 struct s3c64xx_spi_csinfo *cs;
833 struct device_node *slave_np, *data_np;
834 u32 fb_delay = 0;
835
836 slave_np = spi->dev.of_node;
837 if (!slave_np) {
838 dev_err(&spi->dev, "device node not found\n");
839 return ERR_PTR(-EINVAL);
840 }
841
842 for_each_child_of_node(slave_np, data_np)
843 if (!strcmp(data_np->name, "controller-data"))
844 break;
845 if (!data_np) {
846 dev_err(&spi->dev, "child node 'controller-data' not found\n");
847 return ERR_PTR(-EINVAL);
848 }
849
850 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
851 if (!cs) {
852 dev_err(&spi->dev, "could not allocate memory for controller"
853 " data\n");
854 return ERR_PTR(-ENOMEM);
855 }
856
857 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
858 if (!gpio_is_valid(cs->line)) {
859 dev_err(&spi->dev, "chip select gpio is not specified or "
860 "invalid\n");
861 kfree(cs);
862 return ERR_PTR(-EINVAL);
863 }
864
865 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
866 cs->fb_delay = fb_delay;
867 return cs;
868}
869
230d42d4
JB		 870/*
871 * Here we only check the validity of requested configuration
872 * and save the configuration in a local data-structure.
873 * The controller is actually configured only just before we
874 * get a message to transfer.
875 */
876static int s3c64xx_spi_setup(struct spi_device *spi)
877{
878 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
879 struct s3c64xx_spi_driver_data *sdd;
ad7de729 880 struct s3c64xx_spi_info *sci;
230d42d4 881 struct spi_message *msg;
230d42d4 882 unsigned long flags;
2b908075 883 int err;
230d42d4 884
2b908075
TA		 885 sdd = spi_master_get_devdata(spi->master);
886 if (!cs && spi->dev.of_node) {
887 cs = s3c64xx_get_slave_ctrldata(sdd, spi);
888 spi->controller_data = cs;
889 }
890
891 if (IS_ERR_OR_NULL(cs)) {
230d42d4
JB		 892 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
893 return -ENODEV;
894 }
895
1c20c200
TA		 896 if (!spi_get_ctldata(spi)) {
897 err = gpio_request(cs->line, dev_name(&spi->dev));
898 if (err) {
899 dev_err(&spi->dev, "request for slave select gpio "
900 "line [%d] failed\n", cs->line);
2b908075
TA		 901 err = -EBUSY;
902 goto err_gpio_req;
1c20c200
TA		 903 }
904 spi_set_ctldata(spi, cs);
905 }
906
230d42d4
JB		 907 sci = sdd->cntrlr_info;
908
909 spin_lock_irqsave(&sdd->lock, flags);
910
911 list_for_each_entry(msg, &sdd->queue, queue) {
912 /* Is some mssg is already queued for this device */
913 if (msg->spi == spi) {
914 dev_err(&spi->dev,
915 "setup: attempt while mssg in queue!\n");
916 spin_unlock_irqrestore(&sdd->lock, flags);
2b908075
TA		 917 err = -EBUSY;
918 goto err_msgq;
230d42d4
JB		 919 }
920 }
921
230d42d4
JB		 922 spin_unlock_irqrestore(&sdd->lock, flags);
923
924 if (spi->bits_per_word != 8
925 && spi->bits_per_word != 16
926 && spi->bits_per_word != 32) {
927 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
928 spi->bits_per_word);
929 err = -EINVAL;
930 goto setup_exit;
931 }
932
b97b6621
MB		 933 pm_runtime_get_sync(&sdd->pdev->dev);
934
230d42d4 935 /* Check if we can provide the requested rate */
a5238e36 936 if (!sdd->port_conf->clk_from_cmu) {
b42a81ca
JB		 937 u32 psr, speed;
938
939 /* Max possible */
940 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
941
942 if (spi->max_speed_hz > speed)
943 spi->max_speed_hz = speed;
944
945 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
946 psr &= S3C64XX_SPI_PSR_MASK;
947 if (psr == S3C64XX_SPI_PSR_MASK)
948 psr--;
949
950 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
951 if (spi->max_speed_hz < speed) {
952 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
953 psr++;
954 } else {
955 err = -EINVAL;
956 goto setup_exit;
957 }
958 }
230d42d4 959
b42a81ca 960 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
2b908075 961 if (spi->max_speed_hz >= speed) {
b42a81ca 962 spi->max_speed_hz = speed;
2b908075 963 } else {
230d42d4 964 err = -EINVAL;
2b908075
TA		 965 goto setup_exit;
966 }
230d42d4
JB		 967 }
968
b97b6621 969 pm_runtime_put(&sdd->pdev->dev);
2b908075
TA		 970 disable_cs(sdd, spi);
971 return 0;
b97b6621 972
230d42d4 973setup_exit:
230d42d4
JB		 974 /* setup() returns with device de-selected */
975 disable_cs(sdd, spi);
976
2b908075
TA		 977err_msgq:
978 gpio_free(cs->line);
979 spi_set_ctldata(spi, NULL);
980
981err_gpio_req:
982 kfree(cs);
983
230d42d4
JB		 984 return err;
985}
986
1c20c200
TA		 987static void s3c64xx_spi_cleanup(struct spi_device *spi)
988{
989 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
990
2b908075 991 if (cs) {
1c20c200 992 gpio_free(cs->line);
2b908075
TA		 993 if (spi->dev.of_node)
994 kfree(cs);
995 }
1c20c200
TA		 996 spi_set_ctldata(spi, NULL);
997}
998
c2573128
MB		 999static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1000{
1001 struct s3c64xx_spi_driver_data *sdd = data;
1002 struct spi_master *spi = sdd->master;
1003 unsigned int val;
1004
1005 val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
1006
1007 val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1008 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1009 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1010 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1011
1012 writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1013
1014 if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
1015 dev_err(&spi->dev, "RX overrun\n");
1016 if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
1017 dev_err(&spi->dev, "RX underrun\n");
1018 if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
1019 dev_err(&spi->dev, "TX overrun\n");
1020 if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
1021 dev_err(&spi->dev, "TX underrun\n");
1022
1023 return IRQ_HANDLED;
1024}
1025
230d42d4
JB		 1026static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1027{
ad7de729 1028 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 1029 void __iomem *regs = sdd->regs;
1030 unsigned int val;
1031
1032 sdd->cur_speed = 0;
1033
1034 S3C64XX_SPI_DEACT(sdd);
1035
1036 /* Disable Interrupts - we use Polling if not DMA mode */
1037 writel(0, regs + S3C64XX_SPI_INT_EN);
1038
a5238e36 1039 if (!sdd->port_conf->clk_from_cmu)
b42a81ca 1040 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
230d42d4
JB		 1041 regs + S3C64XX_SPI_CLK_CFG);
1042 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1043 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1044
1045 /* Clear any irq pending bits */
1046 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
1047 regs + S3C64XX_SPI_PENDING_CLR);
1048
1049 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1050
1051 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1052 val &= ~S3C64XX_SPI_MODE_4BURST;
1053 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1054 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1055 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1056
1057 flush_fifo(sdd);
1058}
1059
2b908075
TA		 1060static int __devinit s3c64xx_spi_get_dmares(
1061 struct s3c64xx_spi_driver_data *sdd, bool tx)
1062{
1063 struct platform_device *pdev = sdd->pdev;
1064 struct s3c64xx_spi_dma_data *dma_data;
1065 struct property *prop;
1066 struct resource *res;
1067 char prop_name[15], *chan_str;
1068
1069 if (tx) {
1070 dma_data = &sdd->tx_dma;
1071 dma_data->direction = DMA_TO_DEVICE;
1072 chan_str = "tx";
1073 } else {
1074 dma_data = &sdd->rx_dma;
1075 dma_data->direction = DMA_FROM_DEVICE;
1076 chan_str = "rx";
1077 }
1078
1079 if (!sdd->pdev->dev.of_node) {
1080 res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
1081 if (!res) {
1082 dev_err(&pdev->dev, "Unable to get SPI-%s dma "
1083 "resource\n", chan_str);
1084 return -ENXIO;
1085 }
1086 dma_data->dmach = res->start;
1087 return 0;
1088 }
1089
1090 sprintf(prop_name, "%s-dma-channel", chan_str);
1091 prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
1092 if (!prop) {
1093 dev_err(&pdev->dev, "%s dma channel property not specified\n",
1094 chan_str);
1095 return -ENXIO;
1096 }
1097
1098 dma_data->dmach = DMACH_DT_PROP;
1099 dma_data->dma_prop = prop;
1100 return 0;
1101}
1102
1103#ifdef CONFIG_OF
1104static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1105{
1106 struct device *dev = &sdd->pdev->dev;
1107 int idx, gpio, ret;
1108
1109 /* find gpios for mosi, miso and clock lines */
1110 for (idx = 0; idx < 3; idx++) {
1111 gpio = of_get_gpio(dev->of_node, idx);
1112 if (!gpio_is_valid(gpio)) {
1113 dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
1114 goto free_gpio;
1115 }
1116
1117 ret = gpio_request(gpio, "spi-bus");
1118 if (ret) {
1119 dev_err(dev, "gpio [%d] request failed\n", gpio);
1120 goto free_gpio;
1121 }
1122 }
1123 return 0;
1124
1125free_gpio:
1126 while (--idx >= 0)
1127 gpio_free(sdd->gpios[idx]);
1128 return -EINVAL;
1129}
1130
1131static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1132{
1133 unsigned int idx;
1134 for (idx = 0; idx < 3; idx++)
1135 gpio_free(sdd->gpios[idx]);
1136}
1137
1138static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
1139 struct device *dev)
1140{
1141 struct s3c64xx_spi_info *sci;
1142 u32 temp;
1143
1144 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1145 if (!sci) {
1146 dev_err(dev, "memory allocation for spi_info failed\n");
1147 return ERR_PTR(-ENOMEM);
1148 }
1149
1150 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1151 dev_warn(dev, "spi bus clock parent not specified, using "
1152 "clock at index 0 as parent\n");
1153 sci->src_clk_nr = 0;
1154 } else {
1155 sci->src_clk_nr = temp;
1156 }
1157
1158 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1159 dev_warn(dev, "number of chip select lines not specified, "
1160 "assuming 1 chip select line\n");
1161 sci->num_cs = 1;
1162 } else {
1163 sci->num_cs = temp;
1164 }
1165
1166 return sci;
1167}
1168#else
1169static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1170{
1171 return dev->platform_data;
1172}
1173
1174static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
1175{
1176 return -EINVAL;
1177}
1178
1179static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
1180{
1181}
1182#endif
1183
1184static const struct of_device_id s3c64xx_spi_dt_match[];
1185
a5238e36
TA		 1186static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1187 struct platform_device *pdev)
1188{
2b908075
TA		 1189#ifdef CONFIG_OF
1190 if (pdev->dev.of_node) {
1191 const struct of_device_id *match;
1192 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1193 return (struct s3c64xx_spi_port_config *)match->data;
1194 }
1195#endif
a5238e36
TA		 1196 return (struct s3c64xx_spi_port_config *)
1197 platform_get_device_id(pdev)->driver_data;
1198}
1199
230d42d4
JB		 1200static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1201{
2b908075 1202 struct resource *mem_res;
230d42d4 1203 struct s3c64xx_spi_driver_data *sdd;
2b908075 1204 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
230d42d4 1205 struct spi_master *master;
c2573128 1206 int ret, irq;
a24d850b 1207 char clk_name[16];
230d42d4 1208
2b908075
TA		 1209 if (!sci && pdev->dev.of_node) {
1210 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1211 if (IS_ERR(sci))
1212 return PTR_ERR(sci);
230d42d4
JB		 1213 }
1214
2b908075 1215 if (!sci) {
230d42d4
JB		 1216 dev_err(&pdev->dev, "platform_data missing!\n");
1217 return -ENODEV;
1218 }
1219
230d42d4
JB		 1220 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1221 if (mem_res == NULL) {
1222 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1223 return -ENXIO;
1224 }
1225
c2573128
MB		 1226 irq = platform_get_irq(pdev, 0);
1227 if (irq < 0) {
1228 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1229 return irq;
1230 }
1231
230d42d4
JB		 1232 master = spi_alloc_master(&pdev->dev,
1233 sizeof(struct s3c64xx_spi_driver_data));
1234 if (master == NULL) {
1235 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1236 return -ENOMEM;
1237 }
1238
230d42d4
JB		 1239 platform_set_drvdata(pdev, master);
1240
1241 sdd = spi_master_get_devdata(master);
a5238e36 1242 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
230d42d4
JB		 1243 sdd->master = master;
1244 sdd->cntrlr_info = sci;
1245 sdd->pdev = pdev;
1246 sdd->sfr_start = mem_res->start;
2b908075
TA		 1247 if (pdev->dev.of_node) {
1248 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1249 if (ret < 0) {
1250 dev_err(&pdev->dev, "failed to get alias id, "
1251 "errno %d\n", ret);
1252 goto err0;
1253 }
1254 sdd->port_id = ret;
1255 } else {
1256 sdd->port_id = pdev->id;
1257 }
230d42d4
JB		 1258
1259 sdd->cur_bpw = 8;
1260
2b908075
TA		 1261 ret = s3c64xx_spi_get_dmares(sdd, true);
1262 if (ret)
1263 goto err0;
1264
1265 ret = s3c64xx_spi_get_dmares(sdd, false);
1266 if (ret)
1267 goto err0;
1268
1269 master->dev.of_node = pdev->dev.of_node;
a5238e36 1270 master->bus_num = sdd->port_id;
230d42d4 1271 master->setup = s3c64xx_spi_setup;
1c20c200 1272 master->cleanup = s3c64xx_spi_cleanup;
ad2a99af
MB		 1273 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1274 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1275 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
230d42d4
JB		 1276 master->num_chipselect = sci->num_cs;
1277 master->dma_alignment = 8;
1278 /* the spi->mode bits understood by this driver: */
1279 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1280
1281 if (request_mem_region(mem_res->start,
1282 resource_size(mem_res), pdev->name) == NULL) {
1283 dev_err(&pdev->dev, "Req mem region failed\n");
1284 ret = -ENXIO;
1285 goto err0;
1286 }
1287
1288 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1289 if (sdd->regs == NULL) {
1290 dev_err(&pdev->dev, "Unable to remap IO\n");
1291 ret = -ENXIO;
1292 goto err1;
1293 }
1294
2b908075
TA		 1295 if (!sci->cfg_gpio && pdev->dev.of_node) {
1296 if (s3c64xx_spi_parse_dt_gpio(sdd))
1297 return -EBUSY;
1298 } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
230d42d4
JB		 1299 dev_err(&pdev->dev, "Unable to config gpio\n");
1300 ret = -EBUSY;
1301 goto err2;
1302 }
1303
1304 /* Setup clocks */
1305 sdd->clk = clk_get(&pdev->dev, "spi");
1306 if (IS_ERR(sdd->clk)) {
1307 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1308 ret = PTR_ERR(sdd->clk);
1309 goto err3;
1310 }
1311
1312 if (clk_enable(sdd->clk)) {
1313 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1314 ret = -EBUSY;
1315 goto err4;
1316 }
1317
a24d850b
PV		 1318 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1319 sdd->src_clk = clk_get(&pdev->dev, clk_name);
b0d5d6e5 1320 if (IS_ERR(sdd->src_clk)) {
230d42d4 1321 dev_err(&pdev->dev,
a24d850b 1322 "Unable to acquire clock '%s'\n", clk_name);
b0d5d6e5 1323 ret = PTR_ERR(sdd->src_clk);
230d42d4
JB		 1324 goto err5;
1325 }
1326
b0d5d6e5 1327 if (clk_enable(sdd->src_clk)) {
a24d850b 1328 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
230d42d4
JB		 1329 ret = -EBUSY;
1330 goto err6;
1331 }
1332
230d42d4 1333 /* Setup Deufult Mode */
a5238e36 1334 s3c64xx_spi_hwinit(sdd, sdd->port_id);
230d42d4
JB		 1335
1336 spin_lock_init(&sdd->lock);
1337 init_completion(&sdd->xfer_completion);
230d42d4
JB		 1338 INIT_LIST_HEAD(&sdd->queue);
1339
c2573128
MB		 1340 ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd);
1341 if (ret != 0) {
1342 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1343 irq, ret);
ad2a99af 1344 goto err7;
c2573128
MB		 1345 }
1346
1347 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1348 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1349 sdd->regs + S3C64XX_SPI_INT_EN);
1350
230d42d4
JB		 1351 if (spi_register_master(master)) {
1352 dev_err(&pdev->dev, "cannot register SPI master\n");
1353 ret = -EBUSY;
ad2a99af 1354 goto err8;
230d42d4
JB		 1355 }
1356
8a349d4b
JP		 1357 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1358 "with %d Slaves attached\n",
a5238e36 1359 sdd->port_id, master->num_chipselect);
8a349d4b 1360 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
230d42d4 1361 mem_res->end, mem_res->start,
82ab8cd7 1362 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
230d42d4 1363
b97b6621
MB		 1364 pm_runtime_enable(&pdev->dev);
1365
230d42d4
JB		 1366 return 0;
1367
1368err8:
ad2a99af 1369 free_irq(irq, sdd);
230d42d4 1370err7:
b0d5d6e5 1371 clk_disable(sdd->src_clk);
230d42d4 1372err6:
b0d5d6e5 1373 clk_put(sdd->src_clk);
230d42d4
JB		 1374err5:
1375 clk_disable(sdd->clk);
1376err4:
1377 clk_put(sdd->clk);
1378err3:
2b908075
TA		 1379 if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1380 s3c64xx_spi_dt_gpio_free(sdd);
230d42d4
JB		 1381err2:
1382 iounmap((void *) sdd->regs);
1383err1:
1384 release_mem_region(mem_res->start, resource_size(mem_res));
1385err0:
1386 platform_set_drvdata(pdev, NULL);
1387 spi_master_put(master);
1388
1389 return ret;
1390}
1391
1392static int s3c64xx_spi_remove(struct platform_device *pdev)
1393{
1394 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1395 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
230d42d4 1396 struct resource *mem_res;
230d42d4 1397
b97b6621
MB		 1398 pm_runtime_disable(&pdev->dev);
1399
230d42d4
JB		 1400 spi_unregister_master(master);
1401
c2573128
MB		 1402 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1403
1404 free_irq(platform_get_irq(pdev, 0), sdd);
1405
b0d5d6e5
JB		 1406 clk_disable(sdd->src_clk);
1407 clk_put(sdd->src_clk);
230d42d4
JB		 1408
1409 clk_disable(sdd->clk);
1410 clk_put(sdd->clk);
1411
2b908075
TA		 1412 if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
1413 s3c64xx_spi_dt_gpio_free(sdd);
1414
230d42d4
JB		 1415 iounmap((void *) sdd->regs);
1416
1417 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ef6c680d
JB		 1418 if (mem_res != NULL)
1419 release_mem_region(mem_res->start, resource_size(mem_res));
230d42d4
JB		 1420
1421 platform_set_drvdata(pdev, NULL);
1422 spi_master_put(master);
1423
1424 return 0;
1425}
1426
1427#ifdef CONFIG_PM
e25d0bf9 1428static int s3c64xx_spi_suspend(struct device *dev)
230d42d4 1429{
e25d0bf9 1430 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
230d42d4 1431 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
230d42d4 1432
ad2a99af 1433 spi_master_suspend(master);
230d42d4
JB		 1434
1435 /* Disable the clock */
b0d5d6e5 1436 clk_disable(sdd->src_clk);
230d42d4
JB		 1437 clk_disable(sdd->clk);
1438
2b908075
TA		 1439 if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
1440 s3c64xx_spi_dt_gpio_free(sdd);
1441
230d42d4
JB		 1442 sdd->cur_speed = 0; /* Output Clock is stopped */
1443
1444 return 0;
1445}
1446
e25d0bf9 1447static int s3c64xx_spi_resume(struct device *dev)
230d42d4 1448{
e25d0bf9 1449 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
230d42d4 1450 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
ad7de729 1451 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4 1452
2b908075
TA		 1453 if (!sci->cfg_gpio && dev->of_node)
1454 s3c64xx_spi_parse_dt_gpio(sdd);
1455 else
1456 sci->cfg_gpio();
230d42d4
JB		 1457
1458 /* Enable the clock */
b0d5d6e5 1459 clk_enable(sdd->src_clk);
230d42d4
JB		 1460 clk_enable(sdd->clk);
1461
a5238e36 1462 s3c64xx_spi_hwinit(sdd, sdd->port_id);
230d42d4 1463
ad2a99af 1464 spi_master_resume(master);
230d42d4
JB		 1465
1466 return 0;
1467}
230d42d4
JB		 1468#endif /* CONFIG_PM */
1469
b97b6621
MB		 1470#ifdef CONFIG_PM_RUNTIME
1471static int s3c64xx_spi_runtime_suspend(struct device *dev)
1472{
1473 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1474 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1475
1476 clk_disable(sdd->clk);
1477 clk_disable(sdd->src_clk);
1478
1479 return 0;
1480}
1481
1482static int s3c64xx_spi_runtime_resume(struct device *dev)
1483{
1484 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
1485 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1486
1487 clk_enable(sdd->src_clk);
1488 clk_enable(sdd->clk);
1489
1490 return 0;
1491}
1492#endif /* CONFIG_PM_RUNTIME */
1493
e25d0bf9
MB		 1494static const struct dev_pm_ops s3c64xx_spi_pm = {
1495 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
b97b6621
MB		 1496 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1497 s3c64xx_spi_runtime_resume, NULL)
e25d0bf9
MB		 1498};
1499
a5238e36
TA		 1500struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1501 .fifo_lvl_mask = { 0x7f },
1502 .rx_lvl_offset = 13,
1503 .tx_st_done = 21,
1504 .high_speed = true,
1505};
1506
1507struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1508 .fifo_lvl_mask = { 0x7f, 0x7F },
1509 .rx_lvl_offset = 13,
1510 .tx_st_done = 21,
1511};
1512
1513struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1514 .fifo_lvl_mask = { 0x1ff, 0x7F },
1515 .rx_lvl_offset = 15,
1516 .tx_st_done = 25,
1517};
1518
1519struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1520 .fifo_lvl_mask = { 0x7f, 0x7F },
1521 .rx_lvl_offset = 13,
1522 .tx_st_done = 21,
1523 .high_speed = true,
1524};
1525
1526struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1527 .fifo_lvl_mask = { 0x1ff, 0x7F },
1528 .rx_lvl_offset = 15,
1529 .tx_st_done = 25,
1530 .high_speed = true,
1531};
1532
1533struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1534 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1535 .rx_lvl_offset = 15,
1536 .tx_st_done = 25,
1537 .high_speed = true,
1538 .clk_from_cmu = true,
1539};
1540
1541static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1542 {
1543 .name = "s3c2443-spi",
1544 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1545 }, {
1546 .name = "s3c6410-spi",
1547 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1548 }, {
1549 .name = "s5p64x0-spi",
1550 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1551 }, {
1552 .name = "s5pc100-spi",
1553 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1554 }, {
1555 .name = "s5pv210-spi",
1556 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1557 }, {
1558 .name = "exynos4210-spi",
1559 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1560 },
1561 { },
1562};
1563
2b908075
TA		 1564#ifdef CONFIG_OF
1565static const struct of_device_id s3c64xx_spi_dt_match[] = {
1566 { .compatible = "samsung,exynos4210-spi",
1567 .data = (void *)&exynos4_spi_port_config,
1568 },
1569 { },
1570};
1571MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1572#endif /* CONFIG_OF */
1573
230d42d4
JB		 1574static struct platform_driver s3c64xx_spi_driver = {
1575 .driver = {
1576 .name = "s3c64xx-spi",
1577 .owner = THIS_MODULE,
e25d0bf9 1578 .pm = &s3c64xx_spi_pm,
2b908075 1579 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
230d42d4
JB		 1580 },
1581 .remove = s3c64xx_spi_remove,
a5238e36 1582 .id_table = s3c64xx_spi_driver_ids,
230d42d4
JB		 1583};
1584MODULE_ALIAS("platform:s3c64xx-spi");
1585
1586static int __init s3c64xx_spi_init(void)
1587{
1588 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1589}
d2a787fc 1590subsys_initcall(s3c64xx_spi_init);
230d42d4
JB		 1591
1592static void __exit s3c64xx_spi_exit(void)
1593{
1594 platform_driver_unregister(&s3c64xx_spi_driver);
1595}
1596module_exit(s3c64xx_spi_exit);
1597
1598MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1599MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1600MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.24614 seconds and 5 git commands to generate.