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d1c8bbd7 KM |
1 | /* |
2 | * SuperH HSPI bus driver | |
3 | * | |
4 | * Copyright (C) 2011 Kuninori Morimoto | |
5 | * | |
6 | * Based on spi-sh.c: | |
7 | * Based on pxa2xx_spi.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; version 2 of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
d1c8bbd7 | 19 | */ |
49e599b8 KM |
20 | |
21 | #include <linux/clk.h> | |
d1c8bbd7 KM |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/timer.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/list.h> | |
d1c8bbd7 KM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/spi/spi.h> | |
32 | #include <linux/spi/sh_hspi.h> | |
33 | ||
34 | #define SPCR 0x00 | |
35 | #define SPSR 0x04 | |
36 | #define SPSCR 0x08 | |
37 | #define SPTBR 0x0C | |
38 | #define SPRBR 0x10 | |
39 | #define SPCR2 0x14 | |
40 | ||
41 | /* SPSR */ | |
42 | #define RXFL (1 << 2) | |
43 | ||
d1c8bbd7 KM |
44 | struct hspi_priv { |
45 | void __iomem *addr; | |
46 | struct spi_master *master; | |
d1c8bbd7 | 47 | struct device *dev; |
49e599b8 | 48 | struct clk *clk; |
d1c8bbd7 KM |
49 | }; |
50 | ||
51 | /* | |
52 | * basic function | |
53 | */ | |
54 | static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) | |
55 | { | |
56 | iowrite32(val, hspi->addr + reg); | |
57 | } | |
58 | ||
59 | static u32 hspi_read(struct hspi_priv *hspi, int reg) | |
60 | { | |
61 | return ioread32(hspi->addr + reg); | |
62 | } | |
63 | ||
ce329305 PE |
64 | static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set) |
65 | { | |
66 | u32 val = hspi_read(hspi, reg); | |
67 | ||
68 | val &= ~mask; | |
69 | val |= set & mask; | |
70 | ||
71 | hspi_write(hspi, reg, val); | |
72 | } | |
73 | ||
d1c8bbd7 KM |
74 | /* |
75 | * transfer function | |
76 | */ | |
77 | static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) | |
78 | { | |
79 | int t = 256; | |
80 | ||
81 | while (t--) { | |
82 | if ((mask & hspi_read(hspi, SPSR)) == val) | |
83 | return 0; | |
84 | ||
bc2bfffc | 85 | udelay(10); |
d1c8bbd7 KM |
86 | } |
87 | ||
88 | dev_err(hspi->dev, "timeout\n"); | |
89 | return -ETIMEDOUT; | |
90 | } | |
91 | ||
ec139b67 KM |
92 | /* |
93 | * spi master function | |
94 | */ | |
d1c8bbd7 | 95 | |
ce329305 PE |
96 | #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0) |
97 | #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1) | |
98 | static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi) | |
99 | { | |
100 | hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6); | |
101 | } | |
102 | ||
49e599b8 KM |
103 | static void hspi_hw_setup(struct hspi_priv *hspi, |
104 | struct spi_message *msg, | |
105 | struct spi_transfer *t) | |
106 | { | |
107 | struct spi_device *spi = msg->spi; | |
108 | struct device *dev = hspi->dev; | |
49e599b8 KM |
109 | u32 spcr, idiv_clk; |
110 | u32 rate, best_rate, min, tmp; | |
111 | ||
49e599b8 KM |
112 | /* |
113 | * find best IDIV/CLKCx settings | |
114 | */ | |
115 | min = ~0; | |
116 | best_rate = 0; | |
117 | spcr = 0; | |
118 | for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) { | |
119 | rate = clk_get_rate(hspi->clk); | |
120 | ||
121 | /* IDIV calculation */ | |
122 | if (idiv_clk & (1 << 5)) | |
123 | rate /= 128; | |
124 | else | |
125 | rate /= 16; | |
126 | ||
127 | /* CLKCx calculation */ | |
a29c8ae7 | 128 | rate /= (((idiv_clk & 0x1F) + 1) * 2); |
49e599b8 KM |
129 | |
130 | /* save best settings */ | |
e428a420 | 131 | tmp = abs(t->speed_hz - rate); |
49e599b8 KM |
132 | if (tmp < min) { |
133 | min = tmp; | |
134 | spcr = idiv_clk; | |
135 | best_rate = rate; | |
136 | } | |
137 | } | |
138 | ||
139 | if (spi->mode & SPI_CPHA) | |
140 | spcr |= 1 << 7; | |
141 | if (spi->mode & SPI_CPOL) | |
142 | spcr |= 1 << 6; | |
143 | ||
e428a420 | 144 | dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate); |
49e599b8 KM |
145 | |
146 | hspi_write(hspi, SPCR, spcr); | |
147 | hspi_write(hspi, SPSR, 0x0); | |
ce329305 | 148 | hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */ |
49e599b8 KM |
149 | } |
150 | ||
ec139b67 KM |
151 | static int hspi_transfer_one_message(struct spi_master *master, |
152 | struct spi_message *msg) | |
153 | { | |
154 | struct hspi_priv *hspi = spi_master_get_devdata(master); | |
155 | struct spi_transfer *t; | |
bb9c5687 KM |
156 | u32 tx; |
157 | u32 rx; | |
158 | int ret, i; | |
ce329305 PE |
159 | unsigned int cs_change; |
160 | const int nsecs = 50; | |
d1c8bbd7 | 161 | |
ec139b67 | 162 | dev_dbg(hspi->dev, "%s\n", __func__); |
d1c8bbd7 | 163 | |
ce329305 | 164 | cs_change = 1; |
ec139b67 KM |
165 | ret = 0; |
166 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
ce329305 PE |
167 | |
168 | if (cs_change) { | |
169 | hspi_hw_setup(hspi, msg, t); | |
170 | hspi_hw_cs_enable(hspi); | |
171 | ndelay(nsecs); | |
172 | } | |
173 | cs_change = t->cs_change; | |
49e599b8 | 174 | |
bb9c5687 KM |
175 | for (i = 0; i < t->len; i++) { |
176 | ||
177 | /* wait remains */ | |
178 | ret = hspi_status_check_timeout(hspi, 0x1, 0); | |
ec139b67 | 179 | if (ret < 0) |
bb9c5687 KM |
180 | break; |
181 | ||
182 | tx = 0; | |
183 | if (t->tx_buf) | |
184 | tx = (u32)((u8 *)t->tx_buf)[i]; | |
185 | ||
186 | hspi_write(hspi, SPTBR, tx); | |
187 | ||
c6c07b4f | 188 | /* wait receive */ |
bb9c5687 | 189 | ret = hspi_status_check_timeout(hspi, 0x4, 0x4); |
ec139b67 | 190 | if (ret < 0) |
bb9c5687 KM |
191 | break; |
192 | ||
193 | rx = hspi_read(hspi, SPRBR); | |
194 | if (t->rx_buf) | |
195 | ((u8 *)t->rx_buf)[i] = (u8)rx; | |
196 | ||
d1c8bbd7 | 197 | } |
bb9c5687 | 198 | |
ec139b67 | 199 | msg->actual_length += t->len; |
ce329305 PE |
200 | |
201 | if (t->delay_usecs) | |
202 | udelay(t->delay_usecs); | |
203 | ||
204 | if (cs_change) { | |
205 | ndelay(nsecs); | |
206 | hspi_hw_cs_disable(hspi); | |
207 | ndelay(nsecs); | |
208 | } | |
d1c8bbd7 KM |
209 | } |
210 | ||
ec139b67 | 211 | msg->status = ret; |
ce329305 PE |
212 | if (!cs_change) { |
213 | ndelay(nsecs); | |
214 | hspi_hw_cs_disable(hspi); | |
215 | } | |
ec139b67 | 216 | spi_finalize_current_message(master); |
d1c8bbd7 | 217 | |
ec139b67 | 218 | return ret; |
d1c8bbd7 KM |
219 | } |
220 | ||
fd4a319b | 221 | static int hspi_probe(struct platform_device *pdev) |
d1c8bbd7 KM |
222 | { |
223 | struct resource *res; | |
224 | struct spi_master *master; | |
225 | struct hspi_priv *hspi; | |
49e599b8 | 226 | struct clk *clk; |
d1c8bbd7 KM |
227 | int ret; |
228 | ||
229 | /* get base addr */ | |
230 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
231 | if (!res) { | |
232 | dev_err(&pdev->dev, "invalid resource\n"); | |
233 | return -EINVAL; | |
234 | } | |
235 | ||
236 | master = spi_alloc_master(&pdev->dev, sizeof(*hspi)); | |
237 | if (!master) { | |
238 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
239 | return -ENOMEM; | |
240 | } | |
241 | ||
4a4dd7d8 | 242 | clk = clk_get(&pdev->dev, NULL); |
d3601e56 | 243 | if (IS_ERR(clk)) { |
4a4dd7d8 | 244 | dev_err(&pdev->dev, "couldn't get clock\n"); |
49e599b8 KM |
245 | ret = -EINVAL; |
246 | goto error0; | |
247 | } | |
248 | ||
d1c8bbd7 | 249 | hspi = spi_master_get_devdata(master); |
24b5a82c | 250 | platform_set_drvdata(pdev, hspi); |
d1c8bbd7 KM |
251 | |
252 | /* init hspi */ | |
253 | hspi->master = master; | |
254 | hspi->dev = &pdev->dev; | |
49e599b8 | 255 | hspi->clk = clk; |
d1c8bbd7 KM |
256 | hspi->addr = devm_ioremap(hspi->dev, |
257 | res->start, resource_size(res)); | |
258 | if (!hspi->addr) { | |
259 | dev_err(&pdev->dev, "ioremap error.\n"); | |
260 | ret = -ENOMEM; | |
261 | goto error1; | |
262 | } | |
d1c8bbd7 | 263 | |
268d7643 KM |
264 | pm_runtime_enable(&pdev->dev); |
265 | ||
d1c8bbd7 | 266 | master->bus_num = pdev->id; |
d1c8bbd7 | 267 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
e5f7825c | 268 | master->dev.of_node = pdev->dev.of_node; |
3e00a09d | 269 | master->auto_runtime_pm = true; |
ec139b67 | 270 | master->transfer_one_message = hspi_transfer_one_message; |
45221936 AL |
271 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
272 | ||
1c43f2ae | 273 | ret = devm_spi_register_master(&pdev->dev, master); |
d1c8bbd7 KM |
274 | if (ret < 0) { |
275 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
3abf0edd | 276 | goto error2; |
d1c8bbd7 KM |
277 | } |
278 | ||
d1c8bbd7 KM |
279 | return 0; |
280 | ||
3abf0edd GU |
281 | error2: |
282 | pm_runtime_disable(&pdev->dev); | |
d1c8bbd7 | 283 | error1: |
49e599b8 KM |
284 | clk_put(clk); |
285 | error0: | |
d1c8bbd7 KM |
286 | spi_master_put(master); |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
fd4a319b | 291 | static int hspi_remove(struct platform_device *pdev) |
d1c8bbd7 | 292 | { |
24b5a82c | 293 | struct hspi_priv *hspi = platform_get_drvdata(pdev); |
d1c8bbd7 KM |
294 | |
295 | pm_runtime_disable(&pdev->dev); | |
296 | ||
49e599b8 | 297 | clk_put(hspi->clk); |
d1c8bbd7 KM |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
8e3489f3 | 302 | static const struct of_device_id hspi_of_match[] = { |
e5f7825c KM |
303 | { .compatible = "renesas,hspi", }, |
304 | { /* sentinel */ } | |
305 | }; | |
306 | MODULE_DEVICE_TABLE(of, hspi_of_match); | |
307 | ||
d1c8bbd7 KM |
308 | static struct platform_driver hspi_driver = { |
309 | .probe = hspi_probe, | |
fd4a319b | 310 | .remove = hspi_remove, |
d1c8bbd7 KM |
311 | .driver = { |
312 | .name = "sh-hspi", | |
e5f7825c | 313 | .of_match_table = hspi_of_match, |
d1c8bbd7 KM |
314 | }, |
315 | }; | |
316 | module_platform_driver(hspi_driver); | |
317 | ||
318 | MODULE_DESCRIPTION("SuperH HSPI bus driver"); | |
319 | MODULE_LICENSE("GPL"); | |
320 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); | |
caedb997 | 321 | MODULE_ALIAS("platform:sh-hspi"); |