Commit | Line | Data |
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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
e2dbf5eb GL |
12 | #include <linux/bitmap.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/completion.h> | |
8051effc | 15 | #include <linux/delay.h> |
e2dbf5eb GL |
16 | #include <linux/err.h> |
17 | #include <linux/gpio.h> | |
8051effc | 18 | #include <linux/interrupt.h> |
e2dbf5eb GL |
19 | #include <linux/io.h> |
20 | #include <linux/kernel.h> | |
d7614de4 | 21 | #include <linux/module.h> |
cf9c86ef | 22 | #include <linux/of.h> |
50a7e23f | 23 | #include <linux/of_device.h> |
8051effc | 24 | #include <linux/platform_device.h> |
8051effc | 25 | #include <linux/pm_runtime.h> |
8051effc | 26 | |
e2dbf5eb | 27 | #include <linux/spi/sh_msiof.h> |
8051effc | 28 | #include <linux/spi/spi.h> |
8051effc | 29 | |
8051effc MD |
30 | #include <asm/unaligned.h> |
31 | ||
50a7e23f GU |
32 | |
33 | struct sh_msiof_chipdata { | |
34 | u16 tx_fifo_size; | |
35 | u16 rx_fifo_size; | |
beb74bb0 | 36 | u16 master_flags; |
50a7e23f GU |
37 | }; |
38 | ||
8051effc | 39 | struct sh_msiof_spi_priv { |
8051effc MD |
40 | void __iomem *mapbase; |
41 | struct clk *clk; | |
42 | struct platform_device *pdev; | |
50a7e23f | 43 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
44 | struct sh_msiof_spi_info *info; |
45 | struct completion done; | |
8051effc MD |
46 | int tx_fifo_size; |
47 | int rx_fifo_size; | |
48 | }; | |
49 | ||
01cfef57 GU |
50 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
51 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
52 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
53 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
54 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
55 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
56 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
57 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
58 | #define CTR 0x28 /* Control Register */ | |
59 | #define FCTR 0x30 /* FIFO Control Register */ | |
60 | #define STR 0x40 /* Status Register */ | |
61 | #define IER 0x44 /* Interrupt Enable Register */ | |
62 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
63 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
64 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
65 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
66 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
67 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
68 | ||
69 | /* TMDR1 and RMDR1 */ | |
70 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
71 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
72 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
73 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
74 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
75 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
76 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
77 | #define MDR1_FLD_SHIFT 2 | |
78 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
79 | /* TMDR1 */ | |
80 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
81 | ||
82 | /* TMDR2 and RMDR2 */ | |
83 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
84 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
85 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
86 | ||
87 | /* TSCR and RSCR */ | |
88 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
89 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
90 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
91 | #define SCR_BRDV_DIV_2 0x0000 | |
92 | #define SCR_BRDV_DIV_4 0x0001 | |
93 | #define SCR_BRDV_DIV_8 0x0002 | |
94 | #define SCR_BRDV_DIV_16 0x0003 | |
95 | #define SCR_BRDV_DIV_32 0x0004 | |
96 | #define SCR_BRDV_DIV_1 0x0007 | |
97 | ||
98 | /* CTR */ | |
99 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
100 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
101 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
102 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
103 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
104 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
105 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
106 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
107 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
108 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
109 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
110 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
111 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
112 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
113 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
114 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
115 | ||
116 | /* STR and IER */ | |
117 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ | |
118 | #define STR_REOF 0x00000080 /* Frame Reception End */ | |
119 | ||
8051effc | 120 | |
e2dbf5eb | 121 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
122 | { |
123 | switch (reg_offs) { | |
124 | case TSCR: | |
125 | case RSCR: | |
126 | return ioread16(p->mapbase + reg_offs); | |
127 | default: | |
128 | return ioread32(p->mapbase + reg_offs); | |
129 | } | |
130 | } | |
131 | ||
132 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 133 | u32 value) |
8051effc MD |
134 | { |
135 | switch (reg_offs) { | |
136 | case TSCR: | |
137 | case RSCR: | |
138 | iowrite16(value, p->mapbase + reg_offs); | |
139 | break; | |
140 | default: | |
141 | iowrite32(value, p->mapbase + reg_offs); | |
142 | break; | |
143 | } | |
144 | } | |
145 | ||
146 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 147 | u32 clr, u32 set) |
8051effc | 148 | { |
e2dbf5eb GL |
149 | u32 mask = clr | set; |
150 | u32 data; | |
8051effc MD |
151 | int k; |
152 | ||
153 | data = sh_msiof_read(p, CTR); | |
154 | data &= ~clr; | |
155 | data |= set; | |
156 | sh_msiof_write(p, CTR, data); | |
157 | ||
158 | for (k = 100; k > 0; k--) { | |
159 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
160 | break; | |
161 | ||
162 | udelay(10); | |
163 | } | |
164 | ||
165 | return k > 0 ? 0 : -ETIMEDOUT; | |
166 | } | |
167 | ||
168 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
169 | { | |
170 | struct sh_msiof_spi_priv *p = data; | |
171 | ||
172 | /* just disable the interrupt and wake up */ | |
173 | sh_msiof_write(p, IER, 0); | |
174 | complete(&p->done); | |
175 | ||
176 | return IRQ_HANDLED; | |
177 | } | |
178 | ||
179 | static struct { | |
180 | unsigned short div; | |
181 | unsigned short scr; | |
182 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
183 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
184 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
185 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
186 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
187 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
188 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
189 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
190 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
191 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
192 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
193 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
194 | }; |
195 | ||
196 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 197 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
198 | { |
199 | unsigned long div = 1024; | |
200 | size_t k; | |
201 | ||
202 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 203 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
204 | |
205 | /* TODO: make more fine grained */ | |
206 | ||
207 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
208 | if (sh_msiof_spi_clk_table[k].div >= div) | |
209 | break; | |
210 | } | |
211 | ||
212 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
213 | ||
214 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
215 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
216 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
217 | } |
218 | ||
219 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 220 | u32 cpol, u32 cpha, |
50a77998 | 221 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 222 | { |
e2dbf5eb | 223 | u32 tmp; |
8051effc MD |
224 | int edge; |
225 | ||
226 | /* | |
e8708ef7 MP |
227 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
228 | * 0 0 10 10 1 1 | |
229 | * 0 1 10 10 0 0 | |
230 | * 1 0 11 11 0 0 | |
231 | * 1 1 11 11 1 1 | |
8051effc | 232 | */ |
8051effc | 233 | sh_msiof_write(p, FCTR, 0); |
50a77998 | 234 | |
01cfef57 GU |
235 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
236 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
237 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
238 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
239 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
240 | /* These bits are reserved if RX needs TX */ | |
241 | tmp &= ~0x0000ffff; | |
242 | } | |
01cfef57 | 243 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 244 | |
01cfef57 GU |
245 | tmp = 0; |
246 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
247 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 248 | |
e2dbf5eb | 249 | edge = cpol ^ !cpha; |
8051effc | 250 | |
01cfef57 GU |
251 | tmp |= edge << CTR_TEDG_SHIFT; |
252 | tmp |= edge << CTR_REDG_SHIFT; | |
253 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
254 | sh_msiof_write(p, CTR, tmp); |
255 | } | |
256 | ||
257 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
258 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 259 | u32 bits, u32 words) |
8051effc | 260 | { |
01cfef57 | 261 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 262 | |
beb74bb0 | 263 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
264 | sh_msiof_write(p, TMDR2, dr2); |
265 | else | |
01cfef57 | 266 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
267 | |
268 | if (rx_buf) | |
269 | sh_msiof_write(p, RMDR2, dr2); | |
270 | ||
271 | sh_msiof_write(p, IER, STR_TEOF | STR_REOF); | |
272 | } | |
273 | ||
274 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
275 | { | |
276 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
277 | } | |
278 | ||
279 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
280 | const void *tx_buf, int words, int fs) | |
281 | { | |
e2dbf5eb | 282 | const u8 *buf_8 = tx_buf; |
8051effc MD |
283 | int k; |
284 | ||
285 | for (k = 0; k < words; k++) | |
286 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
287 | } | |
288 | ||
289 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
290 | const void *tx_buf, int words, int fs) | |
291 | { | |
e2dbf5eb | 292 | const u16 *buf_16 = tx_buf; |
8051effc MD |
293 | int k; |
294 | ||
295 | for (k = 0; k < words; k++) | |
296 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
297 | } | |
298 | ||
299 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
300 | const void *tx_buf, int words, int fs) | |
301 | { | |
e2dbf5eb | 302 | const u16 *buf_16 = tx_buf; |
8051effc MD |
303 | int k; |
304 | ||
305 | for (k = 0; k < words; k++) | |
306 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
307 | } | |
308 | ||
309 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
310 | const void *tx_buf, int words, int fs) | |
311 | { | |
e2dbf5eb | 312 | const u32 *buf_32 = tx_buf; |
8051effc MD |
313 | int k; |
314 | ||
315 | for (k = 0; k < words; k++) | |
316 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
317 | } | |
318 | ||
319 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
320 | const void *tx_buf, int words, int fs) | |
321 | { | |
e2dbf5eb | 322 | const u32 *buf_32 = tx_buf; |
8051effc MD |
323 | int k; |
324 | ||
325 | for (k = 0; k < words; k++) | |
326 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
327 | } | |
328 | ||
9dabb3f3 GL |
329 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
330 | const void *tx_buf, int words, int fs) | |
331 | { | |
332 | const u32 *buf_32 = tx_buf; | |
333 | int k; | |
334 | ||
335 | for (k = 0; k < words; k++) | |
336 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
337 | } | |
338 | ||
339 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
340 | const void *tx_buf, int words, int fs) | |
341 | { | |
342 | const u32 *buf_32 = tx_buf; | |
343 | int k; | |
344 | ||
345 | for (k = 0; k < words; k++) | |
346 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
347 | } | |
348 | ||
8051effc MD |
349 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
350 | void *rx_buf, int words, int fs) | |
351 | { | |
e2dbf5eb | 352 | u8 *buf_8 = rx_buf; |
8051effc MD |
353 | int k; |
354 | ||
355 | for (k = 0; k < words; k++) | |
356 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
357 | } | |
358 | ||
359 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
360 | void *rx_buf, int words, int fs) | |
361 | { | |
e2dbf5eb | 362 | u16 *buf_16 = rx_buf; |
8051effc MD |
363 | int k; |
364 | ||
365 | for (k = 0; k < words; k++) | |
366 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
367 | } | |
368 | ||
369 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
370 | void *rx_buf, int words, int fs) | |
371 | { | |
e2dbf5eb | 372 | u16 *buf_16 = rx_buf; |
8051effc MD |
373 | int k; |
374 | ||
375 | for (k = 0; k < words; k++) | |
376 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
377 | } | |
378 | ||
379 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
380 | void *rx_buf, int words, int fs) | |
381 | { | |
e2dbf5eb | 382 | u32 *buf_32 = rx_buf; |
8051effc MD |
383 | int k; |
384 | ||
385 | for (k = 0; k < words; k++) | |
386 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
387 | } | |
388 | ||
389 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
390 | void *rx_buf, int words, int fs) | |
391 | { | |
e2dbf5eb | 392 | u32 *buf_32 = rx_buf; |
8051effc MD |
393 | int k; |
394 | ||
395 | for (k = 0; k < words; k++) | |
396 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
397 | } | |
398 | ||
9dabb3f3 GL |
399 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
400 | void *rx_buf, int words, int fs) | |
401 | { | |
402 | u32 *buf_32 = rx_buf; | |
403 | int k; | |
404 | ||
405 | for (k = 0; k < words; k++) | |
406 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
407 | } | |
408 | ||
409 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
410 | void *rx_buf, int words, int fs) | |
411 | { | |
412 | u32 *buf_32 = rx_buf; | |
413 | int k; | |
414 | ||
415 | for (k = 0; k < words; k++) | |
416 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
417 | } | |
418 | ||
8d19534a | 419 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 420 | { |
8d19534a | 421 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 422 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8051effc | 423 | |
8d19534a GU |
424 | if (!np) { |
425 | /* | |
426 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
427 | * if any. otherwise let HW control CS | |
428 | */ | |
429 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
430 | } | |
8051effc | 431 | |
c833ff73 GU |
432 | /* Configure pins before deasserting CS */ |
433 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
434 | !!(spi->mode & SPI_CPHA), | |
435 | !!(spi->mode & SPI_3WIRE), | |
436 | !!(spi->mode & SPI_LSB_FIRST), | |
437 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc | 438 | |
1bd6363b GU |
439 | if (spi->cs_gpio >= 0) |
440 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
8051effc | 441 | |
1bd6363b | 442 | return 0; |
8051effc MD |
443 | } |
444 | ||
c833ff73 GU |
445 | static int sh_msiof_prepare_message(struct spi_master *master, |
446 | struct spi_message *msg) | |
8051effc | 447 | { |
c833ff73 GU |
448 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
449 | const struct spi_device *spi = msg->spi; | |
8051effc | 450 | |
c833ff73 GU |
451 | /* Configure pins before asserting CS */ |
452 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
453 | !!(spi->mode & SPI_CPHA), | |
454 | !!(spi->mode & SPI_3WIRE), | |
455 | !!(spi->mode & SPI_LSB_FIRST), | |
456 | !!(spi->mode & SPI_CS_HIGH)); | |
457 | return 0; | |
8051effc MD |
458 | } |
459 | ||
460 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, | |
461 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
462 | const void *, int, int), | |
463 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
464 | void *, int, int), | |
465 | const void *tx_buf, void *rx_buf, | |
466 | int words, int bits) | |
467 | { | |
468 | int fifo_shift; | |
469 | int ret; | |
470 | ||
471 | /* limit maximum word transfer to rx/tx fifo size */ | |
472 | if (tx_buf) | |
473 | words = min_t(int, words, p->tx_fifo_size); | |
474 | if (rx_buf) | |
475 | words = min_t(int, words, p->rx_fifo_size); | |
476 | ||
477 | /* the fifo contents need shifting */ | |
478 | fifo_shift = 32 - bits; | |
479 | ||
480 | /* setup msiof transfer mode registers */ | |
481 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
482 | ||
483 | /* write tx fifo */ | |
484 | if (tx_buf) | |
485 | tx_fifo(p, tx_buf, words, fifo_shift); | |
486 | ||
487 | /* setup clock and rx/tx signals */ | |
488 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
489 | if (rx_buf) | |
490 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
491 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
492 | ||
493 | /* start by setting frame bit */ | |
16735d02 | 494 | reinit_completion(&p->done); |
8051effc MD |
495 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
496 | if (ret) { | |
497 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
498 | goto err; | |
499 | } | |
500 | ||
501 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
502 | wait_for_completion(&p->done); | |
503 | ||
504 | /* read rx fifo */ | |
505 | if (rx_buf) | |
506 | rx_fifo(p, rx_buf, words, fifo_shift); | |
507 | ||
508 | /* clear status bits */ | |
509 | sh_msiof_reset_str(p); | |
510 | ||
a669c11a | 511 | /* shut down frame, rx/tx and clock signals */ |
8051effc MD |
512 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); |
513 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
514 | if (rx_buf) | |
515 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
516 | ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
517 | if (ret) { | |
518 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
519 | goto err; | |
520 | } | |
521 | ||
522 | return words; | |
523 | ||
524 | err: | |
525 | sh_msiof_write(p, IER, 0); | |
526 | return ret; | |
527 | } | |
528 | ||
1bd6363b GU |
529 | static int sh_msiof_transfer_one(struct spi_master *master, |
530 | struct spi_device *spi, | |
531 | struct spi_transfer *t) | |
8051effc | 532 | { |
1bd6363b | 533 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
8051effc MD |
534 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
535 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
536 | int bits; | |
537 | int bytes_per_word; | |
538 | int bytes_done; | |
539 | int words; | |
540 | int n; | |
9dabb3f3 | 541 | bool swab; |
8051effc | 542 | |
b1415860 | 543 | bits = t->bits_per_word; |
8051effc | 544 | |
9dabb3f3 GL |
545 | if (bits <= 8 && t->len > 15 && !(t->len & 3)) { |
546 | bits = 32; | |
547 | swab = true; | |
548 | } else { | |
549 | swab = false; | |
550 | } | |
551 | ||
8051effc MD |
552 | /* setup bytes per word and fifo read/write functions */ |
553 | if (bits <= 8) { | |
554 | bytes_per_word = 1; | |
555 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
556 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
557 | } else if (bits <= 16) { | |
558 | bytes_per_word = 2; | |
559 | if ((unsigned long)t->tx_buf & 0x01) | |
560 | tx_fifo = sh_msiof_spi_write_fifo_16u; | |
561 | else | |
562 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
563 | ||
564 | if ((unsigned long)t->rx_buf & 0x01) | |
565 | rx_fifo = sh_msiof_spi_read_fifo_16u; | |
566 | else | |
567 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
568 | } else if (swab) { |
569 | bytes_per_word = 4; | |
570 | if ((unsigned long)t->tx_buf & 0x03) | |
571 | tx_fifo = sh_msiof_spi_write_fifo_s32u; | |
572 | else | |
573 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
574 | ||
575 | if ((unsigned long)t->rx_buf & 0x03) | |
576 | rx_fifo = sh_msiof_spi_read_fifo_s32u; | |
577 | else | |
578 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
579 | } else { |
580 | bytes_per_word = 4; | |
581 | if ((unsigned long)t->tx_buf & 0x03) | |
582 | tx_fifo = sh_msiof_spi_write_fifo_32u; | |
583 | else | |
584 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
585 | ||
586 | if ((unsigned long)t->rx_buf & 0x03) | |
587 | rx_fifo = sh_msiof_spi_read_fifo_32u; | |
588 | else | |
589 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
590 | } | |
591 | ||
592 | /* setup clocks (clock already enabled in chipselect()) */ | |
b1415860 | 593 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); |
8051effc MD |
594 | |
595 | /* transfer in fifo sized chunks */ | |
596 | words = t->len / bytes_per_word; | |
597 | bytes_done = 0; | |
598 | ||
599 | while (bytes_done < t->len) { | |
8a6afb9a GL |
600 | void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL; |
601 | const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL; | |
8051effc | 602 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, |
8a6afb9a GL |
603 | tx_buf, |
604 | rx_buf, | |
8051effc MD |
605 | words, bits); |
606 | if (n < 0) | |
607 | break; | |
608 | ||
609 | bytes_done += n * bytes_per_word; | |
610 | words -= n; | |
611 | } | |
612 | ||
8051effc MD |
613 | return 0; |
614 | } | |
615 | ||
50a7e23f GU |
616 | static const struct sh_msiof_chipdata sh_data = { |
617 | .tx_fifo_size = 64, | |
618 | .rx_fifo_size = 64, | |
beb74bb0 GU |
619 | .master_flags = 0, |
620 | }; | |
621 | ||
622 | static const struct sh_msiof_chipdata r8a779x_data = { | |
623 | .tx_fifo_size = 64, | |
624 | .rx_fifo_size = 256, | |
625 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
626 | }; |
627 | ||
628 | static const struct of_device_id sh_msiof_match[] = { | |
629 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
630 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
631 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
632 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
633 | {}, |
634 | }; | |
635 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
636 | ||
cf9c86ef BH |
637 | #ifdef CONFIG_OF |
638 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
639 | { | |
640 | struct sh_msiof_spi_info *info; | |
641 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 642 | u32 num_cs = 1; |
cf9c86ef BH |
643 | |
644 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 645 | if (!info) |
cf9c86ef | 646 | return NULL; |
cf9c86ef BH |
647 | |
648 | /* Parse the MSIOF properties */ | |
649 | of_property_read_u32(np, "num-cs", &num_cs); | |
650 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
651 | &info->tx_fifo_override); | |
652 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
653 | &info->rx_fifo_override); | |
654 | ||
655 | info->num_chipselect = num_cs; | |
656 | ||
657 | return info; | |
658 | } | |
659 | #else | |
660 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
661 | { | |
662 | return NULL; | |
663 | } | |
664 | #endif | |
665 | ||
8051effc MD |
666 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
667 | { | |
668 | struct resource *r; | |
669 | struct spi_master *master; | |
50a7e23f | 670 | const struct of_device_id *of_id; |
8051effc | 671 | struct sh_msiof_spi_priv *p; |
8051effc MD |
672 | int i; |
673 | int ret; | |
674 | ||
675 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
676 | if (master == NULL) { | |
677 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 678 | return -ENOMEM; |
8051effc MD |
679 | } |
680 | ||
681 | p = spi_master_get_devdata(master); | |
682 | ||
683 | platform_set_drvdata(pdev, p); | |
50a7e23f GU |
684 | |
685 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
686 | if (of_id) { | |
687 | p->chipdata = of_id->data; | |
cf9c86ef | 688 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
689 | } else { |
690 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 691 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 692 | } |
cf9c86ef BH |
693 | |
694 | if (!p->info) { | |
695 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
696 | ret = -ENXIO; | |
697 | goto err1; | |
698 | } | |
699 | ||
8051effc MD |
700 | init_completion(&p->done); |
701 | ||
b4dd05de | 702 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 703 | if (IS_ERR(p->clk)) { |
078b6ead | 704 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
705 | ret = PTR_ERR(p->clk); |
706 | goto err1; | |
707 | } | |
708 | ||
8051effc | 709 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
710 | if (i < 0) { |
711 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 712 | ret = -ENOENT; |
b4dd05de | 713 | goto err1; |
8051effc | 714 | } |
b4dd05de LP |
715 | |
716 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
718 | if (IS_ERR(p->mapbase)) { | |
719 | ret = PTR_ERR(p->mapbase); | |
720 | goto err1; | |
8051effc MD |
721 | } |
722 | ||
b4dd05de LP |
723 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
724 | dev_name(&pdev->dev), p); | |
8051effc MD |
725 | if (ret) { |
726 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 727 | goto err1; |
8051effc MD |
728 | } |
729 | ||
730 | p->pdev = pdev; | |
731 | pm_runtime_enable(&pdev->dev); | |
732 | ||
8051effc | 733 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
734 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
735 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
736 | if (p->info->tx_fifo_override) |
737 | p->tx_fifo_size = p->info->tx_fifo_override; | |
738 | if (p->info->rx_fifo_override) | |
739 | p->rx_fifo_size = p->info->rx_fifo_override; | |
740 | ||
1bd6363b | 741 | /* init master code */ |
8051effc MD |
742 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
743 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 744 | master->flags = p->chipdata->master_flags; |
8051effc | 745 | master->bus_num = pdev->id; |
f7c05e83 | 746 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 747 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 748 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 749 | master->prepare_message = sh_msiof_prepare_message; |
2416289c | 750 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 751 | master->auto_runtime_pm = true; |
1bd6363b | 752 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 753 | |
1bd6363b GU |
754 | ret = devm_spi_register_master(&pdev->dev, master); |
755 | if (ret < 0) { | |
756 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
757 | goto err2; | |
758 | } | |
8051effc | 759 | |
1bd6363b | 760 | return 0; |
8051effc | 761 | |
1bd6363b | 762 | err2: |
8051effc | 763 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
764 | err1: |
765 | spi_master_put(master); | |
8051effc MD |
766 | return ret; |
767 | } | |
768 | ||
769 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
770 | { | |
1bd6363b | 771 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 772 | return 0; |
8051effc MD |
773 | } |
774 | ||
50a7e23f GU |
775 | static struct platform_device_id spi_driver_ids[] = { |
776 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
777 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
778 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
779 | {}, |
780 | }; | |
50a7e23f | 781 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 782 | |
8051effc MD |
783 | static struct platform_driver sh_msiof_spi_drv = { |
784 | .probe = sh_msiof_spi_probe, | |
785 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 786 | .id_table = spi_driver_ids, |
8051effc MD |
787 | .driver = { |
788 | .name = "spi_sh_msiof", | |
789 | .owner = THIS_MODULE, | |
691ee4ed | 790 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
791 | }, |
792 | }; | |
940ab889 | 793 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
794 | |
795 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
796 | MODULE_AUTHOR("Magnus Damm"); | |
797 | MODULE_LICENSE("GPL v2"); | |
798 | MODULE_ALIAS("platform:spi_sh_msiof"); |