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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
b0d0ce8b | 5 | * Copyright (C) 2014 Glider bvba |
8051effc MD |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
e2dbf5eb GL |
13 | #include <linux/bitmap.h> |
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
8051effc | 16 | #include <linux/delay.h> |
b0d0ce8b GU |
17 | #include <linux/dma-mapping.h> |
18 | #include <linux/dmaengine.h> | |
e2dbf5eb GL |
19 | #include <linux/err.h> |
20 | #include <linux/gpio.h> | |
8051effc | 21 | #include <linux/interrupt.h> |
e2dbf5eb GL |
22 | #include <linux/io.h> |
23 | #include <linux/kernel.h> | |
d7614de4 | 24 | #include <linux/module.h> |
cf9c86ef | 25 | #include <linux/of.h> |
50a7e23f | 26 | #include <linux/of_device.h> |
8051effc | 27 | #include <linux/platform_device.h> |
8051effc | 28 | #include <linux/pm_runtime.h> |
b0d0ce8b | 29 | #include <linux/sh_dma.h> |
8051effc | 30 | |
e2dbf5eb | 31 | #include <linux/spi/sh_msiof.h> |
8051effc | 32 | #include <linux/spi/spi.h> |
8051effc | 33 | |
8051effc MD |
34 | #include <asm/unaligned.h> |
35 | ||
50a7e23f GU |
36 | |
37 | struct sh_msiof_chipdata { | |
38 | u16 tx_fifo_size; | |
39 | u16 rx_fifo_size; | |
beb74bb0 | 40 | u16 master_flags; |
50a7e23f GU |
41 | }; |
42 | ||
8051effc | 43 | struct sh_msiof_spi_priv { |
b0d0ce8b | 44 | struct spi_master *master; |
8051effc MD |
45 | void __iomem *mapbase; |
46 | struct clk *clk; | |
47 | struct platform_device *pdev; | |
50a7e23f | 48 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
49 | struct sh_msiof_spi_info *info; |
50 | struct completion done; | |
8051effc MD |
51 | int tx_fifo_size; |
52 | int rx_fifo_size; | |
b0d0ce8b GU |
53 | void *tx_dma_page; |
54 | void *rx_dma_page; | |
55 | dma_addr_t tx_dma_addr; | |
56 | dma_addr_t rx_dma_addr; | |
8051effc MD |
57 | }; |
58 | ||
01cfef57 GU |
59 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
60 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
61 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
62 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
63 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
64 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
65 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
66 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
67 | #define CTR 0x28 /* Control Register */ | |
68 | #define FCTR 0x30 /* FIFO Control Register */ | |
69 | #define STR 0x40 /* Status Register */ | |
70 | #define IER 0x44 /* Interrupt Enable Register */ | |
71 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
72 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
73 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
74 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
75 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
76 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
77 | ||
78 | /* TMDR1 and RMDR1 */ | |
79 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
80 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
81 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
82 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
83 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
84 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
85 | #define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ | |
86 | #define MDR1_FLD_SHIFT 2 | |
87 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
88 | /* TMDR1 */ | |
89 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
90 | ||
91 | /* TMDR2 and RMDR2 */ | |
92 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
93 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
94 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
95 | ||
b0d0ce8b GU |
96 | #define MAX_WDLEN 256U |
97 | ||
01cfef57 GU |
98 | /* TSCR and RSCR */ |
99 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
100 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
101 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
102 | #define SCR_BRDV_DIV_2 0x0000 | |
103 | #define SCR_BRDV_DIV_4 0x0001 | |
104 | #define SCR_BRDV_DIV_8 0x0002 | |
105 | #define SCR_BRDV_DIV_16 0x0003 | |
106 | #define SCR_BRDV_DIV_32 0x0004 | |
107 | #define SCR_BRDV_DIV_1 0x0007 | |
108 | ||
109 | /* CTR */ | |
110 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
111 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
112 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
113 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
114 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
115 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
116 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
117 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
118 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
119 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
120 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
121 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
122 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
123 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
124 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
125 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
126 | ||
2e2b3687 GU |
127 | /* FCTR */ |
128 | #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ | |
129 | #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ | |
130 | #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ | |
131 | #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ | |
132 | #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ | |
133 | #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ | |
134 | #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ | |
135 | #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ | |
136 | #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ | |
137 | #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ | |
138 | #define FCTR_TFUA_SHIFT 20 | |
139 | #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) | |
140 | #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ | |
141 | #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ | |
142 | #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ | |
143 | #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ | |
144 | #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ | |
145 | #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ | |
146 | #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ | |
147 | #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ | |
148 | #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ | |
149 | #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ | |
150 | #define FCTR_RFUA_SHIFT 4 | |
151 | #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) | |
152 | ||
153 | /* STR */ | |
154 | #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ | |
155 | #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ | |
01cfef57 | 156 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ |
2e2b3687 GU |
157 | #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ |
158 | #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ | |
159 | #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ | |
160 | #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ | |
161 | #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ | |
01cfef57 | 162 | #define STR_REOF 0x00000080 /* Frame Reception End */ |
2e2b3687 GU |
163 | #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ |
164 | #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ | |
165 | #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ | |
166 | ||
167 | /* IER */ | |
168 | #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ | |
169 | #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ | |
170 | #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ | |
171 | #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ | |
172 | #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ | |
173 | #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ | |
174 | #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ | |
175 | #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ | |
176 | #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ | |
177 | #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ | |
178 | #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ | |
179 | #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ | |
180 | #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ | |
181 | #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ | |
01cfef57 | 182 | |
8051effc | 183 | |
e2dbf5eb | 184 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
185 | { |
186 | switch (reg_offs) { | |
187 | case TSCR: | |
188 | case RSCR: | |
189 | return ioread16(p->mapbase + reg_offs); | |
190 | default: | |
191 | return ioread32(p->mapbase + reg_offs); | |
192 | } | |
193 | } | |
194 | ||
195 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 196 | u32 value) |
8051effc MD |
197 | { |
198 | switch (reg_offs) { | |
199 | case TSCR: | |
200 | case RSCR: | |
201 | iowrite16(value, p->mapbase + reg_offs); | |
202 | break; | |
203 | default: | |
204 | iowrite32(value, p->mapbase + reg_offs); | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
209 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 210 | u32 clr, u32 set) |
8051effc | 211 | { |
e2dbf5eb GL |
212 | u32 mask = clr | set; |
213 | u32 data; | |
8051effc MD |
214 | int k; |
215 | ||
216 | data = sh_msiof_read(p, CTR); | |
217 | data &= ~clr; | |
218 | data |= set; | |
219 | sh_msiof_write(p, CTR, data); | |
220 | ||
221 | for (k = 100; k > 0; k--) { | |
222 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
223 | break; | |
224 | ||
225 | udelay(10); | |
226 | } | |
227 | ||
228 | return k > 0 ? 0 : -ETIMEDOUT; | |
229 | } | |
230 | ||
231 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
232 | { | |
233 | struct sh_msiof_spi_priv *p = data; | |
234 | ||
235 | /* just disable the interrupt and wake up */ | |
236 | sh_msiof_write(p, IER, 0); | |
237 | complete(&p->done); | |
238 | ||
239 | return IRQ_HANDLED; | |
240 | } | |
241 | ||
242 | static struct { | |
243 | unsigned short div; | |
244 | unsigned short scr; | |
245 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
246 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
247 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
248 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
249 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
250 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
251 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
252 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
253 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
254 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
255 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
256 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
257 | }; |
258 | ||
259 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 260 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
261 | { |
262 | unsigned long div = 1024; | |
263 | size_t k; | |
264 | ||
265 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 266 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
267 | |
268 | /* TODO: make more fine grained */ | |
269 | ||
270 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
271 | if (sh_msiof_spi_clk_table[k].div >= div) | |
272 | break; | |
273 | } | |
274 | ||
275 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
276 | ||
277 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
278 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
279 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
280 | } |
281 | ||
282 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 283 | u32 cpol, u32 cpha, |
50a77998 | 284 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 285 | { |
e2dbf5eb | 286 | u32 tmp; |
8051effc MD |
287 | int edge; |
288 | ||
289 | /* | |
e8708ef7 MP |
290 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
291 | * 0 0 10 10 1 1 | |
292 | * 0 1 10 10 0 0 | |
293 | * 1 0 11 11 0 0 | |
294 | * 1 1 11 11 1 1 | |
8051effc | 295 | */ |
01cfef57 GU |
296 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
297 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
298 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
299 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
beb74bb0 GU |
300 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
301 | /* These bits are reserved if RX needs TX */ | |
302 | tmp &= ~0x0000ffff; | |
303 | } | |
01cfef57 | 304 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 305 | |
01cfef57 GU |
306 | tmp = 0; |
307 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
308 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 309 | |
e2dbf5eb | 310 | edge = cpol ^ !cpha; |
8051effc | 311 | |
01cfef57 GU |
312 | tmp |= edge << CTR_TEDG_SHIFT; |
313 | tmp |= edge << CTR_REDG_SHIFT; | |
314 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
315 | sh_msiof_write(p, CTR, tmp); |
316 | } | |
317 | ||
318 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
319 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 320 | u32 bits, u32 words) |
8051effc | 321 | { |
01cfef57 | 322 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 323 | |
beb74bb0 | 324 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
325 | sh_msiof_write(p, TMDR2, dr2); |
326 | else | |
01cfef57 | 327 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
328 | |
329 | if (rx_buf) | |
330 | sh_msiof_write(p, RMDR2, dr2); | |
8051effc MD |
331 | } |
332 | ||
333 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
334 | { | |
335 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
336 | } | |
337 | ||
338 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
339 | const void *tx_buf, int words, int fs) | |
340 | { | |
e2dbf5eb | 341 | const u8 *buf_8 = tx_buf; |
8051effc MD |
342 | int k; |
343 | ||
344 | for (k = 0; k < words; k++) | |
345 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
346 | } | |
347 | ||
348 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
349 | const void *tx_buf, int words, int fs) | |
350 | { | |
e2dbf5eb | 351 | const u16 *buf_16 = tx_buf; |
8051effc MD |
352 | int k; |
353 | ||
354 | for (k = 0; k < words; k++) | |
355 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
356 | } | |
357 | ||
358 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
359 | const void *tx_buf, int words, int fs) | |
360 | { | |
e2dbf5eb | 361 | const u16 *buf_16 = tx_buf; |
8051effc MD |
362 | int k; |
363 | ||
364 | for (k = 0; k < words; k++) | |
365 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
366 | } | |
367 | ||
368 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
369 | const void *tx_buf, int words, int fs) | |
370 | { | |
e2dbf5eb | 371 | const u32 *buf_32 = tx_buf; |
8051effc MD |
372 | int k; |
373 | ||
374 | for (k = 0; k < words; k++) | |
375 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
376 | } | |
377 | ||
378 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
379 | const void *tx_buf, int words, int fs) | |
380 | { | |
e2dbf5eb | 381 | const u32 *buf_32 = tx_buf; |
8051effc MD |
382 | int k; |
383 | ||
384 | for (k = 0; k < words; k++) | |
385 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
386 | } | |
387 | ||
9dabb3f3 GL |
388 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
389 | const void *tx_buf, int words, int fs) | |
390 | { | |
391 | const u32 *buf_32 = tx_buf; | |
392 | int k; | |
393 | ||
394 | for (k = 0; k < words; k++) | |
395 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
396 | } | |
397 | ||
398 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
399 | const void *tx_buf, int words, int fs) | |
400 | { | |
401 | const u32 *buf_32 = tx_buf; | |
402 | int k; | |
403 | ||
404 | for (k = 0; k < words; k++) | |
405 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
406 | } | |
407 | ||
8051effc MD |
408 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
409 | void *rx_buf, int words, int fs) | |
410 | { | |
e2dbf5eb | 411 | u8 *buf_8 = rx_buf; |
8051effc MD |
412 | int k; |
413 | ||
414 | for (k = 0; k < words; k++) | |
415 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
416 | } | |
417 | ||
418 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
419 | void *rx_buf, int words, int fs) | |
420 | { | |
e2dbf5eb | 421 | u16 *buf_16 = rx_buf; |
8051effc MD |
422 | int k; |
423 | ||
424 | for (k = 0; k < words; k++) | |
425 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
426 | } | |
427 | ||
428 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
429 | void *rx_buf, int words, int fs) | |
430 | { | |
e2dbf5eb | 431 | u16 *buf_16 = rx_buf; |
8051effc MD |
432 | int k; |
433 | ||
434 | for (k = 0; k < words; k++) | |
435 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
436 | } | |
437 | ||
438 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
439 | void *rx_buf, int words, int fs) | |
440 | { | |
e2dbf5eb | 441 | u32 *buf_32 = rx_buf; |
8051effc MD |
442 | int k; |
443 | ||
444 | for (k = 0; k < words; k++) | |
445 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
446 | } | |
447 | ||
448 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
449 | void *rx_buf, int words, int fs) | |
450 | { | |
e2dbf5eb | 451 | u32 *buf_32 = rx_buf; |
8051effc MD |
452 | int k; |
453 | ||
454 | for (k = 0; k < words; k++) | |
455 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
456 | } | |
457 | ||
9dabb3f3 GL |
458 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
459 | void *rx_buf, int words, int fs) | |
460 | { | |
461 | u32 *buf_32 = rx_buf; | |
462 | int k; | |
463 | ||
464 | for (k = 0; k < words; k++) | |
465 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
466 | } | |
467 | ||
468 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
469 | void *rx_buf, int words, int fs) | |
470 | { | |
471 | u32 *buf_32 = rx_buf; | |
472 | int k; | |
473 | ||
474 | for (k = 0; k < words; k++) | |
475 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
476 | } | |
477 | ||
8d19534a | 478 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 479 | { |
8d19534a | 480 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 481 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8051effc | 482 | |
8d19534a GU |
483 | if (!np) { |
484 | /* | |
485 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
486 | * if any. otherwise let HW control CS | |
487 | */ | |
488 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
489 | } | |
8051effc | 490 | |
c833ff73 GU |
491 | /* Configure pins before deasserting CS */ |
492 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
493 | !!(spi->mode & SPI_CPHA), | |
494 | !!(spi->mode & SPI_3WIRE), | |
495 | !!(spi->mode & SPI_LSB_FIRST), | |
496 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc | 497 | |
1bd6363b GU |
498 | if (spi->cs_gpio >= 0) |
499 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
8051effc | 500 | |
1bd6363b | 501 | return 0; |
8051effc MD |
502 | } |
503 | ||
c833ff73 GU |
504 | static int sh_msiof_prepare_message(struct spi_master *master, |
505 | struct spi_message *msg) | |
8051effc | 506 | { |
c833ff73 GU |
507 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
508 | const struct spi_device *spi = msg->spi; | |
8051effc | 509 | |
c833ff73 GU |
510 | /* Configure pins before asserting CS */ |
511 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
512 | !!(spi->mode & SPI_CPHA), | |
513 | !!(spi->mode & SPI_3WIRE), | |
514 | !!(spi->mode & SPI_LSB_FIRST), | |
515 | !!(spi->mode & SPI_CS_HIGH)); | |
516 | return 0; | |
8051effc MD |
517 | } |
518 | ||
76c02e71 GU |
519 | static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) |
520 | { | |
521 | int ret; | |
522 | ||
523 | /* setup clock and rx/tx signals */ | |
524 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
525 | if (rx_buf && !ret) | |
526 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
527 | if (!ret) | |
528 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
529 | ||
530 | /* start by setting frame bit */ | |
531 | if (!ret) | |
532 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
537 | static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) | |
538 | { | |
539 | int ret; | |
540 | ||
541 | /* shut down frame, rx/tx and clock signals */ | |
542 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
543 | if (!ret) | |
544 | ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
545 | if (rx_buf && !ret) | |
546 | ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
547 | if (!ret) | |
548 | ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
8051effc MD |
553 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
554 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
555 | const void *, int, int), | |
556 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
557 | void *, int, int), | |
558 | const void *tx_buf, void *rx_buf, | |
559 | int words, int bits) | |
560 | { | |
561 | int fifo_shift; | |
562 | int ret; | |
563 | ||
564 | /* limit maximum word transfer to rx/tx fifo size */ | |
565 | if (tx_buf) | |
566 | words = min_t(int, words, p->tx_fifo_size); | |
567 | if (rx_buf) | |
568 | words = min_t(int, words, p->rx_fifo_size); | |
569 | ||
570 | /* the fifo contents need shifting */ | |
571 | fifo_shift = 32 - bits; | |
572 | ||
b0d0ce8b GU |
573 | /* default FIFO watermarks for PIO */ |
574 | sh_msiof_write(p, FCTR, 0); | |
575 | ||
8051effc MD |
576 | /* setup msiof transfer mode registers */ |
577 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
b0d0ce8b | 578 | sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); |
8051effc MD |
579 | |
580 | /* write tx fifo */ | |
581 | if (tx_buf) | |
582 | tx_fifo(p, tx_buf, words, fifo_shift); | |
583 | ||
16735d02 | 584 | reinit_completion(&p->done); |
76c02e71 GU |
585 | |
586 | ret = sh_msiof_spi_start(p, rx_buf); | |
8051effc MD |
587 | if (ret) { |
588 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
75b82e23 | 589 | goto stop_ier; |
8051effc MD |
590 | } |
591 | ||
592 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
75b82e23 GU |
593 | ret = wait_for_completion_timeout(&p->done, HZ); |
594 | if (!ret) { | |
595 | dev_err(&p->pdev->dev, "PIO timeout\n"); | |
596 | ret = -ETIMEDOUT; | |
597 | goto stop_reset; | |
598 | } | |
8051effc MD |
599 | |
600 | /* read rx fifo */ | |
601 | if (rx_buf) | |
602 | rx_fifo(p, rx_buf, words, fifo_shift); | |
603 | ||
604 | /* clear status bits */ | |
605 | sh_msiof_reset_str(p); | |
606 | ||
76c02e71 | 607 | ret = sh_msiof_spi_stop(p, rx_buf); |
8051effc MD |
608 | if (ret) { |
609 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
75b82e23 | 610 | return ret; |
8051effc MD |
611 | } |
612 | ||
613 | return words; | |
614 | ||
75b82e23 GU |
615 | stop_reset: |
616 | sh_msiof_reset_str(p); | |
617 | sh_msiof_spi_stop(p, rx_buf); | |
618 | stop_ier: | |
8051effc MD |
619 | sh_msiof_write(p, IER, 0); |
620 | return ret; | |
621 | } | |
622 | ||
b0d0ce8b GU |
623 | static void sh_msiof_dma_complete(void *arg) |
624 | { | |
625 | struct sh_msiof_spi_priv *p = arg; | |
626 | ||
627 | sh_msiof_write(p, IER, 0); | |
628 | complete(&p->done); | |
629 | } | |
630 | ||
631 | static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, | |
632 | void *rx, unsigned int len) | |
633 | { | |
634 | u32 ier_bits = 0; | |
635 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; | |
636 | dma_cookie_t cookie; | |
637 | int ret; | |
638 | ||
3e81b592 | 639 | /* First prepare and submit the DMA request(s), as this may fail */ |
b0d0ce8b GU |
640 | if (rx) { |
641 | ier_bits |= IER_RDREQE | IER_RDMAE; | |
642 | desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, | |
643 | p->rx_dma_addr, len, DMA_FROM_DEVICE, | |
644 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
a5e7c719 GU |
645 | if (!desc_rx) |
646 | return -EAGAIN; | |
b0d0ce8b | 647 | |
b0d0ce8b GU |
648 | desc_rx->callback = sh_msiof_dma_complete; |
649 | desc_rx->callback_param = p; | |
650 | cookie = dmaengine_submit(desc_rx); | |
a5e7c719 GU |
651 | if (dma_submit_error(cookie)) |
652 | return cookie; | |
b0d0ce8b GU |
653 | } |
654 | ||
655 | if (tx) { | |
3e81b592 GU |
656 | ier_bits |= IER_TDREQE | IER_TDMAE; |
657 | dma_sync_single_for_device(p->master->dma_tx->device->dev, | |
658 | p->tx_dma_addr, len, DMA_TO_DEVICE); | |
659 | desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, | |
660 | p->tx_dma_addr, len, DMA_TO_DEVICE, | |
661 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
662 | if (!desc_tx) { | |
663 | ret = -EAGAIN; | |
664 | goto no_dma_tx; | |
665 | } | |
666 | ||
b0d0ce8b GU |
667 | if (rx) { |
668 | /* No callback */ | |
669 | desc_tx->callback = NULL; | |
670 | } else { | |
671 | desc_tx->callback = sh_msiof_dma_complete; | |
672 | desc_tx->callback_param = p; | |
673 | } | |
674 | cookie = dmaengine_submit(desc_tx); | |
675 | if (dma_submit_error(cookie)) { | |
676 | ret = cookie; | |
3e81b592 | 677 | goto no_dma_tx; |
b0d0ce8b | 678 | } |
b0d0ce8b GU |
679 | } |
680 | ||
3e81b592 GU |
681 | /* 1 stage FIFO watermarks for DMA */ |
682 | sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); | |
683 | ||
684 | /* setup msiof transfer mode registers (32-bit words) */ | |
685 | sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); | |
686 | ||
687 | sh_msiof_write(p, IER, ier_bits); | |
688 | ||
689 | reinit_completion(&p->done); | |
690 | ||
691 | /* Now start DMA */ | |
692 | if (tx) | |
693 | dma_async_issue_pending(p->master->dma_rx); | |
694 | if (rx) | |
695 | dma_async_issue_pending(p->master->dma_tx); | |
696 | ||
b0d0ce8b GU |
697 | ret = sh_msiof_spi_start(p, rx); |
698 | if (ret) { | |
699 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
3e81b592 | 700 | goto stop_dma; |
b0d0ce8b GU |
701 | } |
702 | ||
703 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
704 | ret = wait_for_completion_timeout(&p->done, HZ); | |
705 | if (!ret) { | |
706 | dev_err(&p->pdev->dev, "DMA timeout\n"); | |
707 | ret = -ETIMEDOUT; | |
708 | goto stop_reset; | |
709 | } | |
710 | ||
711 | /* clear status bits */ | |
712 | sh_msiof_reset_str(p); | |
713 | ||
714 | ret = sh_msiof_spi_stop(p, rx); | |
715 | if (ret) { | |
716 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
717 | return ret; | |
718 | } | |
719 | ||
720 | if (rx) | |
5dabcf2f GU |
721 | dma_sync_single_for_cpu(p->master->dma_rx->device->dev, |
722 | p->rx_dma_addr, len, | |
b0d0ce8b GU |
723 | DMA_FROM_DEVICE); |
724 | ||
725 | return 0; | |
726 | ||
727 | stop_reset: | |
728 | sh_msiof_reset_str(p); | |
729 | sh_msiof_spi_stop(p, rx); | |
3e81b592 | 730 | stop_dma: |
b0d0ce8b GU |
731 | if (tx) |
732 | dmaengine_terminate_all(p->master->dma_tx); | |
3e81b592 | 733 | no_dma_tx: |
b0d0ce8b GU |
734 | if (rx) |
735 | dmaengine_terminate_all(p->master->dma_rx); | |
b0d0ce8b GU |
736 | sh_msiof_write(p, IER, 0); |
737 | return ret; | |
738 | } | |
739 | ||
740 | static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) | |
741 | { | |
742 | /* src or dst can be unaligned, but not both */ | |
743 | if ((unsigned long)src & 3) { | |
744 | while (words--) { | |
745 | *dst++ = swab32(get_unaligned(src)); | |
746 | src++; | |
747 | } | |
748 | } else if ((unsigned long)dst & 3) { | |
749 | while (words--) { | |
750 | put_unaligned(swab32(*src++), dst); | |
751 | dst++; | |
752 | } | |
753 | } else { | |
754 | while (words--) | |
755 | *dst++ = swab32(*src++); | |
756 | } | |
757 | } | |
758 | ||
759 | static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) | |
760 | { | |
761 | /* src or dst can be unaligned, but not both */ | |
762 | if ((unsigned long)src & 3) { | |
763 | while (words--) { | |
764 | *dst++ = swahw32(get_unaligned(src)); | |
765 | src++; | |
766 | } | |
767 | } else if ((unsigned long)dst & 3) { | |
768 | while (words--) { | |
769 | put_unaligned(swahw32(*src++), dst); | |
770 | dst++; | |
771 | } | |
772 | } else { | |
773 | while (words--) | |
774 | *dst++ = swahw32(*src++); | |
775 | } | |
776 | } | |
777 | ||
778 | static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) | |
779 | { | |
780 | memcpy(dst, src, words * 4); | |
781 | } | |
782 | ||
1bd6363b GU |
783 | static int sh_msiof_transfer_one(struct spi_master *master, |
784 | struct spi_device *spi, | |
785 | struct spi_transfer *t) | |
8051effc | 786 | { |
1bd6363b | 787 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
b0d0ce8b | 788 | void (*copy32)(u32 *, const u32 *, unsigned int); |
8051effc MD |
789 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
790 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
0312d591 GU |
791 | const void *tx_buf = t->tx_buf; |
792 | void *rx_buf = t->rx_buf; | |
793 | unsigned int len = t->len; | |
794 | unsigned int bits = t->bits_per_word; | |
795 | unsigned int bytes_per_word; | |
796 | unsigned int words; | |
8051effc | 797 | int n; |
9dabb3f3 | 798 | bool swab; |
b0d0ce8b GU |
799 | int ret; |
800 | ||
801 | /* setup clocks (clock already enabled in chipselect()) */ | |
802 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); | |
803 | ||
804 | while (master->dma_tx && len > 15) { | |
805 | /* | |
806 | * DMA supports 32-bit words only, hence pack 8-bit and 16-bit | |
807 | * words, with byte resp. word swapping. | |
808 | */ | |
809 | unsigned int l = min(len, MAX_WDLEN * 4); | |
810 | ||
811 | if (bits <= 8) { | |
812 | if (l & 3) | |
813 | break; | |
814 | copy32 = copy_bswap32; | |
815 | } else if (bits <= 16) { | |
816 | if (l & 1) | |
817 | break; | |
818 | copy32 = copy_wswap32; | |
819 | } else { | |
820 | copy32 = copy_plain32; | |
821 | } | |
822 | ||
823 | if (tx_buf) | |
824 | copy32(p->tx_dma_page, tx_buf, l / 4); | |
8051effc | 825 | |
b0d0ce8b | 826 | ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); |
279d2378 GU |
827 | if (ret == -EAGAIN) { |
828 | pr_warn_once("%s %s: DMA not available, falling back to PIO\n", | |
829 | dev_driver_string(&p->pdev->dev), | |
830 | dev_name(&p->pdev->dev)); | |
831 | break; | |
832 | } | |
b0d0ce8b GU |
833 | if (ret) |
834 | return ret; | |
835 | ||
836 | if (rx_buf) { | |
837 | copy32(rx_buf, p->rx_dma_page, l / 4); | |
838 | rx_buf += l; | |
839 | } | |
840 | if (tx_buf) | |
841 | tx_buf += l; | |
842 | ||
843 | len -= l; | |
844 | if (!len) | |
845 | return 0; | |
846 | } | |
8051effc | 847 | |
0312d591 | 848 | if (bits <= 8 && len > 15 && !(len & 3)) { |
9dabb3f3 GL |
849 | bits = 32; |
850 | swab = true; | |
851 | } else { | |
852 | swab = false; | |
853 | } | |
854 | ||
8051effc MD |
855 | /* setup bytes per word and fifo read/write functions */ |
856 | if (bits <= 8) { | |
857 | bytes_per_word = 1; | |
858 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
859 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
860 | } else if (bits <= 16) { | |
861 | bytes_per_word = 2; | |
0312d591 | 862 | if ((unsigned long)tx_buf & 0x01) |
8051effc MD |
863 | tx_fifo = sh_msiof_spi_write_fifo_16u; |
864 | else | |
865 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
866 | ||
0312d591 | 867 | if ((unsigned long)rx_buf & 0x01) |
8051effc MD |
868 | rx_fifo = sh_msiof_spi_read_fifo_16u; |
869 | else | |
870 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
871 | } else if (swab) { |
872 | bytes_per_word = 4; | |
0312d591 | 873 | if ((unsigned long)tx_buf & 0x03) |
9dabb3f3 GL |
874 | tx_fifo = sh_msiof_spi_write_fifo_s32u; |
875 | else | |
876 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
877 | ||
0312d591 | 878 | if ((unsigned long)rx_buf & 0x03) |
9dabb3f3 GL |
879 | rx_fifo = sh_msiof_spi_read_fifo_s32u; |
880 | else | |
881 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
882 | } else { |
883 | bytes_per_word = 4; | |
0312d591 | 884 | if ((unsigned long)tx_buf & 0x03) |
8051effc MD |
885 | tx_fifo = sh_msiof_spi_write_fifo_32u; |
886 | else | |
887 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
888 | ||
0312d591 | 889 | if ((unsigned long)rx_buf & 0x03) |
8051effc MD |
890 | rx_fifo = sh_msiof_spi_read_fifo_32u; |
891 | else | |
892 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
893 | } | |
894 | ||
8051effc | 895 | /* transfer in fifo sized chunks */ |
0312d591 GU |
896 | words = len / bytes_per_word; |
897 | ||
898 | while (words > 0) { | |
899 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, | |
8051effc MD |
900 | words, bits); |
901 | if (n < 0) | |
75b82e23 | 902 | return n; |
8051effc | 903 | |
0312d591 GU |
904 | if (tx_buf) |
905 | tx_buf += n * bytes_per_word; | |
906 | if (rx_buf) | |
907 | rx_buf += n * bytes_per_word; | |
8051effc MD |
908 | words -= n; |
909 | } | |
910 | ||
8051effc MD |
911 | return 0; |
912 | } | |
913 | ||
50a7e23f GU |
914 | static const struct sh_msiof_chipdata sh_data = { |
915 | .tx_fifo_size = 64, | |
916 | .rx_fifo_size = 64, | |
beb74bb0 GU |
917 | .master_flags = 0, |
918 | }; | |
919 | ||
920 | static const struct sh_msiof_chipdata r8a779x_data = { | |
921 | .tx_fifo_size = 64, | |
922 | .rx_fifo_size = 256, | |
923 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
924 | }; |
925 | ||
926 | static const struct of_device_id sh_msiof_match[] = { | |
927 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
928 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
929 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
930 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
50a7e23f GU |
931 | {}, |
932 | }; | |
933 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
934 | ||
cf9c86ef BH |
935 | #ifdef CONFIG_OF |
936 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
937 | { | |
938 | struct sh_msiof_spi_info *info; | |
939 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 940 | u32 num_cs = 1; |
cf9c86ef BH |
941 | |
942 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 943 | if (!info) |
cf9c86ef | 944 | return NULL; |
cf9c86ef BH |
945 | |
946 | /* Parse the MSIOF properties */ | |
947 | of_property_read_u32(np, "num-cs", &num_cs); | |
948 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
949 | &info->tx_fifo_override); | |
950 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
951 | &info->rx_fifo_override); | |
952 | ||
953 | info->num_chipselect = num_cs; | |
954 | ||
955 | return info; | |
956 | } | |
957 | #else | |
958 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
959 | { | |
960 | return NULL; | |
961 | } | |
962 | #endif | |
963 | ||
b0d0ce8b GU |
964 | static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, |
965 | enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) | |
966 | { | |
967 | dma_cap_mask_t mask; | |
968 | struct dma_chan *chan; | |
969 | struct dma_slave_config cfg; | |
970 | int ret; | |
971 | ||
972 | dma_cap_zero(mask); | |
973 | dma_cap_set(DMA_SLAVE, mask); | |
974 | ||
a6be4de6 GU |
975 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
976 | (void *)(unsigned long)id, dev, | |
977 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
b0d0ce8b | 978 | if (!chan) { |
a6be4de6 | 979 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
b0d0ce8b GU |
980 | return NULL; |
981 | } | |
982 | ||
983 | memset(&cfg, 0, sizeof(cfg)); | |
984 | cfg.slave_id = id; | |
985 | cfg.direction = dir; | |
52fba2b8 | 986 | if (dir == DMA_MEM_TO_DEV) { |
b0d0ce8b | 987 | cfg.dst_addr = port_addr; |
52fba2b8 GU |
988 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
989 | } else { | |
b0d0ce8b | 990 | cfg.src_addr = port_addr; |
52fba2b8 GU |
991 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
992 | } | |
b0d0ce8b GU |
993 | |
994 | ret = dmaengine_slave_config(chan, &cfg); | |
995 | if (ret) { | |
996 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
997 | dma_release_channel(chan); | |
998 | return NULL; | |
999 | } | |
1000 | ||
1001 | return chan; | |
1002 | } | |
1003 | ||
1004 | static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) | |
1005 | { | |
1006 | struct platform_device *pdev = p->pdev; | |
1007 | struct device *dev = &pdev->dev; | |
1008 | const struct sh_msiof_spi_info *info = dev_get_platdata(dev); | |
a6be4de6 | 1009 | unsigned int dma_tx_id, dma_rx_id; |
b0d0ce8b GU |
1010 | const struct resource *res; |
1011 | struct spi_master *master; | |
5dabcf2f | 1012 | struct device *tx_dev, *rx_dev; |
b0d0ce8b | 1013 | |
a6be4de6 GU |
1014 | if (dev->of_node) { |
1015 | /* In the OF case we will get the slave IDs from the DT */ | |
1016 | dma_tx_id = 0; | |
1017 | dma_rx_id = 0; | |
1018 | } else if (info && info->dma_tx_id && info->dma_rx_id) { | |
1019 | dma_tx_id = info->dma_tx_id; | |
1020 | dma_rx_id = info->dma_rx_id; | |
1021 | } else { | |
1022 | /* The driver assumes no error */ | |
1023 | return 0; | |
1024 | } | |
b0d0ce8b GU |
1025 | |
1026 | /* The DMA engine uses the second register set, if present */ | |
1027 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1028 | if (!res) | |
1029 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1030 | ||
1031 | master = p->master; | |
1032 | master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, | |
a6be4de6 | 1033 | dma_tx_id, |
b0d0ce8b GU |
1034 | res->start + TFDR); |
1035 | if (!master->dma_tx) | |
1036 | return -ENODEV; | |
1037 | ||
1038 | master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, | |
a6be4de6 | 1039 | dma_rx_id, |
b0d0ce8b GU |
1040 | res->start + RFDR); |
1041 | if (!master->dma_rx) | |
1042 | goto free_tx_chan; | |
1043 | ||
1044 | p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1045 | if (!p->tx_dma_page) | |
1046 | goto free_rx_chan; | |
1047 | ||
1048 | p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1049 | if (!p->rx_dma_page) | |
1050 | goto free_tx_page; | |
1051 | ||
5dabcf2f GU |
1052 | tx_dev = master->dma_tx->device->dev; |
1053 | p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1054 | DMA_TO_DEVICE); |
5dabcf2f | 1055 | if (dma_mapping_error(tx_dev, p->tx_dma_addr)) |
b0d0ce8b GU |
1056 | goto free_rx_page; |
1057 | ||
5dabcf2f GU |
1058 | rx_dev = master->dma_rx->device->dev; |
1059 | p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1060 | DMA_FROM_DEVICE); |
5dabcf2f | 1061 | if (dma_mapping_error(rx_dev, p->rx_dma_addr)) |
b0d0ce8b GU |
1062 | goto unmap_tx_page; |
1063 | ||
1064 | dev_info(dev, "DMA available"); | |
1065 | return 0; | |
1066 | ||
1067 | unmap_tx_page: | |
5dabcf2f | 1068 | dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); |
b0d0ce8b GU |
1069 | free_rx_page: |
1070 | free_page((unsigned long)p->rx_dma_page); | |
1071 | free_tx_page: | |
1072 | free_page((unsigned long)p->tx_dma_page); | |
1073 | free_rx_chan: | |
1074 | dma_release_channel(master->dma_rx); | |
1075 | free_tx_chan: | |
1076 | dma_release_channel(master->dma_tx); | |
1077 | master->dma_tx = NULL; | |
1078 | return -ENODEV; | |
1079 | } | |
1080 | ||
1081 | static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) | |
1082 | { | |
1083 | struct spi_master *master = p->master; | |
1084 | struct device *dev; | |
1085 | ||
1086 | if (!master->dma_tx) | |
1087 | return; | |
1088 | ||
1089 | dev = &p->pdev->dev; | |
5dabcf2f GU |
1090 | dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, |
1091 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1092 | dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, | |
1093 | PAGE_SIZE, DMA_TO_DEVICE); | |
b0d0ce8b GU |
1094 | free_page((unsigned long)p->rx_dma_page); |
1095 | free_page((unsigned long)p->tx_dma_page); | |
1096 | dma_release_channel(master->dma_rx); | |
1097 | dma_release_channel(master->dma_tx); | |
1098 | } | |
1099 | ||
8051effc MD |
1100 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
1101 | { | |
1102 | struct resource *r; | |
1103 | struct spi_master *master; | |
50a7e23f | 1104 | const struct of_device_id *of_id; |
8051effc | 1105 | struct sh_msiof_spi_priv *p; |
8051effc MD |
1106 | int i; |
1107 | int ret; | |
1108 | ||
1109 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
1110 | if (master == NULL) { | |
1111 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 1112 | return -ENOMEM; |
8051effc MD |
1113 | } |
1114 | ||
1115 | p = spi_master_get_devdata(master); | |
1116 | ||
1117 | platform_set_drvdata(pdev, p); | |
b0d0ce8b | 1118 | p->master = master; |
50a7e23f GU |
1119 | |
1120 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
1121 | if (of_id) { | |
1122 | p->chipdata = of_id->data; | |
cf9c86ef | 1123 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
1124 | } else { |
1125 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 1126 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 1127 | } |
cf9c86ef BH |
1128 | |
1129 | if (!p->info) { | |
1130 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
1131 | ret = -ENXIO; | |
1132 | goto err1; | |
1133 | } | |
1134 | ||
8051effc MD |
1135 | init_completion(&p->done); |
1136 | ||
b4dd05de | 1137 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 1138 | if (IS_ERR(p->clk)) { |
078b6ead | 1139 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
1140 | ret = PTR_ERR(p->clk); |
1141 | goto err1; | |
1142 | } | |
1143 | ||
8051effc | 1144 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
1145 | if (i < 0) { |
1146 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 1147 | ret = -ENOENT; |
b4dd05de | 1148 | goto err1; |
8051effc | 1149 | } |
b4dd05de LP |
1150 | |
1151 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1152 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
1153 | if (IS_ERR(p->mapbase)) { | |
1154 | ret = PTR_ERR(p->mapbase); | |
1155 | goto err1; | |
8051effc MD |
1156 | } |
1157 | ||
b4dd05de LP |
1158 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
1159 | dev_name(&pdev->dev), p); | |
8051effc MD |
1160 | if (ret) { |
1161 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 1162 | goto err1; |
8051effc MD |
1163 | } |
1164 | ||
1165 | p->pdev = pdev; | |
1166 | pm_runtime_enable(&pdev->dev); | |
1167 | ||
8051effc | 1168 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
1169 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
1170 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
1171 | if (p->info->tx_fifo_override) |
1172 | p->tx_fifo_size = p->info->tx_fifo_override; | |
1173 | if (p->info->rx_fifo_override) | |
1174 | p->rx_fifo_size = p->info->rx_fifo_override; | |
1175 | ||
1bd6363b | 1176 | /* init master code */ |
8051effc MD |
1177 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1178 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 1179 | master->flags = p->chipdata->master_flags; |
8051effc | 1180 | master->bus_num = pdev->id; |
f7c05e83 | 1181 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 1182 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 1183 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 1184 | master->prepare_message = sh_msiof_prepare_message; |
2416289c | 1185 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 1186 | master->auto_runtime_pm = true; |
1bd6363b | 1187 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 1188 | |
b0d0ce8b GU |
1189 | ret = sh_msiof_request_dma(p); |
1190 | if (ret < 0) | |
1191 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
1192 | ||
1bd6363b GU |
1193 | ret = devm_spi_register_master(&pdev->dev, master); |
1194 | if (ret < 0) { | |
1195 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
1196 | goto err2; | |
1197 | } | |
8051effc | 1198 | |
1bd6363b | 1199 | return 0; |
8051effc | 1200 | |
1bd6363b | 1201 | err2: |
b0d0ce8b | 1202 | sh_msiof_release_dma(p); |
8051effc | 1203 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
1204 | err1: |
1205 | spi_master_put(master); | |
8051effc MD |
1206 | return ret; |
1207 | } | |
1208 | ||
1209 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
1210 | { | |
b0d0ce8b GU |
1211 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); |
1212 | ||
1213 | sh_msiof_release_dma(p); | |
1bd6363b | 1214 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 1215 | return 0; |
8051effc MD |
1216 | } |
1217 | ||
50a7e23f GU |
1218 | static struct platform_device_id spi_driver_ids[] = { |
1219 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
1220 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
1221 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
1222 | {}, |
1223 | }; | |
50a7e23f | 1224 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 1225 | |
8051effc MD |
1226 | static struct platform_driver sh_msiof_spi_drv = { |
1227 | .probe = sh_msiof_spi_probe, | |
1228 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 1229 | .id_table = spi_driver_ids, |
8051effc MD |
1230 | .driver = { |
1231 | .name = "spi_sh_msiof", | |
1232 | .owner = THIS_MODULE, | |
691ee4ed | 1233 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
1234 | }, |
1235 | }; | |
940ab889 | 1236 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
1237 | |
1238 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
1239 | MODULE_AUTHOR("Magnus Damm"); | |
1240 | MODULE_LICENSE("GPL v2"); | |
1241 | MODULE_ALIAS("platform:spi_sh_msiof"); |