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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
b0d0ce8b | 5 | * Copyright (C) 2014 Glider bvba |
8051effc MD |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
e2dbf5eb GL |
13 | #include <linux/bitmap.h> |
14 | #include <linux/clk.h> | |
15 | #include <linux/completion.h> | |
8051effc | 16 | #include <linux/delay.h> |
b0d0ce8b GU |
17 | #include <linux/dma-mapping.h> |
18 | #include <linux/dmaengine.h> | |
e2dbf5eb GL |
19 | #include <linux/err.h> |
20 | #include <linux/gpio.h> | |
8051effc | 21 | #include <linux/interrupt.h> |
e2dbf5eb GL |
22 | #include <linux/io.h> |
23 | #include <linux/kernel.h> | |
d7614de4 | 24 | #include <linux/module.h> |
cf9c86ef | 25 | #include <linux/of.h> |
50a7e23f | 26 | #include <linux/of_device.h> |
8051effc | 27 | #include <linux/platform_device.h> |
8051effc | 28 | #include <linux/pm_runtime.h> |
b0d0ce8b | 29 | #include <linux/sh_dma.h> |
8051effc | 30 | |
e2dbf5eb | 31 | #include <linux/spi/sh_msiof.h> |
8051effc | 32 | #include <linux/spi/spi.h> |
8051effc | 33 | |
8051effc MD |
34 | #include <asm/unaligned.h> |
35 | ||
50a7e23f GU |
36 | |
37 | struct sh_msiof_chipdata { | |
38 | u16 tx_fifo_size; | |
39 | u16 rx_fifo_size; | |
beb74bb0 | 40 | u16 master_flags; |
50a7e23f GU |
41 | }; |
42 | ||
8051effc | 43 | struct sh_msiof_spi_priv { |
b0d0ce8b | 44 | struct spi_master *master; |
8051effc MD |
45 | void __iomem *mapbase; |
46 | struct clk *clk; | |
47 | struct platform_device *pdev; | |
50a7e23f | 48 | const struct sh_msiof_chipdata *chipdata; |
8051effc MD |
49 | struct sh_msiof_spi_info *info; |
50 | struct completion done; | |
8051effc MD |
51 | int tx_fifo_size; |
52 | int rx_fifo_size; | |
b0d0ce8b GU |
53 | void *tx_dma_page; |
54 | void *rx_dma_page; | |
55 | dma_addr_t tx_dma_addr; | |
56 | dma_addr_t rx_dma_addr; | |
8051effc MD |
57 | }; |
58 | ||
01cfef57 GU |
59 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
60 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
61 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
62 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
63 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
64 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
65 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
66 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
67 | #define CTR 0x28 /* Control Register */ | |
68 | #define FCTR 0x30 /* FIFO Control Register */ | |
69 | #define STR 0x40 /* Status Register */ | |
70 | #define IER 0x44 /* Interrupt Enable Register */ | |
71 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
72 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
73 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
74 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
75 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
76 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
77 | ||
78 | /* TMDR1 and RMDR1 */ | |
79 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
80 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
81 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
82 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
83 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
84 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
3110628d YS |
85 | #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ |
86 | #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ | |
6d40530e | 87 | #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ |
01cfef57 GU |
88 | #define MDR1_FLD_SHIFT 2 |
89 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
90 | /* TMDR1 */ | |
91 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
92 | ||
93 | /* TMDR2 and RMDR2 */ | |
94 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
95 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
96 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
97 | ||
b0d0ce8b GU |
98 | #define MAX_WDLEN 256U |
99 | ||
01cfef57 GU |
100 | /* TSCR and RSCR */ |
101 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
102 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
103 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
104 | #define SCR_BRDV_DIV_2 0x0000 | |
105 | #define SCR_BRDV_DIV_4 0x0001 | |
106 | #define SCR_BRDV_DIV_8 0x0002 | |
107 | #define SCR_BRDV_DIV_16 0x0003 | |
108 | #define SCR_BRDV_DIV_32 0x0004 | |
109 | #define SCR_BRDV_DIV_1 0x0007 | |
110 | ||
111 | /* CTR */ | |
112 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
113 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
114 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
115 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
116 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
117 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
118 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
119 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
120 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
121 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
122 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
123 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
124 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
125 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
126 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
127 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
128 | ||
2e2b3687 GU |
129 | /* FCTR */ |
130 | #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ | |
131 | #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ | |
132 | #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ | |
133 | #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ | |
134 | #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ | |
135 | #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ | |
136 | #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ | |
137 | #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ | |
138 | #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ | |
139 | #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ | |
140 | #define FCTR_TFUA_SHIFT 20 | |
141 | #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) | |
142 | #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ | |
143 | #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ | |
144 | #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ | |
145 | #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ | |
146 | #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ | |
147 | #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ | |
148 | #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ | |
149 | #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ | |
150 | #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ | |
151 | #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ | |
152 | #define FCTR_RFUA_SHIFT 4 | |
153 | #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) | |
154 | ||
155 | /* STR */ | |
156 | #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ | |
157 | #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ | |
01cfef57 | 158 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ |
2e2b3687 GU |
159 | #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ |
160 | #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ | |
161 | #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ | |
162 | #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ | |
163 | #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ | |
01cfef57 | 164 | #define STR_REOF 0x00000080 /* Frame Reception End */ |
2e2b3687 GU |
165 | #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ |
166 | #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ | |
167 | #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ | |
168 | ||
169 | /* IER */ | |
170 | #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ | |
171 | #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ | |
172 | #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ | |
173 | #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ | |
174 | #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ | |
175 | #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ | |
176 | #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ | |
177 | #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ | |
178 | #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ | |
179 | #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ | |
180 | #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ | |
181 | #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ | |
182 | #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ | |
183 | #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ | |
01cfef57 | 184 | |
8051effc | 185 | |
e2dbf5eb | 186 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
187 | { |
188 | switch (reg_offs) { | |
189 | case TSCR: | |
190 | case RSCR: | |
191 | return ioread16(p->mapbase + reg_offs); | |
192 | default: | |
193 | return ioread32(p->mapbase + reg_offs); | |
194 | } | |
195 | } | |
196 | ||
197 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 198 | u32 value) |
8051effc MD |
199 | { |
200 | switch (reg_offs) { | |
201 | case TSCR: | |
202 | case RSCR: | |
203 | iowrite16(value, p->mapbase + reg_offs); | |
204 | break; | |
205 | default: | |
206 | iowrite32(value, p->mapbase + reg_offs); | |
207 | break; | |
208 | } | |
209 | } | |
210 | ||
211 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 212 | u32 clr, u32 set) |
8051effc | 213 | { |
e2dbf5eb GL |
214 | u32 mask = clr | set; |
215 | u32 data; | |
8051effc MD |
216 | int k; |
217 | ||
218 | data = sh_msiof_read(p, CTR); | |
219 | data &= ~clr; | |
220 | data |= set; | |
221 | sh_msiof_write(p, CTR, data); | |
222 | ||
223 | for (k = 100; k > 0; k--) { | |
224 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
225 | break; | |
226 | ||
227 | udelay(10); | |
228 | } | |
229 | ||
230 | return k > 0 ? 0 : -ETIMEDOUT; | |
231 | } | |
232 | ||
233 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
234 | { | |
235 | struct sh_msiof_spi_priv *p = data; | |
236 | ||
237 | /* just disable the interrupt and wake up */ | |
238 | sh_msiof_write(p, IER, 0); | |
239 | complete(&p->done); | |
240 | ||
241 | return IRQ_HANDLED; | |
242 | } | |
243 | ||
244 | static struct { | |
245 | unsigned short div; | |
246 | unsigned short scr; | |
247 | } const sh_msiof_spi_clk_table[] = { | |
01cfef57 GU |
248 | { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, |
249 | { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, | |
250 | { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, | |
251 | { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, | |
252 | { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, | |
253 | { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, | |
254 | { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, | |
255 | { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, | |
256 | { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, | |
257 | { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, | |
258 | { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, | |
8051effc MD |
259 | }; |
260 | ||
261 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 262 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
263 | { |
264 | unsigned long div = 1024; | |
265 | size_t k; | |
266 | ||
267 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 268 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc MD |
269 | |
270 | /* TODO: make more fine grained */ | |
271 | ||
272 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { | |
273 | if (sh_msiof_spi_clk_table[k].div >= div) | |
274 | break; | |
275 | } | |
276 | ||
277 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); | |
278 | ||
279 | sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); | |
beb74bb0 GU |
280 | if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
281 | sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); | |
8051effc MD |
282 | } |
283 | ||
3110628d YS |
284 | static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) |
285 | { | |
286 | /* | |
287 | * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl | |
288 | * b'000 : 0 | |
289 | * b'001 : 100 | |
290 | * b'010 : 200 | |
291 | * b'011 (SYNCDL only) : 300 | |
292 | * b'101 : 50 | |
293 | * b'110 : 150 | |
294 | */ | |
295 | if (dtdl_or_syncdl % 100) | |
296 | return dtdl_or_syncdl / 100 + 5; | |
297 | else | |
298 | return dtdl_or_syncdl / 100; | |
299 | } | |
300 | ||
301 | static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) | |
302 | { | |
303 | u32 val; | |
304 | ||
305 | if (!p->info) | |
306 | return 0; | |
307 | ||
308 | /* check if DTDL and SYNCDL is allowed value */ | |
309 | if (p->info->dtdl > 200 || p->info->syncdl > 300) { | |
310 | dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); | |
311 | return 0; | |
312 | } | |
313 | ||
314 | /* check if the sum of DTDL and SYNCDL becomes an integer value */ | |
315 | if ((p->info->dtdl + p->info->syncdl) % 100) { | |
316 | dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; | |
321 | val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; | |
322 | ||
323 | return val; | |
324 | } | |
325 | ||
8051effc | 326 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, |
e2dbf5eb | 327 | u32 cpol, u32 cpha, |
50a77998 | 328 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 329 | { |
e2dbf5eb | 330 | u32 tmp; |
8051effc MD |
331 | int edge; |
332 | ||
333 | /* | |
e8708ef7 MP |
334 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
335 | * 0 0 10 10 1 1 | |
336 | * 0 1 10 10 0 0 | |
337 | * 1 0 11 11 0 0 | |
338 | * 1 1 11 11 1 1 | |
8051effc | 339 | */ |
01cfef57 GU |
340 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
341 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
342 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
3110628d | 343 | tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); |
01cfef57 | 344 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); |
beb74bb0 GU |
345 | if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { |
346 | /* These bits are reserved if RX needs TX */ | |
347 | tmp &= ~0x0000ffff; | |
348 | } | |
01cfef57 | 349 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 350 | |
01cfef57 GU |
351 | tmp = 0; |
352 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
353 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 354 | |
e2dbf5eb | 355 | edge = cpol ^ !cpha; |
8051effc | 356 | |
01cfef57 GU |
357 | tmp |= edge << CTR_TEDG_SHIFT; |
358 | tmp |= edge << CTR_REDG_SHIFT; | |
359 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
360 | sh_msiof_write(p, CTR, tmp); |
361 | } | |
362 | ||
363 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
364 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 365 | u32 bits, u32 words) |
8051effc | 366 | { |
01cfef57 | 367 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 368 | |
beb74bb0 | 369 | if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
370 | sh_msiof_write(p, TMDR2, dr2); |
371 | else | |
01cfef57 | 372 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
373 | |
374 | if (rx_buf) | |
375 | sh_msiof_write(p, RMDR2, dr2); | |
8051effc MD |
376 | } |
377 | ||
378 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
379 | { | |
380 | sh_msiof_write(p, STR, sh_msiof_read(p, STR)); | |
381 | } | |
382 | ||
383 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
384 | const void *tx_buf, int words, int fs) | |
385 | { | |
e2dbf5eb | 386 | const u8 *buf_8 = tx_buf; |
8051effc MD |
387 | int k; |
388 | ||
389 | for (k = 0; k < words; k++) | |
390 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
391 | } | |
392 | ||
393 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
394 | const void *tx_buf, int words, int fs) | |
395 | { | |
e2dbf5eb | 396 | const u16 *buf_16 = tx_buf; |
8051effc MD |
397 | int k; |
398 | ||
399 | for (k = 0; k < words; k++) | |
400 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
401 | } | |
402 | ||
403 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
404 | const void *tx_buf, int words, int fs) | |
405 | { | |
e2dbf5eb | 406 | const u16 *buf_16 = tx_buf; |
8051effc MD |
407 | int k; |
408 | ||
409 | for (k = 0; k < words; k++) | |
410 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
411 | } | |
412 | ||
413 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
414 | const void *tx_buf, int words, int fs) | |
415 | { | |
e2dbf5eb | 416 | const u32 *buf_32 = tx_buf; |
8051effc MD |
417 | int k; |
418 | ||
419 | for (k = 0; k < words; k++) | |
420 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
421 | } | |
422 | ||
423 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
424 | const void *tx_buf, int words, int fs) | |
425 | { | |
e2dbf5eb | 426 | const u32 *buf_32 = tx_buf; |
8051effc MD |
427 | int k; |
428 | ||
429 | for (k = 0; k < words; k++) | |
430 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
431 | } | |
432 | ||
9dabb3f3 GL |
433 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
434 | const void *tx_buf, int words, int fs) | |
435 | { | |
436 | const u32 *buf_32 = tx_buf; | |
437 | int k; | |
438 | ||
439 | for (k = 0; k < words; k++) | |
440 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
441 | } | |
442 | ||
443 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
444 | const void *tx_buf, int words, int fs) | |
445 | { | |
446 | const u32 *buf_32 = tx_buf; | |
447 | int k; | |
448 | ||
449 | for (k = 0; k < words; k++) | |
450 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
451 | } | |
452 | ||
8051effc MD |
453 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
454 | void *rx_buf, int words, int fs) | |
455 | { | |
e2dbf5eb | 456 | u8 *buf_8 = rx_buf; |
8051effc MD |
457 | int k; |
458 | ||
459 | for (k = 0; k < words; k++) | |
460 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
461 | } | |
462 | ||
463 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
464 | void *rx_buf, int words, int fs) | |
465 | { | |
e2dbf5eb | 466 | u16 *buf_16 = rx_buf; |
8051effc MD |
467 | int k; |
468 | ||
469 | for (k = 0; k < words; k++) | |
470 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
471 | } | |
472 | ||
473 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
474 | void *rx_buf, int words, int fs) | |
475 | { | |
e2dbf5eb | 476 | u16 *buf_16 = rx_buf; |
8051effc MD |
477 | int k; |
478 | ||
479 | for (k = 0; k < words; k++) | |
480 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
481 | } | |
482 | ||
483 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
484 | void *rx_buf, int words, int fs) | |
485 | { | |
e2dbf5eb | 486 | u32 *buf_32 = rx_buf; |
8051effc MD |
487 | int k; |
488 | ||
489 | for (k = 0; k < words; k++) | |
490 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
491 | } | |
492 | ||
493 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
494 | void *rx_buf, int words, int fs) | |
495 | { | |
e2dbf5eb | 496 | u32 *buf_32 = rx_buf; |
8051effc MD |
497 | int k; |
498 | ||
499 | for (k = 0; k < words; k++) | |
500 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
501 | } | |
502 | ||
9dabb3f3 GL |
503 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
504 | void *rx_buf, int words, int fs) | |
505 | { | |
506 | u32 *buf_32 = rx_buf; | |
507 | int k; | |
508 | ||
509 | for (k = 0; k < words; k++) | |
510 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
511 | } | |
512 | ||
513 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
514 | void *rx_buf, int words, int fs) | |
515 | { | |
516 | u32 *buf_32 = rx_buf; | |
517 | int k; | |
518 | ||
519 | for (k = 0; k < words; k++) | |
520 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
521 | } | |
522 | ||
8d19534a | 523 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 524 | { |
8d19534a | 525 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 526 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8051effc | 527 | |
01576056 HN |
528 | pm_runtime_get_sync(&p->pdev->dev); |
529 | ||
8d19534a GU |
530 | if (!np) { |
531 | /* | |
532 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
533 | * if any. otherwise let HW control CS | |
534 | */ | |
535 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
536 | } | |
8051effc | 537 | |
c833ff73 GU |
538 | /* Configure pins before deasserting CS */ |
539 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
540 | !!(spi->mode & SPI_CPHA), | |
541 | !!(spi->mode & SPI_3WIRE), | |
542 | !!(spi->mode & SPI_LSB_FIRST), | |
543 | !!(spi->mode & SPI_CS_HIGH)); | |
8051effc | 544 | |
1bd6363b GU |
545 | if (spi->cs_gpio >= 0) |
546 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); | |
8051effc | 547 | |
01576056 | 548 | |
c8935ef0 | 549 | pm_runtime_put(&p->pdev->dev); |
01576056 | 550 | |
1bd6363b | 551 | return 0; |
8051effc MD |
552 | } |
553 | ||
c833ff73 GU |
554 | static int sh_msiof_prepare_message(struct spi_master *master, |
555 | struct spi_message *msg) | |
8051effc | 556 | { |
c833ff73 GU |
557 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
558 | const struct spi_device *spi = msg->spi; | |
8051effc | 559 | |
c833ff73 GU |
560 | /* Configure pins before asserting CS */ |
561 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
562 | !!(spi->mode & SPI_CPHA), | |
563 | !!(spi->mode & SPI_3WIRE), | |
564 | !!(spi->mode & SPI_LSB_FIRST), | |
565 | !!(spi->mode & SPI_CS_HIGH)); | |
566 | return 0; | |
8051effc MD |
567 | } |
568 | ||
76c02e71 GU |
569 | static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) |
570 | { | |
571 | int ret; | |
572 | ||
573 | /* setup clock and rx/tx signals */ | |
574 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
575 | if (rx_buf && !ret) | |
576 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
577 | if (!ret) | |
578 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
579 | ||
580 | /* start by setting frame bit */ | |
581 | if (!ret) | |
582 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); | |
583 | ||
584 | return ret; | |
585 | } | |
586 | ||
587 | static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) | |
588 | { | |
589 | int ret; | |
590 | ||
591 | /* shut down frame, rx/tx and clock signals */ | |
592 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
593 | if (!ret) | |
594 | ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
595 | if (rx_buf && !ret) | |
596 | ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
597 | if (!ret) | |
598 | ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); | |
599 | ||
600 | return ret; | |
601 | } | |
602 | ||
8051effc MD |
603 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
604 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
605 | const void *, int, int), | |
606 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
607 | void *, int, int), | |
608 | const void *tx_buf, void *rx_buf, | |
609 | int words, int bits) | |
610 | { | |
611 | int fifo_shift; | |
612 | int ret; | |
613 | ||
614 | /* limit maximum word transfer to rx/tx fifo size */ | |
615 | if (tx_buf) | |
616 | words = min_t(int, words, p->tx_fifo_size); | |
617 | if (rx_buf) | |
618 | words = min_t(int, words, p->rx_fifo_size); | |
619 | ||
620 | /* the fifo contents need shifting */ | |
621 | fifo_shift = 32 - bits; | |
622 | ||
b0d0ce8b GU |
623 | /* default FIFO watermarks for PIO */ |
624 | sh_msiof_write(p, FCTR, 0); | |
625 | ||
8051effc MD |
626 | /* setup msiof transfer mode registers */ |
627 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
b0d0ce8b | 628 | sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); |
8051effc MD |
629 | |
630 | /* write tx fifo */ | |
631 | if (tx_buf) | |
632 | tx_fifo(p, tx_buf, words, fifo_shift); | |
633 | ||
16735d02 | 634 | reinit_completion(&p->done); |
76c02e71 GU |
635 | |
636 | ret = sh_msiof_spi_start(p, rx_buf); | |
8051effc MD |
637 | if (ret) { |
638 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
75b82e23 | 639 | goto stop_ier; |
8051effc MD |
640 | } |
641 | ||
642 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
75b82e23 GU |
643 | ret = wait_for_completion_timeout(&p->done, HZ); |
644 | if (!ret) { | |
645 | dev_err(&p->pdev->dev, "PIO timeout\n"); | |
646 | ret = -ETIMEDOUT; | |
647 | goto stop_reset; | |
648 | } | |
8051effc MD |
649 | |
650 | /* read rx fifo */ | |
651 | if (rx_buf) | |
652 | rx_fifo(p, rx_buf, words, fifo_shift); | |
653 | ||
654 | /* clear status bits */ | |
655 | sh_msiof_reset_str(p); | |
656 | ||
76c02e71 | 657 | ret = sh_msiof_spi_stop(p, rx_buf); |
8051effc MD |
658 | if (ret) { |
659 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
75b82e23 | 660 | return ret; |
8051effc MD |
661 | } |
662 | ||
663 | return words; | |
664 | ||
75b82e23 GU |
665 | stop_reset: |
666 | sh_msiof_reset_str(p); | |
667 | sh_msiof_spi_stop(p, rx_buf); | |
668 | stop_ier: | |
8051effc MD |
669 | sh_msiof_write(p, IER, 0); |
670 | return ret; | |
671 | } | |
672 | ||
b0d0ce8b GU |
673 | static void sh_msiof_dma_complete(void *arg) |
674 | { | |
675 | struct sh_msiof_spi_priv *p = arg; | |
676 | ||
677 | sh_msiof_write(p, IER, 0); | |
678 | complete(&p->done); | |
679 | } | |
680 | ||
681 | static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, | |
682 | void *rx, unsigned int len) | |
683 | { | |
684 | u32 ier_bits = 0; | |
685 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; | |
686 | dma_cookie_t cookie; | |
687 | int ret; | |
688 | ||
3e81b592 | 689 | /* First prepare and submit the DMA request(s), as this may fail */ |
b0d0ce8b GU |
690 | if (rx) { |
691 | ier_bits |= IER_RDREQE | IER_RDMAE; | |
692 | desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, | |
693 | p->rx_dma_addr, len, DMA_FROM_DEVICE, | |
694 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
a5e7c719 GU |
695 | if (!desc_rx) |
696 | return -EAGAIN; | |
b0d0ce8b | 697 | |
b0d0ce8b GU |
698 | desc_rx->callback = sh_msiof_dma_complete; |
699 | desc_rx->callback_param = p; | |
700 | cookie = dmaengine_submit(desc_rx); | |
a5e7c719 GU |
701 | if (dma_submit_error(cookie)) |
702 | return cookie; | |
b0d0ce8b GU |
703 | } |
704 | ||
705 | if (tx) { | |
3e81b592 GU |
706 | ier_bits |= IER_TDREQE | IER_TDMAE; |
707 | dma_sync_single_for_device(p->master->dma_tx->device->dev, | |
708 | p->tx_dma_addr, len, DMA_TO_DEVICE); | |
709 | desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, | |
710 | p->tx_dma_addr, len, DMA_TO_DEVICE, | |
711 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
712 | if (!desc_tx) { | |
713 | ret = -EAGAIN; | |
714 | goto no_dma_tx; | |
715 | } | |
716 | ||
b0d0ce8b GU |
717 | if (rx) { |
718 | /* No callback */ | |
719 | desc_tx->callback = NULL; | |
720 | } else { | |
721 | desc_tx->callback = sh_msiof_dma_complete; | |
722 | desc_tx->callback_param = p; | |
723 | } | |
724 | cookie = dmaengine_submit(desc_tx); | |
725 | if (dma_submit_error(cookie)) { | |
726 | ret = cookie; | |
3e81b592 | 727 | goto no_dma_tx; |
b0d0ce8b | 728 | } |
b0d0ce8b GU |
729 | } |
730 | ||
3e81b592 GU |
731 | /* 1 stage FIFO watermarks for DMA */ |
732 | sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); | |
733 | ||
734 | /* setup msiof transfer mode registers (32-bit words) */ | |
735 | sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); | |
736 | ||
737 | sh_msiof_write(p, IER, ier_bits); | |
738 | ||
739 | reinit_completion(&p->done); | |
740 | ||
741 | /* Now start DMA */ | |
3e81b592 | 742 | if (rx) |
7a9f957b GU |
743 | dma_async_issue_pending(p->master->dma_rx); |
744 | if (tx) | |
3e81b592 GU |
745 | dma_async_issue_pending(p->master->dma_tx); |
746 | ||
b0d0ce8b GU |
747 | ret = sh_msiof_spi_start(p, rx); |
748 | if (ret) { | |
749 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
3e81b592 | 750 | goto stop_dma; |
b0d0ce8b GU |
751 | } |
752 | ||
753 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
754 | ret = wait_for_completion_timeout(&p->done, HZ); | |
755 | if (!ret) { | |
756 | dev_err(&p->pdev->dev, "DMA timeout\n"); | |
757 | ret = -ETIMEDOUT; | |
758 | goto stop_reset; | |
759 | } | |
760 | ||
761 | /* clear status bits */ | |
762 | sh_msiof_reset_str(p); | |
763 | ||
764 | ret = sh_msiof_spi_stop(p, rx); | |
765 | if (ret) { | |
766 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
767 | return ret; | |
768 | } | |
769 | ||
770 | if (rx) | |
5dabcf2f GU |
771 | dma_sync_single_for_cpu(p->master->dma_rx->device->dev, |
772 | p->rx_dma_addr, len, | |
b0d0ce8b GU |
773 | DMA_FROM_DEVICE); |
774 | ||
775 | return 0; | |
776 | ||
777 | stop_reset: | |
778 | sh_msiof_reset_str(p); | |
779 | sh_msiof_spi_stop(p, rx); | |
3e81b592 | 780 | stop_dma: |
b0d0ce8b GU |
781 | if (tx) |
782 | dmaengine_terminate_all(p->master->dma_tx); | |
3e81b592 | 783 | no_dma_tx: |
b0d0ce8b GU |
784 | if (rx) |
785 | dmaengine_terminate_all(p->master->dma_rx); | |
b0d0ce8b GU |
786 | sh_msiof_write(p, IER, 0); |
787 | return ret; | |
788 | } | |
789 | ||
790 | static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) | |
791 | { | |
792 | /* src or dst can be unaligned, but not both */ | |
793 | if ((unsigned long)src & 3) { | |
794 | while (words--) { | |
795 | *dst++ = swab32(get_unaligned(src)); | |
796 | src++; | |
797 | } | |
798 | } else if ((unsigned long)dst & 3) { | |
799 | while (words--) { | |
800 | put_unaligned(swab32(*src++), dst); | |
801 | dst++; | |
802 | } | |
803 | } else { | |
804 | while (words--) | |
805 | *dst++ = swab32(*src++); | |
806 | } | |
807 | } | |
808 | ||
809 | static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) | |
810 | { | |
811 | /* src or dst can be unaligned, but not both */ | |
812 | if ((unsigned long)src & 3) { | |
813 | while (words--) { | |
814 | *dst++ = swahw32(get_unaligned(src)); | |
815 | src++; | |
816 | } | |
817 | } else if ((unsigned long)dst & 3) { | |
818 | while (words--) { | |
819 | put_unaligned(swahw32(*src++), dst); | |
820 | dst++; | |
821 | } | |
822 | } else { | |
823 | while (words--) | |
824 | *dst++ = swahw32(*src++); | |
825 | } | |
826 | } | |
827 | ||
828 | static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) | |
829 | { | |
830 | memcpy(dst, src, words * 4); | |
831 | } | |
832 | ||
1bd6363b GU |
833 | static int sh_msiof_transfer_one(struct spi_master *master, |
834 | struct spi_device *spi, | |
835 | struct spi_transfer *t) | |
8051effc | 836 | { |
1bd6363b | 837 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
b0d0ce8b | 838 | void (*copy32)(u32 *, const u32 *, unsigned int); |
8051effc MD |
839 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
840 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
0312d591 GU |
841 | const void *tx_buf = t->tx_buf; |
842 | void *rx_buf = t->rx_buf; | |
843 | unsigned int len = t->len; | |
844 | unsigned int bits = t->bits_per_word; | |
845 | unsigned int bytes_per_word; | |
846 | unsigned int words; | |
8051effc | 847 | int n; |
9dabb3f3 | 848 | bool swab; |
b0d0ce8b GU |
849 | int ret; |
850 | ||
851 | /* setup clocks (clock already enabled in chipselect()) */ | |
852 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); | |
853 | ||
854 | while (master->dma_tx && len > 15) { | |
855 | /* | |
856 | * DMA supports 32-bit words only, hence pack 8-bit and 16-bit | |
857 | * words, with byte resp. word swapping. | |
858 | */ | |
859 | unsigned int l = min(len, MAX_WDLEN * 4); | |
860 | ||
861 | if (bits <= 8) { | |
862 | if (l & 3) | |
863 | break; | |
864 | copy32 = copy_bswap32; | |
865 | } else if (bits <= 16) { | |
866 | if (l & 1) | |
867 | break; | |
868 | copy32 = copy_wswap32; | |
869 | } else { | |
870 | copy32 = copy_plain32; | |
871 | } | |
872 | ||
873 | if (tx_buf) | |
874 | copy32(p->tx_dma_page, tx_buf, l / 4); | |
8051effc | 875 | |
b0d0ce8b | 876 | ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); |
279d2378 GU |
877 | if (ret == -EAGAIN) { |
878 | pr_warn_once("%s %s: DMA not available, falling back to PIO\n", | |
879 | dev_driver_string(&p->pdev->dev), | |
880 | dev_name(&p->pdev->dev)); | |
881 | break; | |
882 | } | |
b0d0ce8b GU |
883 | if (ret) |
884 | return ret; | |
885 | ||
886 | if (rx_buf) { | |
887 | copy32(rx_buf, p->rx_dma_page, l / 4); | |
888 | rx_buf += l; | |
889 | } | |
890 | if (tx_buf) | |
891 | tx_buf += l; | |
892 | ||
893 | len -= l; | |
894 | if (!len) | |
895 | return 0; | |
896 | } | |
8051effc | 897 | |
0312d591 | 898 | if (bits <= 8 && len > 15 && !(len & 3)) { |
9dabb3f3 GL |
899 | bits = 32; |
900 | swab = true; | |
901 | } else { | |
902 | swab = false; | |
903 | } | |
904 | ||
8051effc MD |
905 | /* setup bytes per word and fifo read/write functions */ |
906 | if (bits <= 8) { | |
907 | bytes_per_word = 1; | |
908 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
909 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
910 | } else if (bits <= 16) { | |
911 | bytes_per_word = 2; | |
0312d591 | 912 | if ((unsigned long)tx_buf & 0x01) |
8051effc MD |
913 | tx_fifo = sh_msiof_spi_write_fifo_16u; |
914 | else | |
915 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
916 | ||
0312d591 | 917 | if ((unsigned long)rx_buf & 0x01) |
8051effc MD |
918 | rx_fifo = sh_msiof_spi_read_fifo_16u; |
919 | else | |
920 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
921 | } else if (swab) { |
922 | bytes_per_word = 4; | |
0312d591 | 923 | if ((unsigned long)tx_buf & 0x03) |
9dabb3f3 GL |
924 | tx_fifo = sh_msiof_spi_write_fifo_s32u; |
925 | else | |
926 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
927 | ||
0312d591 | 928 | if ((unsigned long)rx_buf & 0x03) |
9dabb3f3 GL |
929 | rx_fifo = sh_msiof_spi_read_fifo_s32u; |
930 | else | |
931 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
932 | } else { |
933 | bytes_per_word = 4; | |
0312d591 | 934 | if ((unsigned long)tx_buf & 0x03) |
8051effc MD |
935 | tx_fifo = sh_msiof_spi_write_fifo_32u; |
936 | else | |
937 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
938 | ||
0312d591 | 939 | if ((unsigned long)rx_buf & 0x03) |
8051effc MD |
940 | rx_fifo = sh_msiof_spi_read_fifo_32u; |
941 | else | |
942 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
943 | } | |
944 | ||
8051effc | 945 | /* transfer in fifo sized chunks */ |
0312d591 GU |
946 | words = len / bytes_per_word; |
947 | ||
948 | while (words > 0) { | |
949 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, | |
8051effc MD |
950 | words, bits); |
951 | if (n < 0) | |
75b82e23 | 952 | return n; |
8051effc | 953 | |
0312d591 GU |
954 | if (tx_buf) |
955 | tx_buf += n * bytes_per_word; | |
956 | if (rx_buf) | |
957 | rx_buf += n * bytes_per_word; | |
8051effc MD |
958 | words -= n; |
959 | } | |
960 | ||
8051effc MD |
961 | return 0; |
962 | } | |
963 | ||
50a7e23f GU |
964 | static const struct sh_msiof_chipdata sh_data = { |
965 | .tx_fifo_size = 64, | |
966 | .rx_fifo_size = 64, | |
beb74bb0 GU |
967 | .master_flags = 0, |
968 | }; | |
969 | ||
970 | static const struct sh_msiof_chipdata r8a779x_data = { | |
971 | .tx_fifo_size = 64, | |
972 | .rx_fifo_size = 256, | |
973 | .master_flags = SPI_MASTER_MUST_TX, | |
50a7e23f GU |
974 | }; |
975 | ||
976 | static const struct of_device_id sh_msiof_match[] = { | |
977 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, | |
978 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, | |
beb74bb0 GU |
979 | { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, |
980 | { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, | |
e221cc99 GU |
981 | { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data }, |
982 | { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data }, | |
983 | { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data }, | |
50a7e23f GU |
984 | {}, |
985 | }; | |
986 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
987 | ||
cf9c86ef BH |
988 | #ifdef CONFIG_OF |
989 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
990 | { | |
991 | struct sh_msiof_spi_info *info; | |
992 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 993 | u32 num_cs = 1; |
cf9c86ef BH |
994 | |
995 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 996 | if (!info) |
cf9c86ef | 997 | return NULL; |
cf9c86ef BH |
998 | |
999 | /* Parse the MSIOF properties */ | |
1000 | of_property_read_u32(np, "num-cs", &num_cs); | |
1001 | of_property_read_u32(np, "renesas,tx-fifo-size", | |
1002 | &info->tx_fifo_override); | |
1003 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
1004 | &info->rx_fifo_override); | |
3110628d YS |
1005 | of_property_read_u32(np, "renesas,dtdl", &info->dtdl); |
1006 | of_property_read_u32(np, "renesas,syncdl", &info->syncdl); | |
cf9c86ef BH |
1007 | |
1008 | info->num_chipselect = num_cs; | |
1009 | ||
1010 | return info; | |
1011 | } | |
1012 | #else | |
1013 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
1014 | { | |
1015 | return NULL; | |
1016 | } | |
1017 | #endif | |
1018 | ||
b0d0ce8b GU |
1019 | static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, |
1020 | enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) | |
1021 | { | |
1022 | dma_cap_mask_t mask; | |
1023 | struct dma_chan *chan; | |
1024 | struct dma_slave_config cfg; | |
1025 | int ret; | |
1026 | ||
1027 | dma_cap_zero(mask); | |
1028 | dma_cap_set(DMA_SLAVE, mask); | |
1029 | ||
a6be4de6 GU |
1030 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
1031 | (void *)(unsigned long)id, dev, | |
1032 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
b0d0ce8b | 1033 | if (!chan) { |
a6be4de6 | 1034 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
b0d0ce8b GU |
1035 | return NULL; |
1036 | } | |
1037 | ||
1038 | memset(&cfg, 0, sizeof(cfg)); | |
1039 | cfg.slave_id = id; | |
1040 | cfg.direction = dir; | |
52fba2b8 | 1041 | if (dir == DMA_MEM_TO_DEV) { |
b0d0ce8b | 1042 | cfg.dst_addr = port_addr; |
52fba2b8 GU |
1043 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1044 | } else { | |
b0d0ce8b | 1045 | cfg.src_addr = port_addr; |
52fba2b8 GU |
1046 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1047 | } | |
b0d0ce8b GU |
1048 | |
1049 | ret = dmaengine_slave_config(chan, &cfg); | |
1050 | if (ret) { | |
1051 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
1052 | dma_release_channel(chan); | |
1053 | return NULL; | |
1054 | } | |
1055 | ||
1056 | return chan; | |
1057 | } | |
1058 | ||
1059 | static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) | |
1060 | { | |
1061 | struct platform_device *pdev = p->pdev; | |
1062 | struct device *dev = &pdev->dev; | |
1063 | const struct sh_msiof_spi_info *info = dev_get_platdata(dev); | |
a6be4de6 | 1064 | unsigned int dma_tx_id, dma_rx_id; |
b0d0ce8b GU |
1065 | const struct resource *res; |
1066 | struct spi_master *master; | |
5dabcf2f | 1067 | struct device *tx_dev, *rx_dev; |
b0d0ce8b | 1068 | |
a6be4de6 GU |
1069 | if (dev->of_node) { |
1070 | /* In the OF case we will get the slave IDs from the DT */ | |
1071 | dma_tx_id = 0; | |
1072 | dma_rx_id = 0; | |
1073 | } else if (info && info->dma_tx_id && info->dma_rx_id) { | |
1074 | dma_tx_id = info->dma_tx_id; | |
1075 | dma_rx_id = info->dma_rx_id; | |
1076 | } else { | |
1077 | /* The driver assumes no error */ | |
1078 | return 0; | |
1079 | } | |
b0d0ce8b GU |
1080 | |
1081 | /* The DMA engine uses the second register set, if present */ | |
1082 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1083 | if (!res) | |
1084 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1085 | ||
1086 | master = p->master; | |
1087 | master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, | |
a6be4de6 | 1088 | dma_tx_id, |
b0d0ce8b GU |
1089 | res->start + TFDR); |
1090 | if (!master->dma_tx) | |
1091 | return -ENODEV; | |
1092 | ||
1093 | master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, | |
a6be4de6 | 1094 | dma_rx_id, |
b0d0ce8b GU |
1095 | res->start + RFDR); |
1096 | if (!master->dma_rx) | |
1097 | goto free_tx_chan; | |
1098 | ||
1099 | p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1100 | if (!p->tx_dma_page) | |
1101 | goto free_rx_chan; | |
1102 | ||
1103 | p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1104 | if (!p->rx_dma_page) | |
1105 | goto free_tx_page; | |
1106 | ||
5dabcf2f GU |
1107 | tx_dev = master->dma_tx->device->dev; |
1108 | p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1109 | DMA_TO_DEVICE); |
5dabcf2f | 1110 | if (dma_mapping_error(tx_dev, p->tx_dma_addr)) |
b0d0ce8b GU |
1111 | goto free_rx_page; |
1112 | ||
5dabcf2f GU |
1113 | rx_dev = master->dma_rx->device->dev; |
1114 | p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1115 | DMA_FROM_DEVICE); |
5dabcf2f | 1116 | if (dma_mapping_error(rx_dev, p->rx_dma_addr)) |
b0d0ce8b GU |
1117 | goto unmap_tx_page; |
1118 | ||
1119 | dev_info(dev, "DMA available"); | |
1120 | return 0; | |
1121 | ||
1122 | unmap_tx_page: | |
5dabcf2f | 1123 | dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); |
b0d0ce8b GU |
1124 | free_rx_page: |
1125 | free_page((unsigned long)p->rx_dma_page); | |
1126 | free_tx_page: | |
1127 | free_page((unsigned long)p->tx_dma_page); | |
1128 | free_rx_chan: | |
1129 | dma_release_channel(master->dma_rx); | |
1130 | free_tx_chan: | |
1131 | dma_release_channel(master->dma_tx); | |
1132 | master->dma_tx = NULL; | |
1133 | return -ENODEV; | |
1134 | } | |
1135 | ||
1136 | static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) | |
1137 | { | |
1138 | struct spi_master *master = p->master; | |
1139 | struct device *dev; | |
1140 | ||
1141 | if (!master->dma_tx) | |
1142 | return; | |
1143 | ||
1144 | dev = &p->pdev->dev; | |
5dabcf2f GU |
1145 | dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, |
1146 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1147 | dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, | |
1148 | PAGE_SIZE, DMA_TO_DEVICE); | |
b0d0ce8b GU |
1149 | free_page((unsigned long)p->rx_dma_page); |
1150 | free_page((unsigned long)p->tx_dma_page); | |
1151 | dma_release_channel(master->dma_rx); | |
1152 | dma_release_channel(master->dma_tx); | |
1153 | } | |
1154 | ||
8051effc MD |
1155 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
1156 | { | |
1157 | struct resource *r; | |
1158 | struct spi_master *master; | |
50a7e23f | 1159 | const struct of_device_id *of_id; |
8051effc | 1160 | struct sh_msiof_spi_priv *p; |
8051effc MD |
1161 | int i; |
1162 | int ret; | |
1163 | ||
1164 | master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); | |
1165 | if (master == NULL) { | |
1166 | dev_err(&pdev->dev, "failed to allocate spi master\n"); | |
b4dd05de | 1167 | return -ENOMEM; |
8051effc MD |
1168 | } |
1169 | ||
1170 | p = spi_master_get_devdata(master); | |
1171 | ||
1172 | platform_set_drvdata(pdev, p); | |
b0d0ce8b | 1173 | p->master = master; |
50a7e23f GU |
1174 | |
1175 | of_id = of_match_device(sh_msiof_match, &pdev->dev); | |
1176 | if (of_id) { | |
1177 | p->chipdata = of_id->data; | |
cf9c86ef | 1178 | p->info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f GU |
1179 | } else { |
1180 | p->chipdata = (const void *)pdev->id_entry->driver_data; | |
8074cf06 | 1181 | p->info = dev_get_platdata(&pdev->dev); |
50a7e23f | 1182 | } |
cf9c86ef BH |
1183 | |
1184 | if (!p->info) { | |
1185 | dev_err(&pdev->dev, "failed to obtain device info\n"); | |
1186 | ret = -ENXIO; | |
1187 | goto err1; | |
1188 | } | |
1189 | ||
8051effc MD |
1190 | init_completion(&p->done); |
1191 | ||
b4dd05de | 1192 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 1193 | if (IS_ERR(p->clk)) { |
078b6ead | 1194 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
1195 | ret = PTR_ERR(p->clk); |
1196 | goto err1; | |
1197 | } | |
1198 | ||
8051effc | 1199 | i = platform_get_irq(pdev, 0); |
b4dd05de LP |
1200 | if (i < 0) { |
1201 | dev_err(&pdev->dev, "cannot get platform IRQ\n"); | |
8051effc | 1202 | ret = -ENOENT; |
b4dd05de | 1203 | goto err1; |
8051effc | 1204 | } |
b4dd05de LP |
1205 | |
1206 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1207 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
1208 | if (IS_ERR(p->mapbase)) { | |
1209 | ret = PTR_ERR(p->mapbase); | |
1210 | goto err1; | |
8051effc MD |
1211 | } |
1212 | ||
b4dd05de LP |
1213 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
1214 | dev_name(&pdev->dev), p); | |
8051effc MD |
1215 | if (ret) { |
1216 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 1217 | goto err1; |
8051effc MD |
1218 | } |
1219 | ||
1220 | p->pdev = pdev; | |
1221 | pm_runtime_enable(&pdev->dev); | |
1222 | ||
8051effc | 1223 | /* Platform data may override FIFO sizes */ |
50a7e23f GU |
1224 | p->tx_fifo_size = p->chipdata->tx_fifo_size; |
1225 | p->rx_fifo_size = p->chipdata->rx_fifo_size; | |
8051effc MD |
1226 | if (p->info->tx_fifo_override) |
1227 | p->tx_fifo_size = p->info->tx_fifo_override; | |
1228 | if (p->info->rx_fifo_override) | |
1229 | p->rx_fifo_size = p->info->rx_fifo_override; | |
1230 | ||
1bd6363b | 1231 | /* init master code */ |
8051effc MD |
1232 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1233 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
beb74bb0 | 1234 | master->flags = p->chipdata->master_flags; |
8051effc | 1235 | master->bus_num = pdev->id; |
f7c05e83 | 1236 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 1237 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 1238 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 1239 | master->prepare_message = sh_msiof_prepare_message; |
2416289c | 1240 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 1241 | master->auto_runtime_pm = true; |
1bd6363b | 1242 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 1243 | |
b0d0ce8b GU |
1244 | ret = sh_msiof_request_dma(p); |
1245 | if (ret < 0) | |
1246 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
1247 | ||
1bd6363b GU |
1248 | ret = devm_spi_register_master(&pdev->dev, master); |
1249 | if (ret < 0) { | |
1250 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
1251 | goto err2; | |
1252 | } | |
8051effc | 1253 | |
1bd6363b | 1254 | return 0; |
8051effc | 1255 | |
1bd6363b | 1256 | err2: |
b0d0ce8b | 1257 | sh_msiof_release_dma(p); |
8051effc | 1258 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
1259 | err1: |
1260 | spi_master_put(master); | |
8051effc MD |
1261 | return ret; |
1262 | } | |
1263 | ||
1264 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
1265 | { | |
b0d0ce8b GU |
1266 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); |
1267 | ||
1268 | sh_msiof_release_dma(p); | |
1bd6363b | 1269 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 1270 | return 0; |
8051effc MD |
1271 | } |
1272 | ||
50a7e23f GU |
1273 | static struct platform_device_id spi_driver_ids[] = { |
1274 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, | |
beb74bb0 GU |
1275 | { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, |
1276 | { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, | |
e221cc99 GU |
1277 | { "spi_r8a7792_msiof", (kernel_ulong_t)&r8a779x_data }, |
1278 | { "spi_r8a7793_msiof", (kernel_ulong_t)&r8a779x_data }, | |
1279 | { "spi_r8a7794_msiof", (kernel_ulong_t)&r8a779x_data }, | |
cf9c86ef BH |
1280 | {}, |
1281 | }; | |
50a7e23f | 1282 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 1283 | |
8051effc MD |
1284 | static struct platform_driver sh_msiof_spi_drv = { |
1285 | .probe = sh_msiof_spi_probe, | |
1286 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 1287 | .id_table = spi_driver_ids, |
8051effc MD |
1288 | .driver = { |
1289 | .name = "spi_sh_msiof", | |
691ee4ed | 1290 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
1291 | }, |
1292 | }; | |
940ab889 | 1293 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
1294 | |
1295 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
1296 | MODULE_AUTHOR("Magnus Damm"); | |
1297 | MODULE_LICENSE("GPL v2"); | |
1298 | MODULE_ALIAS("platform:spi_sh_msiof"); |