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1cc2df9d ZS |
1 | /* |
2 | * SPI bus driver for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/clk.h> | |
c908ef34 | 13 | #include <linux/completion.h> |
1cc2df9d ZS |
14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/bitops.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/of_gpio.h> | |
21 | #include <linux/spi/spi.h> | |
22 | #include <linux/spi/spi_bitbang.h> | |
de39f5fa BS |
23 | #include <linux/dmaengine.h> |
24 | #include <linux/dma-direction.h> | |
25 | #include <linux/dma-mapping.h> | |
1cc2df9d ZS |
26 | |
27 | #define DRIVER_NAME "sirfsoc_spi" | |
28 | ||
29 | #define SIRFSOC_SPI_CTRL 0x0000 | |
30 | #define SIRFSOC_SPI_CMD 0x0004 | |
31 | #define SIRFSOC_SPI_TX_RX_EN 0x0008 | |
32 | #define SIRFSOC_SPI_INT_EN 0x000C | |
33 | #define SIRFSOC_SPI_INT_STATUS 0x0010 | |
34 | #define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100 | |
35 | #define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104 | |
36 | #define SIRFSOC_SPI_TXFIFO_CTRL 0x0108 | |
37 | #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C | |
38 | #define SIRFSOC_SPI_TXFIFO_OP 0x0110 | |
39 | #define SIRFSOC_SPI_TXFIFO_STATUS 0x0114 | |
40 | #define SIRFSOC_SPI_TXFIFO_DATA 0x0118 | |
41 | #define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120 | |
42 | #define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124 | |
43 | #define SIRFSOC_SPI_RXFIFO_CTRL 0x0128 | |
44 | #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C | |
45 | #define SIRFSOC_SPI_RXFIFO_OP 0x0130 | |
46 | #define SIRFSOC_SPI_RXFIFO_STATUS 0x0134 | |
47 | #define SIRFSOC_SPI_RXFIFO_DATA 0x0138 | |
48 | #define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144 | |
49 | ||
50 | /* SPI CTRL register defines */ | |
51 | #define SIRFSOC_SPI_SLV_MODE BIT(16) | |
52 | #define SIRFSOC_SPI_CMD_MODE BIT(17) | |
53 | #define SIRFSOC_SPI_CS_IO_OUT BIT(18) | |
54 | #define SIRFSOC_SPI_CS_IO_MODE BIT(19) | |
55 | #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20) | |
56 | #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21) | |
57 | #define SIRFSOC_SPI_TRAN_MSB BIT(22) | |
58 | #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23) | |
59 | #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24) | |
60 | #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25) | |
61 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26) | |
62 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26) | |
63 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26) | |
64 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26) | |
65 | #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28) | |
66 | #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30) | |
67 | #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31) | |
68 | ||
69 | /* Interrupt Enable */ | |
70 | #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0) | |
71 | #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1) | |
72 | #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2) | |
73 | #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3) | |
74 | #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4) | |
75 | #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5) | |
76 | #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6) | |
77 | #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7) | |
78 | #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8) | |
79 | #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) | |
80 | #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) | |
81 | ||
82 | #define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF | |
83 | ||
84 | /* Interrupt status */ | |
85 | #define SIRFSOC_SPI_RX_DONE BIT(0) | |
86 | #define SIRFSOC_SPI_TX_DONE BIT(1) | |
87 | #define SIRFSOC_SPI_RX_OFLOW BIT(2) | |
88 | #define SIRFSOC_SPI_TX_UFLOW BIT(3) | |
89 | #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) | |
90 | #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) | |
91 | #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) | |
92 | #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9) | |
93 | #define SIRFSOC_SPI_FRM_END BIT(10) | |
94 | ||
95 | /* TX RX enable */ | |
96 | #define SIRFSOC_SPI_RX_EN BIT(0) | |
97 | #define SIRFSOC_SPI_TX_EN BIT(1) | |
98 | #define SIRFSOC_SPI_CMD_TX_EN BIT(2) | |
99 | ||
100 | #define SIRFSOC_SPI_IO_MODE_SEL BIT(0) | |
101 | #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2) | |
102 | ||
103 | /* FIFO OPs */ | |
104 | #define SIRFSOC_SPI_FIFO_RESET BIT(0) | |
105 | #define SIRFSOC_SPI_FIFO_START BIT(1) | |
106 | ||
107 | /* FIFO CTRL */ | |
108 | #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0) | |
109 | #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0) | |
110 | #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0) | |
111 | ||
112 | /* FIFO Status */ | |
113 | #define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF | |
114 | #define SIRFSOC_SPI_FIFO_FULL BIT(8) | |
115 | #define SIRFSOC_SPI_FIFO_EMPTY BIT(9) | |
116 | ||
117 | /* 256 bytes rx/tx FIFO */ | |
118 | #define SIRFSOC_SPI_FIFO_SIZE 256 | |
119 | #define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024) | |
120 | ||
121 | #define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F) | |
122 | #define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10) | |
123 | #define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20) | |
124 | #define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2) | |
125 | ||
de39f5fa BS |
126 | /* |
127 | * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma | |
128 | * due to the limitation of dma controller | |
129 | */ | |
130 | ||
131 | #define ALIGNED(x) (!((u32)x & 0x3)) | |
132 | #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \ | |
692fb0fe | 133 | ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE)) |
de39f5fa | 134 | |
eeb71395 QL |
135 | #define SIRFSOC_MAX_CMD_BYTES 4 |
136 | ||
1cc2df9d ZS |
137 | struct sirfsoc_spi { |
138 | struct spi_bitbang bitbang; | |
de39f5fa BS |
139 | struct completion rx_done; |
140 | struct completion tx_done; | |
1cc2df9d ZS |
141 | |
142 | void __iomem *base; | |
143 | u32 ctrl_freq; /* SPI controller clock speed */ | |
144 | struct clk *clk; | |
1cc2df9d ZS |
145 | |
146 | /* rx & tx bufs from the spi_transfer */ | |
147 | const void *tx; | |
148 | void *rx; | |
149 | ||
150 | /* place received word into rx buffer */ | |
151 | void (*rx_word) (struct sirfsoc_spi *); | |
152 | /* get word from tx buffer for sending */ | |
153 | void (*tx_word) (struct sirfsoc_spi *); | |
154 | ||
155 | /* number of words left to be tranmitted/received */ | |
692fb0fe QL |
156 | unsigned int left_tx_word; |
157 | unsigned int left_rx_word; | |
1cc2df9d | 158 | |
de39f5fa BS |
159 | /* rx & tx DMA channels */ |
160 | struct dma_chan *rx_chan; | |
161 | struct dma_chan *tx_chan; | |
162 | dma_addr_t src_start; | |
163 | dma_addr_t dst_start; | |
164 | void *dummypage; | |
165 | int word_width; /* in bytes */ | |
1cc2df9d | 166 | |
eeb71395 QL |
167 | /* |
168 | * if tx size is not more than 4 and rx size is NULL, use | |
169 | * command model | |
170 | */ | |
171 | bool tx_by_cmd; | |
172 | ||
1cc2df9d ZS |
173 | int chipselect[0]; |
174 | }; | |
175 | ||
176 | static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) | |
177 | { | |
178 | u32 data; | |
179 | u8 *rx = sspi->rx; | |
180 | ||
181 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
182 | ||
183 | if (rx) { | |
184 | *rx++ = (u8) data; | |
185 | sspi->rx = rx; | |
186 | } | |
187 | ||
692fb0fe | 188 | sspi->left_rx_word--; |
1cc2df9d ZS |
189 | } |
190 | ||
191 | static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) | |
192 | { | |
193 | u32 data = 0; | |
194 | const u8 *tx = sspi->tx; | |
195 | ||
196 | if (tx) { | |
197 | data = *tx++; | |
198 | sspi->tx = tx; | |
199 | } | |
200 | ||
201 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 202 | sspi->left_tx_word--; |
1cc2df9d ZS |
203 | } |
204 | ||
205 | static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) | |
206 | { | |
207 | u32 data; | |
208 | u16 *rx = sspi->rx; | |
209 | ||
210 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
211 | ||
212 | if (rx) { | |
213 | *rx++ = (u16) data; | |
214 | sspi->rx = rx; | |
215 | } | |
216 | ||
692fb0fe | 217 | sspi->left_rx_word--; |
1cc2df9d ZS |
218 | } |
219 | ||
220 | static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) | |
221 | { | |
222 | u32 data = 0; | |
223 | const u16 *tx = sspi->tx; | |
224 | ||
225 | if (tx) { | |
226 | data = *tx++; | |
227 | sspi->tx = tx; | |
228 | } | |
229 | ||
230 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 231 | sspi->left_tx_word--; |
1cc2df9d ZS |
232 | } |
233 | ||
234 | static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) | |
235 | { | |
236 | u32 data; | |
237 | u32 *rx = sspi->rx; | |
238 | ||
239 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
240 | ||
241 | if (rx) { | |
242 | *rx++ = (u32) data; | |
243 | sspi->rx = rx; | |
244 | } | |
245 | ||
692fb0fe | 246 | sspi->left_rx_word--; |
1cc2df9d ZS |
247 | |
248 | } | |
249 | ||
250 | static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) | |
251 | { | |
252 | u32 data = 0; | |
253 | const u32 *tx = sspi->tx; | |
254 | ||
255 | if (tx) { | |
256 | data = *tx++; | |
257 | sspi->tx = tx; | |
258 | } | |
259 | ||
260 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 261 | sspi->left_tx_word--; |
1cc2df9d ZS |
262 | } |
263 | ||
1cc2df9d ZS |
264 | static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) |
265 | { | |
266 | struct sirfsoc_spi *sspi = dev_id; | |
267 | u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); | |
268 | ||
269 | writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); | |
270 | ||
eeb71395 QL |
271 | if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) { |
272 | complete(&sspi->tx_done); | |
273 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); | |
274 | return IRQ_HANDLED; | |
275 | } | |
276 | ||
1cc2df9d ZS |
277 | /* Error Conditions */ |
278 | if (spi_stat & SIRFSOC_SPI_RX_OFLOW || | |
279 | spi_stat & SIRFSOC_SPI_TX_UFLOW) { | |
de39f5fa | 280 | complete(&sspi->rx_done); |
1cc2df9d ZS |
281 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
282 | } | |
283 | ||
237ce466 QL |
284 | if (spi_stat & (SIRFSOC_SPI_FRM_END |
285 | | SIRFSOC_SPI_RXFIFO_THD_REACH)) | |
1cc2df9d ZS |
286 | while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS) |
287 | & SIRFSOC_SPI_FIFO_EMPTY)) && | |
692fb0fe | 288 | sspi->left_rx_word) |
1cc2df9d ZS |
289 | sspi->rx_word(sspi); |
290 | ||
818e9162 QL |
291 | if (spi_stat & (SIRFSOC_SPI_TXFIFO_EMPTY | |
292 | SIRFSOC_SPI_TXFIFO_THD_REACH)) | |
237ce466 QL |
293 | while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) |
294 | & SIRFSOC_SPI_FIFO_FULL)) && | |
692fb0fe | 295 | sspi->left_tx_word) |
237ce466 | 296 | sspi->tx_word(sspi); |
1cc2df9d | 297 | |
237ce466 | 298 | /* Received all words */ |
692fb0fe | 299 | if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) { |
de39f5fa | 300 | complete(&sspi->rx_done); |
237ce466 QL |
301 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
302 | } | |
1cc2df9d ZS |
303 | return IRQ_HANDLED; |
304 | } | |
305 | ||
de39f5fa BS |
306 | static void spi_sirfsoc_dma_fini_callback(void *data) |
307 | { | |
308 | struct completion *dma_complete = data; | |
309 | ||
310 | complete(dma_complete); | |
311 | } | |
312 | ||
c908ef34 QL |
313 | static int spi_sirfsoc_cmd_transfer(struct spi_device *spi, |
314 | struct spi_transfer *t) | |
1cc2df9d ZS |
315 | { |
316 | struct sirfsoc_spi *sspi; | |
317 | int timeout = t->len * 10; | |
c908ef34 | 318 | u32 cmd; |
1cc2df9d | 319 | |
c908ef34 QL |
320 | sspi = spi_master_get_devdata(spi->master); |
321 | memcpy(&cmd, sspi->tx, t->len); | |
322 | if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) | |
323 | cmd = cpu_to_be32(cmd) >> | |
324 | ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8); | |
325 | if (sspi->word_width == 2 && t->len == 4 && | |
326 | (!(spi->mode & SPI_LSB_FIRST))) | |
327 | cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); | |
328 | writel(cmd, sspi->base + SIRFSOC_SPI_CMD); | |
329 | writel(SIRFSOC_SPI_FRM_END_INT_EN, | |
330 | sspi->base + SIRFSOC_SPI_INT_EN); | |
331 | writel(SIRFSOC_SPI_CMD_TX_EN, | |
332 | sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
333 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { | |
334 | dev_err(&spi->dev, "cmd transfer timeout\n"); | |
335 | return 0; | |
336 | } | |
eeb71395 | 337 | |
c908ef34 QL |
338 | return t->len; |
339 | } | |
eeb71395 | 340 | |
c908ef34 QL |
341 | static void spi_sirfsoc_dma_transfer(struct spi_device *spi, |
342 | struct spi_transfer *t) | |
343 | { | |
344 | struct sirfsoc_spi *sspi; | |
345 | struct dma_async_tx_descriptor *rx_desc, *tx_desc; | |
346 | int timeout = t->len * 10; | |
eeb71395 | 347 | |
c908ef34 QL |
348 | sspi = spi_master_get_devdata(spi->master); |
349 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
350 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
351 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
352 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
353 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); | |
354 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); | |
355 | if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) { | |
1cc2df9d | 356 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | |
c908ef34 | 357 | SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE, |
1cc2df9d | 358 | sspi->base + SIRFSOC_SPI_CTRL); |
692fb0fe QL |
359 | writel(sspi->left_tx_word - 1, |
360 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
361 | writel(sspi->left_tx_word - 1, | |
362 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
1cc2df9d ZS |
363 | } else { |
364 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL), | |
365 | sspi->base + SIRFSOC_SPI_CTRL); | |
366 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
367 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
368 | } | |
c908ef34 QL |
369 | sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, |
370 | (t->tx_buf != t->rx_buf) ? | |
371 | DMA_FROM_DEVICE : DMA_BIDIRECTIONAL); | |
372 | rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, | |
373 | sspi->dst_start, t->len, DMA_DEV_TO_MEM, | |
374 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
375 | rx_desc->callback = spi_sirfsoc_dma_fini_callback; | |
376 | rx_desc->callback_param = &sspi->rx_done; | |
377 | ||
378 | sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, | |
379 | (t->tx_buf != t->rx_buf) ? | |
380 | DMA_TO_DEVICE : DMA_BIDIRECTIONAL); | |
381 | tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, | |
382 | sspi->src_start, t->len, DMA_MEM_TO_DEV, | |
383 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
384 | tx_desc->callback = spi_sirfsoc_dma_fini_callback; | |
385 | tx_desc->callback_param = &sspi->tx_done; | |
386 | ||
387 | dmaengine_submit(tx_desc); | |
388 | dmaengine_submit(rx_desc); | |
389 | dma_async_issue_pending(sspi->tx_chan); | |
390 | dma_async_issue_pending(sspi->rx_chan); | |
d77ec5df QL |
391 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, |
392 | sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
c908ef34 | 393 | if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { |
1cc2df9d | 394 | dev_err(&spi->dev, "transfer timeout\n"); |
de39f5fa BS |
395 | dmaengine_terminate_all(sspi->rx_chan); |
396 | } else | |
692fb0fe | 397 | sspi->left_rx_word = 0; |
de39f5fa BS |
398 | /* |
399 | * we only wait tx-done event if transferring by DMA. for PIO, | |
400 | * we get rx data by writing tx data, so if rx is done, tx has | |
401 | * done earlier | |
402 | */ | |
c908ef34 QL |
403 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { |
404 | dev_err(&spi->dev, "transfer timeout\n"); | |
405 | dmaengine_terminate_all(sspi->tx_chan); | |
de39f5fa | 406 | } |
c908ef34 QL |
407 | dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE); |
408 | dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE); | |
409 | /* TX, RX FIFO stop */ | |
410 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
411 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
412 | if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX) | |
413 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
414 | } | |
de39f5fa | 415 | |
c908ef34 QL |
416 | static void spi_sirfsoc_pio_transfer(struct spi_device *spi, |
417 | struct spi_transfer *t) | |
418 | { | |
419 | struct sirfsoc_spi *sspi; | |
420 | int timeout = t->len * 10; | |
1cc2df9d | 421 | |
c908ef34 QL |
422 | sspi = spi_master_get_devdata(spi->master); |
423 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
424 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
425 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
426 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
427 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); | |
428 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); | |
429 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | SIRFSOC_SPI_MUL_DAT_MODE | | |
430 | SIRFSOC_SPI_ENA_AUTO_CLR, sspi->base + SIRFSOC_SPI_CTRL); | |
431 | writel(sspi->left_tx_word - 1, | |
432 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
433 | writel(sspi->left_rx_word - 1, | |
434 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
435 | sspi->tx_word(sspi); | |
436 | writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN | | |
437 | SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_RXFIFO_THD_INT_EN | | |
438 | SIRFSOC_SPI_TXFIFO_THD_INT_EN | SIRFSOC_SPI_FRM_END_INT_EN| | |
439 | SIRFSOC_SPI_RXFIFO_FULL_INT_EN, | |
440 | sspi->base + SIRFSOC_SPI_INT_EN); | |
441 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, | |
442 | sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
443 | if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) | |
444 | dev_err(&spi->dev, "transfer timeout\n"); | |
1cc2df9d ZS |
445 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
446 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
447 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
448 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); | |
c908ef34 QL |
449 | } |
450 | ||
451 | static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) | |
452 | { | |
453 | struct sirfsoc_spi *sspi; | |
454 | sspi = spi_master_get_devdata(spi->master); | |
455 | ||
456 | sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage; | |
457 | sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage; | |
458 | sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; | |
459 | reinit_completion(&sspi->rx_done); | |
460 | reinit_completion(&sspi->tx_done); | |
461 | /* | |
462 | * in the transfer, if transfer data using command register with rx_buf | |
463 | * null, just fill command data into command register and wait for its | |
464 | * completion. | |
465 | */ | |
466 | if (sspi->tx_by_cmd) | |
467 | spi_sirfsoc_cmd_transfer(spi, t); | |
468 | else if (IS_DMA_VALID(t)) | |
469 | spi_sirfsoc_dma_transfer(spi, t); | |
470 | else | |
471 | spi_sirfsoc_pio_transfer(spi, t); | |
1cc2df9d | 472 | |
692fb0fe | 473 | return t->len - sspi->left_rx_word * sspi->word_width; |
1cc2df9d ZS |
474 | } |
475 | ||
476 | static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) | |
477 | { | |
478 | struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); | |
479 | ||
480 | if (sspi->chipselect[spi->chip_select] == 0) { | |
481 | u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); | |
1cc2df9d ZS |
482 | switch (value) { |
483 | case BITBANG_CS_ACTIVE: | |
484 | if (spi->mode & SPI_CS_HIGH) | |
485 | regval |= SIRFSOC_SPI_CS_IO_OUT; | |
486 | else | |
487 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | |
488 | break; | |
489 | case BITBANG_CS_INACTIVE: | |
490 | if (spi->mode & SPI_CS_HIGH) | |
491 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | |
492 | else | |
493 | regval |= SIRFSOC_SPI_CS_IO_OUT; | |
494 | break; | |
495 | } | |
496 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); | |
497 | } else { | |
498 | int gpio = sspi->chipselect[spi->chip_select]; | |
6ee8a2f7 QL |
499 | switch (value) { |
500 | case BITBANG_CS_ACTIVE: | |
501 | gpio_direction_output(gpio, | |
502 | spi->mode & SPI_CS_HIGH ? 1 : 0); | |
503 | break; | |
504 | case BITBANG_CS_INACTIVE: | |
505 | gpio_direction_output(gpio, | |
506 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
507 | break; | |
508 | } | |
1cc2df9d ZS |
509 | } |
510 | } | |
511 | ||
512 | static int | |
513 | spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
514 | { | |
515 | struct sirfsoc_spi *sspi; | |
516 | u8 bits_per_word = 0; | |
517 | int hz = 0; | |
518 | u32 regval; | |
519 | u32 txfifo_ctrl, rxfifo_ctrl; | |
520 | u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; | |
521 | ||
522 | sspi = spi_master_get_devdata(spi->master); | |
523 | ||
766ed704 | 524 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
1cc2df9d ZS |
525 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; |
526 | ||
1cc2df9d | 527 | regval = (sspi->ctrl_freq / (2 * hz)) - 1; |
1cc2df9d ZS |
528 | if (regval > 0xFFFF || regval < 0) { |
529 | dev_err(&spi->dev, "Speed %d not supported\n", hz); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
533 | switch (bits_per_word) { | |
534 | case 8: | |
535 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; | |
536 | sspi->rx_word = spi_sirfsoc_rx_word_u8; | |
537 | sspi->tx_word = spi_sirfsoc_tx_word_u8; | |
1cc2df9d ZS |
538 | break; |
539 | case 12: | |
540 | case 16: | |
d77ec5df QL |
541 | regval |= (bits_per_word == 12) ? |
542 | SIRFSOC_SPI_TRAN_DAT_FORMAT_12 : | |
1cc2df9d ZS |
543 | SIRFSOC_SPI_TRAN_DAT_FORMAT_16; |
544 | sspi->rx_word = spi_sirfsoc_rx_word_u16; | |
545 | sspi->tx_word = spi_sirfsoc_tx_word_u16; | |
1cc2df9d ZS |
546 | break; |
547 | case 32: | |
548 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; | |
549 | sspi->rx_word = spi_sirfsoc_rx_word_u32; | |
550 | sspi->tx_word = spi_sirfsoc_tx_word_u32; | |
1cc2df9d | 551 | break; |
804ae438 AB |
552 | default: |
553 | BUG(); | |
1cc2df9d ZS |
554 | } |
555 | ||
8c328a26 AL |
556 | sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); |
557 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | |
558 | sspi->word_width; | |
559 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | |
560 | sspi->word_width; | |
561 | ||
1cc2df9d ZS |
562 | if (!(spi->mode & SPI_CS_HIGH)) |
563 | regval |= SIRFSOC_SPI_CS_IDLE_STAT; | |
564 | if (!(spi->mode & SPI_LSB_FIRST)) | |
565 | regval |= SIRFSOC_SPI_TRAN_MSB; | |
566 | if (spi->mode & SPI_CPOL) | |
567 | regval |= SIRFSOC_SPI_CLK_IDLE_STAT; | |
568 | ||
569 | /* | |
d77ec5df QL |
570 | * Data should be driven at least 1/2 cycle before the fetch edge |
571 | * to make sure that data gets stable at the fetch edge. | |
1cc2df9d ZS |
572 | */ |
573 | if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || | |
574 | (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) | |
575 | regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; | |
576 | else | |
577 | regval |= SIRFSOC_SPI_DRV_POS_EDGE; | |
578 | ||
579 | writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) | | |
580 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | |
581 | SIRFSOC_SPI_FIFO_HC(2), | |
582 | sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK); | |
583 | writel(SIRFSOC_SPI_FIFO_SC(2) | | |
584 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | |
585 | SIRFSOC_SPI_FIFO_HC(fifo_size - 2), | |
586 | sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK); | |
587 | writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); | |
588 | writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); | |
589 | ||
eeb71395 QL |
590 | if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) { |
591 | regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | | |
592 | SIRFSOC_SPI_CMD_MODE); | |
593 | sspi->tx_by_cmd = true; | |
594 | } else { | |
595 | regval &= ~SIRFSOC_SPI_CMD_MODE; | |
596 | sspi->tx_by_cmd = false; | |
597 | } | |
625227a4 QL |
598 | /* |
599 | * set spi controller in RISC chipselect mode, we are controlling CS by | |
600 | * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE. | |
601 | */ | |
602 | regval |= SIRFSOC_SPI_CS_IO_MODE; | |
1cc2df9d | 603 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); |
de39f5fa BS |
604 | |
605 | if (IS_DMA_VALID(t)) { | |
606 | /* Enable DMA mode for RX, TX */ | |
607 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); | |
d77ec5df QL |
608 | writel(SIRFSOC_SPI_RX_DMA_FLUSH, |
609 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); | |
de39f5fa BS |
610 | } else { |
611 | /* Enable IO mode for RX, TX */ | |
d77ec5df QL |
612 | writel(SIRFSOC_SPI_IO_MODE_SEL, |
613 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); | |
614 | writel(SIRFSOC_SPI_IO_MODE_SEL, | |
615 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); | |
de39f5fa BS |
616 | } |
617 | ||
1cc2df9d ZS |
618 | return 0; |
619 | } | |
620 | ||
621 | static int spi_sirfsoc_setup(struct spi_device *spi) | |
622 | { | |
1cc2df9d ZS |
623 | if (!spi->max_speed_hz) |
624 | return -EINVAL; | |
625 | ||
1cc2df9d ZS |
626 | return spi_sirfsoc_setup_transfer(spi, NULL); |
627 | } | |
628 | ||
fd4a319b | 629 | static int spi_sirfsoc_probe(struct platform_device *pdev) |
1cc2df9d ZS |
630 | { |
631 | struct sirfsoc_spi *sspi; | |
632 | struct spi_master *master; | |
633 | struct resource *mem_res; | |
634 | int num_cs, cs_gpio, irq; | |
635 | int i; | |
636 | int ret; | |
637 | ||
638 | ret = of_property_read_u32(pdev->dev.of_node, | |
639 | "sirf,spi-num-chipselects", &num_cs); | |
640 | if (ret < 0) { | |
641 | dev_err(&pdev->dev, "Unable to get chip select number\n"); | |
642 | goto err_cs; | |
643 | } | |
644 | ||
d77ec5df QL |
645 | master = spi_alloc_master(&pdev->dev, |
646 | sizeof(*sspi) + sizeof(int) * num_cs); | |
1cc2df9d ZS |
647 | if (!master) { |
648 | dev_err(&pdev->dev, "Unable to allocate SPI master\n"); | |
649 | return -ENOMEM; | |
650 | } | |
651 | platform_set_drvdata(pdev, master); | |
652 | sspi = spi_master_get_devdata(master); | |
653 | ||
1cc2df9d ZS |
654 | master->num_chipselect = num_cs; |
655 | ||
656 | for (i = 0; i < master->num_chipselect; i++) { | |
657 | cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i); | |
658 | if (cs_gpio < 0) { | |
659 | dev_err(&pdev->dev, "can't get cs gpio from DT\n"); | |
660 | ret = -ENODEV; | |
661 | goto free_master; | |
662 | } | |
663 | ||
664 | sspi->chipselect[i] = cs_gpio; | |
665 | if (cs_gpio == 0) | |
666 | continue; /* use cs from spi controller */ | |
667 | ||
668 | ret = gpio_request(cs_gpio, DRIVER_NAME); | |
669 | if (ret) { | |
670 | while (i > 0) { | |
671 | i--; | |
672 | if (sspi->chipselect[i] > 0) | |
673 | gpio_free(sspi->chipselect[i]); | |
674 | } | |
675 | dev_err(&pdev->dev, "fail to request cs gpios\n"); | |
676 | goto free_master; | |
677 | } | |
678 | } | |
679 | ||
2479790b | 680 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b0ee5605 TR |
681 | sspi->base = devm_ioremap_resource(&pdev->dev, mem_res); |
682 | if (IS_ERR(sspi->base)) { | |
683 | ret = PTR_ERR(sspi->base); | |
1cc2df9d ZS |
684 | goto free_master; |
685 | } | |
686 | ||
687 | irq = platform_get_irq(pdev, 0); | |
688 | if (irq < 0) { | |
689 | ret = -ENXIO; | |
690 | goto free_master; | |
691 | } | |
692 | ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, | |
693 | DRIVER_NAME, sspi); | |
694 | if (ret) | |
695 | goto free_master; | |
696 | ||
94c69f76 | 697 | sspi->bitbang.master = master; |
1cc2df9d ZS |
698 | sspi->bitbang.chipselect = spi_sirfsoc_chipselect; |
699 | sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; | |
700 | sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; | |
701 | sspi->bitbang.master->setup = spi_sirfsoc_setup; | |
702 | master->bus_num = pdev->id; | |
94b1f0df | 703 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; |
24778be2 SW |
704 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) | |
705 | SPI_BPW_MASK(16) | SPI_BPW_MASK(32); | |
1cc2df9d ZS |
706 | sspi->bitbang.master->dev.of_node = pdev->dev.of_node; |
707 | ||
de39f5fa | 708 | /* request DMA channels */ |
dd7243d6 | 709 | sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx"); |
de39f5fa BS |
710 | if (!sspi->rx_chan) { |
711 | dev_err(&pdev->dev, "can not allocate rx dma channel\n"); | |
6cca9e2d | 712 | ret = -ENODEV; |
de39f5fa BS |
713 | goto free_master; |
714 | } | |
dd7243d6 | 715 | sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx"); |
de39f5fa BS |
716 | if (!sspi->tx_chan) { |
717 | dev_err(&pdev->dev, "can not allocate tx dma channel\n"); | |
6cca9e2d | 718 | ret = -ENODEV; |
de39f5fa BS |
719 | goto free_rx_dma; |
720 | } | |
721 | ||
1cc2df9d ZS |
722 | sspi->clk = clk_get(&pdev->dev, NULL); |
723 | if (IS_ERR(sspi->clk)) { | |
de39f5fa BS |
724 | ret = PTR_ERR(sspi->clk); |
725 | goto free_tx_dma; | |
1cc2df9d | 726 | } |
e5118cd2 | 727 | clk_prepare_enable(sspi->clk); |
1cc2df9d ZS |
728 | sspi->ctrl_freq = clk_get_rate(sspi->clk); |
729 | ||
de39f5fa BS |
730 | init_completion(&sspi->rx_done); |
731 | init_completion(&sspi->tx_done); | |
1cc2df9d | 732 | |
1cc2df9d ZS |
733 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
734 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
735 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
736 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
737 | /* We are not using dummy delay between command and data */ | |
738 | writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL); | |
739 | ||
de39f5fa | 740 | sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL); |
6cca9e2d WY |
741 | if (!sspi->dummypage) { |
742 | ret = -ENOMEM; | |
de39f5fa | 743 | goto free_clk; |
6cca9e2d | 744 | } |
de39f5fa | 745 | |
1cc2df9d ZS |
746 | ret = spi_bitbang_start(&sspi->bitbang); |
747 | if (ret) | |
de39f5fa | 748 | goto free_dummypage; |
1cc2df9d ZS |
749 | |
750 | dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num); | |
751 | ||
752 | return 0; | |
de39f5fa BS |
753 | free_dummypage: |
754 | kfree(sspi->dummypage); | |
1cc2df9d | 755 | free_clk: |
e5118cd2 | 756 | clk_disable_unprepare(sspi->clk); |
1cc2df9d | 757 | clk_put(sspi->clk); |
de39f5fa BS |
758 | free_tx_dma: |
759 | dma_release_channel(sspi->tx_chan); | |
760 | free_rx_dma: | |
761 | dma_release_channel(sspi->rx_chan); | |
1cc2df9d ZS |
762 | free_master: |
763 | spi_master_put(master); | |
764 | err_cs: | |
765 | return ret; | |
766 | } | |
767 | ||
fd4a319b | 768 | static int spi_sirfsoc_remove(struct platform_device *pdev) |
1cc2df9d ZS |
769 | { |
770 | struct spi_master *master; | |
771 | struct sirfsoc_spi *sspi; | |
772 | int i; | |
773 | ||
774 | master = platform_get_drvdata(pdev); | |
775 | sspi = spi_master_get_devdata(master); | |
776 | ||
777 | spi_bitbang_stop(&sspi->bitbang); | |
778 | for (i = 0; i < master->num_chipselect; i++) { | |
779 | if (sspi->chipselect[i] > 0) | |
780 | gpio_free(sspi->chipselect[i]); | |
781 | } | |
de39f5fa | 782 | kfree(sspi->dummypage); |
e5118cd2 | 783 | clk_disable_unprepare(sspi->clk); |
1cc2df9d | 784 | clk_put(sspi->clk); |
de39f5fa BS |
785 | dma_release_channel(sspi->rx_chan); |
786 | dma_release_channel(sspi->tx_chan); | |
1cc2df9d ZS |
787 | spi_master_put(master); |
788 | return 0; | |
789 | } | |
790 | ||
facffed2 | 791 | #ifdef CONFIG_PM_SLEEP |
1cc2df9d ZS |
792 | static int spi_sirfsoc_suspend(struct device *dev) |
793 | { | |
a1216394 | 794 | struct spi_master *master = dev_get_drvdata(dev); |
1cc2df9d | 795 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
a82ba3a3 AL |
796 | int ret; |
797 | ||
798 | ret = spi_master_suspend(master); | |
799 | if (ret) | |
800 | return ret; | |
1cc2df9d ZS |
801 | |
802 | clk_disable(sspi->clk); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | static int spi_sirfsoc_resume(struct device *dev) | |
807 | { | |
a1216394 | 808 | struct spi_master *master = dev_get_drvdata(dev); |
1cc2df9d ZS |
809 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
810 | ||
811 | clk_enable(sspi->clk); | |
812 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
813 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
814 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
815 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
816 | ||
a82ba3a3 | 817 | return spi_master_resume(master); |
1cc2df9d | 818 | } |
facffed2 | 819 | #endif |
1cc2df9d | 820 | |
71aa2e32 JH |
821 | static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend, |
822 | spi_sirfsoc_resume); | |
1cc2df9d ZS |
823 | |
824 | static const struct of_device_id spi_sirfsoc_of_match[] = { | |
825 | { .compatible = "sirf,prima2-spi", }, | |
f3b8a8ec | 826 | { .compatible = "sirf,marco-spi", }, |
1cc2df9d ZS |
827 | {} |
828 | }; | |
3af4ed70 | 829 | MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); |
1cc2df9d ZS |
830 | |
831 | static struct platform_driver spi_sirfsoc_driver = { | |
832 | .driver = { | |
833 | .name = DRIVER_NAME, | |
834 | .owner = THIS_MODULE, | |
1cc2df9d | 835 | .pm = &spi_sirfsoc_pm_ops, |
1cc2df9d ZS |
836 | .of_match_table = spi_sirfsoc_of_match, |
837 | }, | |
838 | .probe = spi_sirfsoc_probe, | |
fd4a319b | 839 | .remove = spi_sirfsoc_remove, |
1cc2df9d ZS |
840 | }; |
841 | module_platform_driver(spi_sirfsoc_driver); | |
1cc2df9d | 842 | MODULE_DESCRIPTION("SiRF SoC SPI master driver"); |
d77ec5df QL |
843 | MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>"); |
844 | MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>"); | |
1cc2df9d | 845 | MODULE_LICENSE("GPL v2"); |