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spi: sirf: assign spi_master's max_speed_hz member
[deliverable/linux.git] / drivers / spi / spi-sirf.c
CommitLineData
1cc2df9d
ZS		 1/*
2 * SPI bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
c908ef34 13#include <linux/completion.h>
1cc2df9d
ZS		 14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/platform_device.h>
20#include <linux/of_gpio.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
de39f5fa
BS		 23#include <linux/dmaengine.h>
24#include <linux/dma-direction.h>
25#include <linux/dma-mapping.h>
1cc2df9d
ZS		 26
27#define DRIVER_NAME "sirfsoc_spi"
28
29#define SIRFSOC_SPI_CTRL 0x0000
30#define SIRFSOC_SPI_CMD 0x0004
31#define SIRFSOC_SPI_TX_RX_EN 0x0008
32#define SIRFSOC_SPI_INT_EN 0x000C
33#define SIRFSOC_SPI_INT_STATUS 0x0010
34#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
35#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
36#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
37#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
38#define SIRFSOC_SPI_TXFIFO_OP 0x0110
39#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
40#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
41#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
42#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
43#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
44#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
45#define SIRFSOC_SPI_RXFIFO_OP 0x0130
46#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
47#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
48#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
49
50/* SPI CTRL register defines */
51#define SIRFSOC_SPI_SLV_MODE BIT(16)
52#define SIRFSOC_SPI_CMD_MODE BIT(17)
53#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
54#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
55#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
56#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
57#define SIRFSOC_SPI_TRAN_MSB BIT(22)
58#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
59#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
60#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
62#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
63#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
64#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
9593e615
QL		 65#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
66#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
67#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
1cc2df9d
ZS		 68
69/* Interrupt Enable */
9593e615
QL		 70#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
71#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
72#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
73#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
1cc2df9d
ZS		 74#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
75#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
76#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
77#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
78#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
79#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
80#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
81
9593e615 82#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
1cc2df9d
ZS		 83
84/* Interrupt status */
85#define SIRFSOC_SPI_RX_DONE BIT(0)
86#define SIRFSOC_SPI_TX_DONE BIT(1)
87#define SIRFSOC_SPI_RX_OFLOW BIT(2)
88#define SIRFSOC_SPI_TX_UFLOW BIT(3)
41148c3a 89#define SIRFSOC_SPI_RX_IO_DMA BIT(4)
1cc2df9d
ZS		 90#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
91#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
92#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
93#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
94#define SIRFSOC_SPI_FRM_END BIT(10)
95
96/* TX RX enable */
97#define SIRFSOC_SPI_RX_EN BIT(0)
98#define SIRFSOC_SPI_TX_EN BIT(1)
99#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
100
101#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
102#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
103
104/* FIFO OPs */
105#define SIRFSOC_SPI_FIFO_RESET BIT(0)
106#define SIRFSOC_SPI_FIFO_START BIT(1)
107
108/* FIFO CTRL */
109#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
110#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
111#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
112
113/* FIFO Status */
114#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
115#define SIRFSOC_SPI_FIFO_FULL BIT(8)
116#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
117
118/* 256 bytes rx/tx FIFO */
119#define SIRFSOC_SPI_FIFO_SIZE 256
120#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
121
122#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
123#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
124#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
125#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
126
de39f5fa
BS		 127/*
128 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
129 * due to the limitation of dma controller
130 */
131
132#define ALIGNED(x) (!((u32)x & 0x3))
133#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
692fb0fe 134 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
de39f5fa 135
eeb71395 136#define SIRFSOC_MAX_CMD_BYTES 4
fcc50e5c 137#define SIRFSOC_SPI_DEFAULT_FRQ 1000000
eeb71395 138
1cc2df9d
ZS		 139struct sirfsoc_spi {
140 struct spi_bitbang bitbang;
de39f5fa
BS		 141 struct completion rx_done;
142 struct completion tx_done;
1cc2df9d
ZS		 143
144 void __iomem *base;
145 u32 ctrl_freq; /* SPI controller clock speed */
146 struct clk *clk;
1cc2df9d
ZS		 147
148 /* rx & tx bufs from the spi_transfer */
149 const void *tx;
150 void *rx;
151
152 /* place received word into rx buffer */
153 void (*rx_word) (struct sirfsoc_spi *);
154 /* get word from tx buffer for sending */
155 void (*tx_word) (struct sirfsoc_spi *);
156
157 /* number of words left to be tranmitted/received */
692fb0fe
QL		 158 unsigned int left_tx_word;
159 unsigned int left_rx_word;
1cc2df9d 160
de39f5fa
BS		 161 /* rx & tx DMA channels */
162 struct dma_chan *rx_chan;
163 struct dma_chan *tx_chan;
164 dma_addr_t src_start;
165 dma_addr_t dst_start;
166 void *dummypage;
167 int word_width; /* in bytes */
1cc2df9d 168
eeb71395
QL		 169 /*
170 * if tx size is not more than 4 and rx size is NULL, use
171 * command model
172 */
173 bool tx_by_cmd;
7850cdfc 174 bool hw_cs;
1cc2df9d
ZS		 175};
176
177static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
178{
179 u32 data;
180 u8 *rx = sspi->rx;
181
182 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
183
184 if (rx) {
185 *rx++ = (u8) data;
186 sspi->rx = rx;
187 }
188
692fb0fe 189 sspi->left_rx_word--;
1cc2df9d
ZS		 190}
191
192static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
193{
194 u32 data = 0;
195 const u8 *tx = sspi->tx;
196
197 if (tx) {
198 data = *tx++;
199 sspi->tx = tx;
200 }
201
202 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 203 sspi->left_tx_word--;
1cc2df9d
ZS		 204}
205
206static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
207{
208 u32 data;
209 u16 *rx = sspi->rx;
210
211 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
212
213 if (rx) {
214 *rx++ = (u16) data;
215 sspi->rx = rx;
216 }
217
692fb0fe 218 sspi->left_rx_word--;
1cc2df9d
ZS		 219}
220
221static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
222{
223 u32 data = 0;
224 const u16 *tx = sspi->tx;
225
226 if (tx) {
227 data = *tx++;
228 sspi->tx = tx;
229 }
230
231 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 232 sspi->left_tx_word--;
1cc2df9d
ZS		 233}
234
235static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
236{
237 u32 data;
238 u32 *rx = sspi->rx;
239
240 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
241
242 if (rx) {
243 *rx++ = (u32) data;
244 sspi->rx = rx;
245 }
246
692fb0fe 247 sspi->left_rx_word--;
1cc2df9d
ZS		 248
249}
250
251static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
252{
253 u32 data = 0;
254 const u32 *tx = sspi->tx;
255
256 if (tx) {
257 data = *tx++;
258 sspi->tx = tx;
259 }
260
261 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 262 sspi->left_tx_word--;
1cc2df9d
ZS		 263}
264
1cc2df9d
ZS		 265static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
266{
267 struct sirfsoc_spi *sspi = dev_id;
268 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
eeb71395
QL		 269 if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
270 complete(&sspi->tx_done);
271 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
41148c3a
QL		 272 writel(SIRFSOC_SPI_INT_MASK_ALL,
273 sspi->base + SIRFSOC_SPI_INT_STATUS);
eeb71395
QL		 274 return IRQ_HANDLED;
275 }
276
1cc2df9d
ZS		 277 /* Error Conditions */
278 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
279 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
41148c3a 280 complete(&sspi->tx_done);
de39f5fa 281 complete(&sspi->rx_done);
1cc2df9d 282 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
41148c3a
QL		 283 writel(SIRFSOC_SPI_INT_MASK_ALL,
284 sspi->base + SIRFSOC_SPI_INT_STATUS);
285 return IRQ_HANDLED;
1cc2df9d 286 }
41148c3a
QL		 287 if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
288 complete(&sspi->tx_done);
289 while (!(readl(sspi->base + SIRFSOC_SPI_INT_STATUS) &
290 SIRFSOC_SPI_RX_IO_DMA))
291 cpu_relax();
292 complete(&sspi->rx_done);
293 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
294 writel(SIRFSOC_SPI_INT_MASK_ALL,
295 sspi->base + SIRFSOC_SPI_INT_STATUS);
1cc2df9d 296
1cc2df9d
ZS		 297 return IRQ_HANDLED;
298}
299
de39f5fa
BS		 300static void spi_sirfsoc_dma_fini_callback(void *data)
301{
302 struct completion *dma_complete = data;
303
304 complete(dma_complete);
305}
306
0021d973 307static void spi_sirfsoc_cmd_transfer(struct spi_device *spi,
c908ef34 308 struct spi_transfer *t)
1cc2df9d
ZS		 309{
310 struct sirfsoc_spi *sspi;
311 int timeout = t->len * 10;
c908ef34 312 u32 cmd;
1cc2df9d 313
c908ef34 314 sspi = spi_master_get_devdata(spi->master);
810a58b0
QL		 315 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
316 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
c908ef34
QL		 317 memcpy(&cmd, sspi->tx, t->len);
318 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
319 cmd = cpu_to_be32(cmd) >>
320 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
321 if (sspi->word_width == 2 && t->len == 4 &&
322 (!(spi->mode & SPI_LSB_FIRST)))
323 cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
324 writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
325 writel(SIRFSOC_SPI_FRM_END_INT_EN,
326 sspi->base + SIRFSOC_SPI_INT_EN);
327 writel(SIRFSOC_SPI_CMD_TX_EN,
328 sspi->base + SIRFSOC_SPI_TX_RX_EN);
329 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
330 dev_err(&spi->dev, "cmd transfer timeout\n");
0021d973 331 return;
c908ef34 332 }
0021d973 333 sspi->left_rx_word -= t->len;
c908ef34 334}
eeb71395 335
c908ef34
QL		 336static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
337 struct spi_transfer *t)
338{
339 struct sirfsoc_spi *sspi;
340 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
341 int timeout = t->len * 10;
eeb71395 342
c908ef34
QL		 343 sspi = spi_master_get_devdata(spi->master);
344 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
345 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
346 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
347 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
348 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
349 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
350 if (sspi->left_tx_word < SIRFSOC_SPI_DAT_FRM_LEN_MAX) {
1cc2df9d 351 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
c908ef34 352 SIRFSOC_SPI_ENA_AUTO_CLR | SIRFSOC_SPI_MUL_DAT_MODE,
1cc2df9d 353 sspi->base + SIRFSOC_SPI_CTRL);
692fb0fe
QL		 354 writel(sspi->left_tx_word - 1,
355 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
356 writel(sspi->left_tx_word - 1,
357 sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
1cc2df9d
ZS		 358 } else {
359 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
360 sspi->base + SIRFSOC_SPI_CTRL);
361 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
362 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
363 }
c908ef34
QL		 364 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
365 (t->tx_buf != t->rx_buf) ?
366 DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
367 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
368 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
369 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
370 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
371 rx_desc->callback_param = &sspi->rx_done;
372
373 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
374 (t->tx_buf != t->rx_buf) ?
375 DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
376 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
377 sspi->src_start, t->len, DMA_MEM_TO_DEV,
378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
379 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
380 tx_desc->callback_param = &sspi->tx_done;
381
382 dmaengine_submit(tx_desc);
383 dmaengine_submit(rx_desc);
384 dma_async_issue_pending(sspi->tx_chan);
385 dma_async_issue_pending(sspi->rx_chan);
d77ec5df
QL		 386 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
387 sspi->base + SIRFSOC_SPI_TX_RX_EN);
c908ef34 388 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
1cc2df9d 389 dev_err(&spi->dev, "transfer timeout\n");
de39f5fa
BS		 390 dmaengine_terminate_all(sspi->rx_chan);
391 } else
692fb0fe 392 sspi->left_rx_word = 0;
de39f5fa
BS		 393 /*
394 * we only wait tx-done event if transferring by DMA. for PIO,
395 * we get rx data by writing tx data, so if rx is done, tx has
396 * done earlier
397 */
c908ef34
QL		 398 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
399 dev_err(&spi->dev, "transfer timeout\n");
400 dmaengine_terminate_all(sspi->tx_chan);
de39f5fa 401 }
c908ef34
QL		 402 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
403 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
404 /* TX, RX FIFO stop */
405 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
406 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
407 if (sspi->left_tx_word >= SIRFSOC_SPI_DAT_FRM_LEN_MAX)
408 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
409}
de39f5fa 410
c908ef34
QL		 411static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
412 struct spi_transfer *t)
413{
414 struct sirfsoc_spi *sspi;
415 int timeout = t->len * 10;
1cc2df9d 416
c908ef34 417 sspi = spi_master_get_devdata(spi->master);
41148c3a
QL		 418 do {
419 writel(SIRFSOC_SPI_FIFO_RESET,
420 sspi->base + SIRFSOC_SPI_RXFIFO_OP);
421 writel(SIRFSOC_SPI_FIFO_RESET,
422 sspi->base + SIRFSOC_SPI_TXFIFO_OP);
423 writel(SIRFSOC_SPI_FIFO_START,
424 sspi->base + SIRFSOC_SPI_RXFIFO_OP);
425 writel(SIRFSOC_SPI_FIFO_START,
426 sspi->base + SIRFSOC_SPI_TXFIFO_OP);
427 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
428 writel(SIRFSOC_SPI_INT_MASK_ALL,
429 sspi->base + SIRFSOC_SPI_INT_STATUS);
430 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
431 SIRFSOC_SPI_MUL_DAT_MODE | SIRFSOC_SPI_ENA_AUTO_CLR,
432 sspi->base + SIRFSOC_SPI_CTRL);
433 writel(min(sspi->left_tx_word, (u32)(256 / sspi->word_width))
434 - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
435 writel(min(sspi->left_rx_word, (u32)(256 / sspi->word_width))
436 - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
437 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
438 & SIRFSOC_SPI_FIFO_FULL)) && sspi->left_tx_word)
439 sspi->tx_word(sspi);
440 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
441 SIRFSOC_SPI_TX_UFLOW_INT_EN |
f2a08b40
QL		 442 SIRFSOC_SPI_RX_OFLOW_INT_EN |
443 SIRFSOC_SPI_RX_IO_DMA_INT_EN,
41148c3a
QL		 444 sspi->base + SIRFSOC_SPI_INT_EN);
445 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
c908ef34 446 sspi->base + SIRFSOC_SPI_TX_RX_EN);
41148c3a
QL		 447 if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
448 !wait_for_completion_timeout(&sspi->rx_done, timeout)) {
449 dev_err(&spi->dev, "transfer timeout\n");
450 break;
451 }
452 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
453 & SIRFSOC_SPI_FIFO_EMPTY)) && sspi->left_rx_word)
454 sspi->rx_word(sspi);
455 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
456 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
457 } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
c908ef34
QL		 458}
459
460static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
461{
462 struct sirfsoc_spi *sspi;
463 sspi = spi_master_get_devdata(spi->master);
464
465 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
466 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
467 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
468 reinit_completion(&sspi->rx_done);
469 reinit_completion(&sspi->tx_done);
470 /*
471 * in the transfer, if transfer data using command register with rx_buf
472 * null, just fill command data into command register and wait for its
473 * completion.
474 */
475 if (sspi->tx_by_cmd)
476 spi_sirfsoc_cmd_transfer(spi, t);
477 else if (IS_DMA_VALID(t))
478 spi_sirfsoc_dma_transfer(spi, t);
479 else
480 spi_sirfsoc_pio_transfer(spi, t);
1cc2df9d 481
692fb0fe 482 return t->len - sspi->left_rx_word * sspi->word_width;
1cc2df9d
ZS		 483}
484
485static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
486{
487 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
488
7850cdfc 489 if (sspi->hw_cs) {
1cc2df9d 490 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
1cc2df9d
ZS		 491 switch (value) {
492 case BITBANG_CS_ACTIVE:
493 if (spi->mode & SPI_CS_HIGH)
494 regval |= SIRFSOC_SPI_CS_IO_OUT;
495 else
496 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
497 break;
498 case BITBANG_CS_INACTIVE:
499 if (spi->mode & SPI_CS_HIGH)
500 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
501 else
502 regval |= SIRFSOC_SPI_CS_IO_OUT;
503 break;
504 }
505 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
506 } else {
6ee8a2f7
QL		 507 switch (value) {
508 case BITBANG_CS_ACTIVE:
7850cdfc 509 gpio_direction_output(spi->cs_gpio,
6ee8a2f7
QL		 510 spi->mode & SPI_CS_HIGH ? 1 : 0);
511 break;
512 case BITBANG_CS_INACTIVE:
7850cdfc 513 gpio_direction_output(spi->cs_gpio,
6ee8a2f7
QL		 514 spi->mode & SPI_CS_HIGH ? 0 : 1);
515 break;
516 }
1cc2df9d
ZS		 517 }
518}
519
520static int
521spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
522{
523 struct sirfsoc_spi *sspi;
524 u8 bits_per_word = 0;
525 int hz = 0;
526 u32 regval;
527 u32 txfifo_ctrl, rxfifo_ctrl;
528 u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
529
530 sspi = spi_master_get_devdata(spi->master);
531
766ed704 532 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
1cc2df9d
ZS		 533 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
534
1cc2df9d 535 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
1cc2df9d
ZS		 536 if (regval > 0xFFFF || regval < 0) {
537 dev_err(&spi->dev, "Speed %d not supported\n", hz);
538 return -EINVAL;
539 }
540
541 switch (bits_per_word) {
542 case 8:
543 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
544 sspi->rx_word = spi_sirfsoc_rx_word_u8;
545 sspi->tx_word = spi_sirfsoc_tx_word_u8;
1cc2df9d
ZS		 546 break;
547 case 12:
548 case 16:
d77ec5df
QL		 549 regval |= (bits_per_word == 12) ?
550 SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
1cc2df9d
ZS		 551 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
552 sspi->rx_word = spi_sirfsoc_rx_word_u16;
553 sspi->tx_word = spi_sirfsoc_tx_word_u16;
1cc2df9d
ZS		 554 break;
555 case 32:
556 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
557 sspi->rx_word = spi_sirfsoc_rx_word_u32;
558 sspi->tx_word = spi_sirfsoc_tx_word_u32;
1cc2df9d 559 break;
804ae438
AB		 560 default:
561 BUG();
1cc2df9d
ZS		 562 }
563
8c328a26
AL		 564 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
565 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
566 sspi->word_width;
567 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
568 sspi->word_width;
569
1cc2df9d
ZS		 570 if (!(spi->mode & SPI_CS_HIGH))
571 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
572 if (!(spi->mode & SPI_LSB_FIRST))
573 regval |= SIRFSOC_SPI_TRAN_MSB;
574 if (spi->mode & SPI_CPOL)
575 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
576
577 /*
d77ec5df
QL		 578 * Data should be driven at least 1/2 cycle before the fetch edge
579 * to make sure that data gets stable at the fetch edge.
1cc2df9d
ZS		 580 */
581 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
582 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
583 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
584 else
585 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
586
587 writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
588 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
589 SIRFSOC_SPI_FIFO_HC(2),
590 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
591 writel(SIRFSOC_SPI_FIFO_SC(2) |
592 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
593 SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
594 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
595 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
596 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
597
eeb71395
QL		 598 if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
599 regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
600 SIRFSOC_SPI_CMD_MODE);
601 sspi->tx_by_cmd = true;
602 } else {
603 regval &= ~SIRFSOC_SPI_CMD_MODE;
604 sspi->tx_by_cmd = false;
605 }
625227a4 606 /*
7850cdfc
QL		 607 * it should never set to hardware cs mode because in hardware cs mode,
608 * cs signal can't controlled by driver.
625227a4
QL		 609 */
610 regval |= SIRFSOC_SPI_CS_IO_MODE;
1cc2df9d 611 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
de39f5fa
BS		 612
613 if (IS_DMA_VALID(t)) {
614 /* Enable DMA mode for RX, TX */
615 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
d77ec5df
QL		 616 writel(SIRFSOC_SPI_RX_DMA_FLUSH,
617 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
de39f5fa
BS		 618 } else {
619 /* Enable IO mode for RX, TX */
d77ec5df
QL		 620 writel(SIRFSOC_SPI_IO_MODE_SEL,
621 sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
622 writel(SIRFSOC_SPI_IO_MODE_SEL,
623 sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
de39f5fa
BS		 624 }
625
1cc2df9d
ZS		 626 return 0;
627}
628
629static int spi_sirfsoc_setup(struct spi_device *spi)
630{
7850cdfc
QL		 631 struct sirfsoc_spi *sspi;
632
7850cdfc
QL		 633 sspi = spi_master_get_devdata(spi->master);
634
635 if (spi->cs_gpio == -ENOENT)
636 sspi->hw_cs = true;
637 else
638 sspi->hw_cs = false;
1cc2df9d
ZS		 639 return spi_sirfsoc_setup_transfer(spi, NULL);
640}
641
fd4a319b 642static int spi_sirfsoc_probe(struct platform_device *pdev)
1cc2df9d
ZS		 643{
644 struct sirfsoc_spi *sspi;
645 struct spi_master *master;
646 struct resource *mem_res;
7850cdfc
QL		 647 int irq;
648 int i, ret;
1cc2df9d 649
7850cdfc 650 master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
1cc2df9d
ZS		 651 if (!master) {
652 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
653 return -ENOMEM;
654 }
655 platform_set_drvdata(pdev, master);
656 sspi = spi_master_get_devdata(master);
657
2479790b 658 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b0ee5605
TR		 659 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
660 if (IS_ERR(sspi->base)) {
661 ret = PTR_ERR(sspi->base);
1cc2df9d
ZS		 662 goto free_master;
663 }
664
665 irq = platform_get_irq(pdev, 0);
666 if (irq < 0) {
667 ret = -ENXIO;
668 goto free_master;
669 }
670 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
671 DRIVER_NAME, sspi);
672 if (ret)
673 goto free_master;
674
94c69f76 675 sspi->bitbang.master = master;
1cc2df9d
ZS		 676 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
677 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
678 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
679 sspi->bitbang.master->setup = spi_sirfsoc_setup;
680 master->bus_num = pdev->id;
94b1f0df 681 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
24778be2
SW		 682 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
683 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
fcc50e5c 684 master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
1cc2df9d
ZS		 685 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
686
de39f5fa 687 /* request DMA channels */
dd7243d6 688 sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
de39f5fa
BS		 689 if (!sspi->rx_chan) {
690 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
6cca9e2d 691 ret = -ENODEV;
de39f5fa
BS		 692 goto free_master;
693 }
dd7243d6 694 sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx");
de39f5fa
BS		 695 if (!sspi->tx_chan) {
696 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
6cca9e2d 697 ret = -ENODEV;
de39f5fa
BS		 698 goto free_rx_dma;
699 }
700
1cc2df9d
ZS		 701 sspi->clk = clk_get(&pdev->dev, NULL);
702 if (IS_ERR(sspi->clk)) {
de39f5fa
BS		 703 ret = PTR_ERR(sspi->clk);
704 goto free_tx_dma;
1cc2df9d 705 }
e5118cd2 706 clk_prepare_enable(sspi->clk);
1cc2df9d
ZS		 707 sspi->ctrl_freq = clk_get_rate(sspi->clk);
708
de39f5fa
BS		 709 init_completion(&sspi->rx_done);
710 init_completion(&sspi->tx_done);
1cc2df9d 711
1cc2df9d
ZS		 712 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
713 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
714 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
715 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
716 /* We are not using dummy delay between command and data */
717 writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
718
de39f5fa 719 sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
6cca9e2d
WY		 720 if (!sspi->dummypage) {
721 ret = -ENOMEM;
de39f5fa 722 goto free_clk;
6cca9e2d 723 }
de39f5fa 724
1cc2df9d
ZS		 725 ret = spi_bitbang_start(&sspi->bitbang);
726 if (ret)
de39f5fa 727 goto free_dummypage;
7850cdfc
QL		 728 for (i = 0; master->cs_gpios && i < master->num_chipselect; i++) {
729 if (master->cs_gpios[i] == -ENOENT)
730 continue;
731 if (!gpio_is_valid(master->cs_gpios[i])) {
732 dev_err(&pdev->dev, "no valid gpio\n");
733 ret = -EINVAL;
734 goto free_dummypage;
735 }
736 ret = devm_gpio_request(&pdev->dev,
737 master->cs_gpios[i], DRIVER_NAME);
738 if (ret) {
739 dev_err(&pdev->dev, "failed to request gpio\n");
740 goto free_dummypage;
741 }
742 }
1cc2df9d
ZS		 743 dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
744
745 return 0;
de39f5fa
BS		 746free_dummypage:
747 kfree(sspi->dummypage);
1cc2df9d 748free_clk:
e5118cd2 749 clk_disable_unprepare(sspi->clk);
1cc2df9d 750 clk_put(sspi->clk);
de39f5fa
BS		 751free_tx_dma:
752 dma_release_channel(sspi->tx_chan);
753free_rx_dma:
754 dma_release_channel(sspi->rx_chan);
1cc2df9d
ZS		 755free_master:
756 spi_master_put(master);
7850cdfc 757
1cc2df9d
ZS		 758 return ret;
759}
760
fd4a319b 761static int spi_sirfsoc_remove(struct platform_device *pdev)
1cc2df9d
ZS		 762{
763 struct spi_master *master;
764 struct sirfsoc_spi *sspi;
1cc2df9d
ZS		 765
766 master = platform_get_drvdata(pdev);
767 sspi = spi_master_get_devdata(master);
768
769 spi_bitbang_stop(&sspi->bitbang);
de39f5fa 770 kfree(sspi->dummypage);
e5118cd2 771 clk_disable_unprepare(sspi->clk);
1cc2df9d 772 clk_put(sspi->clk);
de39f5fa
BS		 773 dma_release_channel(sspi->rx_chan);
774 dma_release_channel(sspi->tx_chan);
1cc2df9d
ZS		 775 spi_master_put(master);
776 return 0;
777}
778
facffed2 779#ifdef CONFIG_PM_SLEEP
1cc2df9d
ZS		 780static int spi_sirfsoc_suspend(struct device *dev)
781{
a1216394 782 struct spi_master *master = dev_get_drvdata(dev);
1cc2df9d 783 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
a82ba3a3
AL		 784 int ret;
785
786 ret = spi_master_suspend(master);
787 if (ret)
788 return ret;
1cc2df9d
ZS		 789
790 clk_disable(sspi->clk);
791 return 0;
792}
793
794static int spi_sirfsoc_resume(struct device *dev)
795{
a1216394 796 struct spi_master *master = dev_get_drvdata(dev);
1cc2df9d
ZS		 797 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
798
799 clk_enable(sspi->clk);
800 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
801 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
802 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
803 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
804
a82ba3a3 805 return spi_master_resume(master);
1cc2df9d 806}
facffed2 807#endif
1cc2df9d 808
71aa2e32
JH		 809static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
810 spi_sirfsoc_resume);
1cc2df9d
ZS		 811
812static const struct of_device_id spi_sirfsoc_of_match[] = {
813 { .compatible = "sirf,prima2-spi", },
f3b8a8ec 814 { .compatible = "sirf,marco-spi", },
1cc2df9d
ZS		 815 {}
816};
3af4ed70 817MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
1cc2df9d
ZS		 818
819static struct platform_driver spi_sirfsoc_driver = {
820 .driver = {
821 .name = DRIVER_NAME,
822 .owner = THIS_MODULE,
1cc2df9d 823 .pm = &spi_sirfsoc_pm_ops,
1cc2df9d
ZS		 824 .of_match_table = spi_sirfsoc_of_match,
825 },
826 .probe = spi_sirfsoc_probe,
fd4a319b 827 .remove = spi_sirfsoc_remove,
1cc2df9d
ZS		 828};
829module_platform_driver(spi_sirfsoc_driver);
1cc2df9d 830MODULE_DESCRIPTION("SiRF SoC SPI master driver");
d77ec5df
QL		 831MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
832MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
1cc2df9d 833MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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